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Merge pull request #353 from lnis-uofu/testbench_patch 

Bug fix on the reset stimuli generator
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tangxifan 2021-07-01 21:10:40 -06:00 committed by GitHub
parent a2cb153d54 d0e4f8521f
commit 947f078a7e
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1 changed files with 1 additions and 1 deletions
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openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
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@ -230,7 +230,7 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp,
*/ */
fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl;
fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl;
print_verilog_wire_connection(fp, reset_port, reset_port, true); print_verilog_register_connection(fp, reset_port, reset_port, true);
fp << "\tend" << std::endl; fp << "\tend" << std::endl;
} }