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Merge pull request #256 from lnis-uofu/bump_yosys_1 

Bumping up latest yosys changes to yosys submodule
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tpagarani 2021-03-01 04:23:21 -05:00 committed by GitHub
parent c50eacd449 ea4aee8cb2
commit 8e89da5966
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4 changed files with 4 additions and 3 deletions
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2
openfpga_flow/misc/qlf_yosys.ys
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@ -2,5 +2,5 @@
# Read verilog files
${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -openfpga -top ${TOP_MODULE}
synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE}

2
openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

1
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
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@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_circuit_format=eblif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

2
yosys

@ -1 +1 @@
Subproject commit 19f4184a60b4e43f61c54236e7149a40b587d656
Subproject commit 3a9968de914973f65928b724e889b134f8a4f2ae