From ff7c9bb3c6f16293e1293a1e089a490173f86e9d Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 28 Feb 2021 20:55:55 -0800 Subject: [PATCH 1/3] Bumping up latest yosys changes to yosys submodule --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 19f4184a6..3a9968de9 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 19f4184a60b4e43f61c54236e7149a40b587d656 +Subproject commit 3a9968de914973f65928b724e889b134f8a4f2ae From 0038496d9c425015513621543142134a55f7a26a Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 28 Feb 2021 21:08:47 -0800 Subject: [PATCH 2/3] Replacing -openfpga with -family qlf_k4n8 --- openfpga_flow/misc/qlf_yosys.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index cccd220b9..b5169287e 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -2,5 +2,5 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${OUTPUT_BLIF} -openfpga -top ${TOP_MODULE} +synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -top ${TOP_MODULE} From ea4aee8cb257705e0844bd8a38d0416b844220fd Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 28 Feb 2021 22:07:23 -0800 Subject: [PATCH 3/3] For time-being yosys script running in no_adder mode. --- openfpga_flow/misc/qlf_yosys.ys | 2 +- .../quicklogic_flow_example_script.openfpga | 2 +- openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index b5169287e..131bddd3c 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -2,5 +2,5 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -top ${TOP_MODULE} +synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE} diff --git a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga index c9ae60b56..414fd8d47 100644 --- a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 38c047162..71529c23b 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_circuit_format=eblif [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml