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fine-tune micro benchmark to fit port mapping in testbenches

This commit is contained in:
tangxifan 2020-04-19 17:05:12 -06:00
parent e10cafe0a5
commit 8b03ec900f
2 changed files with 4 additions and 3 deletions
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2
openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
View File

@ -1,9 +1,9 @@
`timescale 1ns / 1ps
module top(
clk,
a,
b,
clk,
c,
d);

5
openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
View File

@ -21,8 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
[BENCHMARKS]
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
# Modelsim is ok with this but icarus fails due to poor support on timing and looping
#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
[SYNTHESIS_PARAM]
bench0_top = top