From 8b03ec900ff23dfc7461dfc414ebdd461174e51c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 19 Apr 2020 17:05:12 -0600 Subject: [PATCH] fine-tune micro benchmark to fit port mapping in testbenches --- .../benchmarks/micro_benchmark/and_latch/and_latch.v | 2 +- openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v index 893cdf7a4..a8f147f5b 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v +++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v @@ -1,9 +1,9 @@ `timescale 1ns / 1ps module top( - clk, a, b, + clk, c, d); diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf index cd002c9d4..76c70bb6c 100644 --- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf @@ -21,8 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif +# Modelsim is ok with this but icarus fails due to poor support on timing and looping +#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif [SYNTHESIS_PARAM] bench0_top = top