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[Script] Bug fix in slow clock frequency in shift register chain contraints

This commit is contained in:
tangxifan 2021-10-06 16:49:01 -07:00
parent 40b589dc6d
commit 8aa2647878
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
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@ -7,7 +7,7 @@
<openfpga_simulation_setting> <openfpga_simulation_setting>
<clock_setting> <clock_setting>
<operating frequency="auto" num_cycles="auto" slack="0.2"/> <operating frequency="auto" num_cycles="auto" slack="0.2"/>
<programming frequency="100e6"> <programming frequency="10e6">
<clock name="bl_sr_clock" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/> <clock name="bl_sr_clock" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
<clock name="wl_sr_clock" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/> <clock name="wl_sr_clock" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
</programming> </programming>