From 8aa2647878601bb43aa70f1e7ebd2360b81e9e15 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 Oct 2021 16:49:01 -0700
Subject: [PATCH] [Script] Bug fix in slow clock frequency in shift register
 chain contraints

---
 .../fixed_shift_register_sim_openfpga.xml                       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml b/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
index a3b5b88de..0687db6cf 100644
--- a/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
+++ b/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
@@ -7,7 +7,7 @@
 <openfpga_simulation_setting>
   <clock_setting>
     <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <programming frequency="100e6">
+    <programming frequency="10e6">
       <clock name="bl_sr_clock" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
       <clock name="wl_sr_clock" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
     </programming>