riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

deploy power gating test cases to CI

This commit is contained in:
tangxifan 2020-07-22 20:22:59 -06:00
parent 22159531c5
commit 8a79ff2c24
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.travis/verilog_reg_test.sh
View File

@ -75,6 +75,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_vanilla_key -
python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_random_key --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_random_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/load_external_key --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/load_external_key --debug --show_thread_logs
echo -e "Testing Power-gating designs";
python3 openfpga_flow/scripts/run_fpga_task.py power_gated_design/power_gated_inverter --show_thread_logs --debug
# Verify MCNC big20 benchmark suite with ModelSim # Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment # Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail # Otherwise, it will fail