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[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use

This commit is contained in:
tangxifan 2021-06-09 10:49:00 -06:00
parent be26c06673
commit 89fb672631
2 changed files with 8 additions and 2 deletions
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6
openfpga/src/base/openfpga_verilog.cpp
View File

@ -256,7 +256,8 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) { const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_file = cmd.option("file");
CommandOptionId opt_hdl_dir = cmd.option("hdl_dir");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_verbose = cmd.option("verbose");
@ -264,9 +265,10 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
* Keep it independent from any other outside data structures * Keep it independent from any other outside data structures
*/ */
VerilogTestbenchOption options; VerilogTestbenchOption options;
options.set_output_directory(cmd_context.option_value(cmd, opt_hdl_dir));
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark)); options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_output_dir)); options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file));
return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(), return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(),
openfpga_ctx.bitstream_manager(), openfpga_ctx.bitstream_manager(),

4
openfpga/src/base/openfpga_verilog_command.cpp
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@ -281,6 +281,10 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell<O
shell_cmd.set_option_short_name(output_opt, "f"); shell_cmd.set_option_short_name(output_opt, "f");
shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
/* Add an option '--hdl_dir'*/
CommandOptionId hdl_dir_opt = shell_cmd.add_option("hdl_dir", true, "Specify the directory path where HDL netlists are created");
shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING);
/* Add an option '--reference_benchmark_file_path'*/ /* Add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist"); CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);