From 89fb67263179c1477fb7f6c18df9f1aafa4cef2a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 9 Jun 2021 10:49:00 -0600
Subject: [PATCH] [Tool] Fine-tune the options of 'write_simulation_task_info'
 to be straightforward to use

---
 openfpga/src/base/openfpga_verilog.cpp         | 6 ++++--
 openfpga/src/base/openfpga_verilog_command.cpp | 4 ++++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index f3b6a7d9a..50cd9ba87 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -256,7 +256,8 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
 int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
                                const Command& cmd, const CommandContext& cmd_context) {
 
-  CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_file = cmd.option("file");
+  CommandOptionId opt_hdl_dir = cmd.option("hdl_dir");
   CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
@@ -264,9 +265,10 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
    * Keep it independent from any other outside data structures
    */
   VerilogTestbenchOption options;
+  options.set_output_directory(cmd_context.option_value(cmd, opt_hdl_dir));
   options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
-  options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_output_dir));
+  options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file));
 
   return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(),
                                            openfpga_ctx.bitstream_manager(),
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index 72115e987..471e8784b 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -281,6 +281,10 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell<O
   shell_cmd.set_option_short_name(output_opt, "f");
   shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
 
+  /* Add an option '--hdl_dir'*/
+  CommandOptionId hdl_dir_opt = shell_cmd.add_option("hdl_dir", true, "Specify the directory path where HDL netlists are created");
+  shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING);
+
   /* Add an option '--reference_benchmark_file_path'*/
   CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
   shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);