[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
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@ -173,7 +173,7 @@
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<port type="input" prefix="D" lib_name="SIN" size="1"/>
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<port type="input" prefix="D" lib_name="SIN" size="1"/>
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<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
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<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
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<port type="bl" prefix="BL" lib_name="BL" size="1"/>
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<port type="bl" prefix="BL" lib_name="BL" size="1"/>
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<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
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<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
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</circuit_model>
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</circuit_model>
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<!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
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<!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
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<circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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@ -185,7 +185,7 @@
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<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
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<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
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<port type="wl" prefix="wl" lib_name="WLW" size="1"/>
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<port type="wl" prefix="wl" lib_name="WLW" size="1"/>
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<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
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<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
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<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
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<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
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</circuit_model>
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</circuit_model>
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</circuit_library>
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</circuit_library>
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<configuration_protocol>
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<configuration_protocol>
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