diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
index a21c0e522..803512e5d 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
@@ -173,7 +173,7 @@
        <port type="input" prefix="D" lib_name="SIN" size="1"/>
        <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
        <port type="bl" prefix="BL" lib_name="BL" size="1"/>
-       <port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
+       <port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
     </circuit_model>
     <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
     <circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
@@ -185,7 +185,7 @@
        <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
        <port type="wl" prefix="wl" lib_name="WLW" size="1"/>
        <port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
-       <port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
+       <port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>