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[Test] Deploy new test to CI

This commit is contained in:
tangxifan 2021-02-28 16:18:46 -07:00
parent b90a17543d
commit 86930d63d3
1 changed files with 3 additions and 1 deletions
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4
openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -94,14 +94,16 @@ run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
echo -e "Testing Verilog generation with behavioral description"; echo -e "Testing Verilog generation with behavioral description";
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog_default_nettype_wire --debug --show_thread_logs
echo -e "Testing synthesizable Verilog generation with external standard cells"; echo -e "Testing synthesizable Verilog generation with external standard cells";
run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs
echo -e "Testing implicit Verilog generation"; echo -e "Testing implicit Verilog generation";
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire --debug --show_thread_logs
echo -e "Testing implicit Verilog generation"; echo -e "Testing explicit Verilog generation";
run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire --debug --show_thread_logs
echo -e "Testing Verilog generation with flatten routing modules"; echo -e "Testing Verilog generation with flatten routing modules";