From 86930d63d34e89acc3fedd9c6fb1dd710e81d36c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 28 Feb 2021 16:18:46 -0700 Subject: [PATCH] [Test] Deploy new test to CI --- .../regression_test_scripts/fpga_verilog_reg_test.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 16226c299..450bc262c 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -94,14 +94,16 @@ run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs echo -e "Testing Verilog generation with behavioral description"; run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog_default_nettype_wire --debug --show_thread_logs echo -e "Testing synthesizable Verilog generation with external standard cells"; run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs echo -e "Testing implicit Verilog generation"; run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire --debug --show_thread_logs -echo -e "Testing implicit Verilog generation"; +echo -e "Testing explicit Verilog generation"; run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire --debug --show_thread_logs echo -e "Testing Verilog generation with flatten routing modules";