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typos fixed;

This commit is contained in:
Nachiket Kapre 2021-02-08 22:03:14 -05:00
parent d040ba569c
commit 853bf8af43
2 changed files with 2 additions and 2 deletions
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2
openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
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@ -40,7 +40,7 @@
10e-12 10e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/buf.v"> <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/buf4.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/> <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>

2
openfpga_flow/openfpga_cell_library/verilog/dffsrq.v
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@ -25,7 +25,7 @@ output reg [0:0] Q;
always @(posedge CK) begin always @(posedge CK) begin
if(RST) begin if(RST) begin
Q <= 1'b0; Q <= 1'b0;
else if(SET) begin end else if(SET) begin
Q <= 1'b1; Q <= 1'b1;
end else begin end else begin
Q <= D; Q <= D;