diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
index 6d7b080f1..50c2769ad 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
@@ -40,7 +40,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/buf.v">
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/buf4.v">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v
index c466740c6..cff8848a9 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v
@@ -25,7 +25,7 @@ output reg [0:0] Q;
 always @(posedge CK) begin
   if(RST) begin
     Q <= 1'b0;
-  else if(SET) begin
+  end else if(SET) begin
     Q <= 1'b1;
   end else begin
     Q <= D;