riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Doc] Update VPR arch naming convention

This commit is contained in:
tangxifan 2022-03-20 10:08:30 +08:00
parent 48ec5abed6
commit 851a20f495
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
openfpga_flow/vpr_arch/README.md
View File

@ -26,6 +26,8 @@ Please reveal the following architecture features in the names to help quickly s
* Top-left (Tl): the pins of a tile are placed on the top side and left side only
* Top-right (Tr): the pins of a tile are placed on the top side and right side only
* Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only
- GlobalTile<Int>Clk: How many clocks are defined through global ports from physical tiles. <Int> is the number of clocks
- GlobalTile<Int>Clk<Port>: How many clocks are defined through global ports from physical tiles.
* <Int> is the number of clocks.
* <Port> means each clock pin belongs to a separated port. When not specified, all the clock pins are grouped in one port
Other features are used in naming should be listed here.