From 851a20f49599d95bd79b15d61c42b67d51a375ba Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 20 Mar 2022 10:08:30 +0800 Subject: [PATCH] [Doc] Update VPR arch naming convention --- openfpga_flow/vpr_arch/README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 8fb2b1fbe..90a54240f 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -26,6 +26,8 @@ Please reveal the following architecture features in the names to help quickly s * Top-left (Tl): the pins of a tile are placed on the top side and left side only * Top-right (Tr): the pins of a tile are placed on the top side and right side only * Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only -- GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks +- GlobalTileClk: How many clocks are defined through global ports from physical tiles. + * is the number of clocks. + * means each clock pin belongs to a separated port. When not specified, all the clock pins are grouped in one port Other features are used in naming should be listed here.