Merge branch 'master' into enable-advanced-quicklogic-tests

.github/workflows/build.yml

@@ -170,12 +170,8 @@ jobs:
             openfpga/openfpga
             vpr/libvpr.a
             vpr/vpr
-            yosys/install/share/
-            yosys/install/bin/yosys
-            yosys/install/bin/yosys-abc
-            yosys/install/bin/yosys-config
-            yosys/install/bin/yosys-filterlib
-            yosys/install/bin/yosys-smtbmc
+            yosys/install/share
+            yosys/install/bin
             openfpga_flow
             openfpga.sh
   docker_distribution:

CMakeLists.txt

@@ -227,6 +227,10 @@ include(CheckCCompilerFlag)
 include(CheckCXXCompilerFlag)
 #
 
+# we will check if yosys already exist. if not then build it
+if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys)
+    message(STATUS "Yosys pre-build exist so skipping it")
+else ()
 # run makefile provided, we pass-on the options to the local make file 
 add_custom_target(
     yosys ALL 
@@ -248,6 +252,7 @@ add_custom_target(
 )
 
 add_dependencies(yosys-plugins yosys)
+endif()
 
 # run make to extract compiler options, linker options and list of source files
 #add_custom_target(

docs/source/contact.rst

@@ -13,9 +13,11 @@ Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC:
 
 Dr. Xifan Tang
 
-xifan.tang@utah.edu
+xifan@osfpga.org
 
-.. Technical Details about layout auto-generation
-.. Edouard Giacomin
-.. edouard.giacomin@utah.edu
+Technical Details about physical design
+
+Ganesh Gore
+
+ganesh.gore@utah.edu