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fix formatting

This commit is contained in:
Duck Deux 2024-10-31 01:48:24 -07:00
parent 1877779a99
commit 82c010593d
1 changed files with 4 additions and 3 deletions
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7
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
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@ -87,7 +87,8 @@ static void build_switch_block_mux_bitstream(
break; break;
} }
} }
} else if (false == circuit_lib.mux_add_const_input(mux_model) && prefer_unused_mux_input) { } else if (false == circuit_lib.mux_add_const_input(mux_model) &&
prefer_unused_mux_input) {
/* If /* If
* 1. output net is INVALID (unmapped) * 1. output net is INVALID (unmapped)
* 2. and we don't have a constant input, * 2. and we don't have a constant input,
@ -102,7 +103,7 @@ static void build_switch_block_mux_bitstream(
/* Warn if all inputs were mapped */ /* Warn if all inputs were mapped */
if (path_id == DEFAULT_PATH_ID) { if (path_id == DEFAULT_PATH_ID) {
VTR_LOGV_WARN( VTR_LOGV_WARN(
verbose, verbose,
"At RRNodeId = %d: output is unmapped but all inputs are mapped?", "At RRNodeId = %d: output is unmapped but all inputs are mapped?",
cur_rr_node); cur_rr_node);
} }
@ -342,7 +343,7 @@ static void build_connection_block_mux_bitstream(
RREdgeId edge = driver_rr_edges[iedge]; RREdgeId edge = driver_rr_edges[iedge];
RRNodeId driver_node = rr_graph.edge_src_node(edge); RRNodeId driver_node = rr_graph.edge_src_node(edge);
if (routing_annotation.rr_node_net(driver_node) == if (routing_annotation.rr_node_net(driver_node) ==
ClusterNetId::INVALID()){ ClusterNetId::INVALID()) {
path_id = iedge; path_id = iedge;
break; break;
} }