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[Tool] Update FPGA-SDC to use the new data structure for global ports

This commit is contained in:
tangxifan 2020-11-10 21:17:17 -07:00
parent 2c269c532a
commit 81e56d45d6
5 changed files with 37 additions and 34 deletions
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7
openfpga/src/base/openfpga_sdc.cpp
View File

@ -80,11 +80,6 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
options.set_generate_sdc_pnr(true);
}
/* Collect global ports from the circuit library:
* TODO: should we place this in the OpenFPGA context?
*/
std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(openfpga_ctx.arch().circuit_lib);
/* Execute only when sdc is enabled */
if (true == options.generate_sdc_pnr()) {
print_pnr_sdc(options,
@ -96,7 +91,7 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
openfpga_ctx.module_graph(),
openfpga_ctx.mux_lib(),
openfpga_ctx.arch().circuit_lib,
global_ports,
openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.flow_manager().compress_routing());
}

39
openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp
View File

@ -61,21 +61,22 @@ static
void print_pnr_sdc_global_clock_ports(std::fstream& fp,
const float& programming_critical_path_delay,
const float& operating_critical_path_delay,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports) {
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& fabric_global_port_info) {
valid_file_stream(fp);
/* Get clock port from the global port */
for (const CircuitPortId& clock_port : global_ports) {
if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) {
for (const FabricGlobalPortId& global_port : fabric_global_port_info.global_ports()) {
if (false == fabric_global_port_info.global_port_is_clock(global_port)) {
continue;
}
/* Reach here, it means a clock port and we need print constraints */
float clock_period = operating_critical_path_delay;
/* For programming clock, we give a fixed period */
if (true == circuit_lib.port_is_prog(clock_port)) {
if (true == fabric_global_port_info.global_port_is_prog(global_port)) {
clock_period = programming_critical_path_delay;
/* Print comments */
fp << "##################################################" << std::endl;
@ -88,8 +89,9 @@ void print_pnr_sdc_global_clock_ports(std::fstream& fp,
fp << "##################################################" << std::endl;
}
for (const size_t& pin : circuit_lib.pins(clock_port)) {
BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin);
BasicPort clock_port = module_manager.module_port(top_module, fabric_global_port_info.global_module_port(global_port));
for (const size_t& pin : clock_port.pins()) {
BasicPort port_to_constrain(clock_port.get_name(), pin, pin);
print_pnr_sdc_clock_port(fp,
port_to_constrain,
@ -109,14 +111,15 @@ void print_pnr_sdc_global_clock_ports(std::fstream& fp,
static
void print_pnr_sdc_global_non_clock_ports(std::fstream& fp,
const float& operating_critical_path_delay,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports) {
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& fabric_global_port_info) {
valid_file_stream(fp);
/* For non-clock port from the global port: give a fixed period */
for (const CircuitPortId& global_port : global_ports) {
if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) {
for (const FabricGlobalPortId& global_port : fabric_global_port_info.global_ports()) {
if (true == fabric_global_port_info.global_port_is_clock(global_port)) {
continue;
}
@ -127,8 +130,9 @@ void print_pnr_sdc_global_non_clock_ports(std::fstream& fp,
/* Reach here, it means a non-clock global port and we need print constraints */
float clock_period = operating_critical_path_delay;
for (const size_t& pin : circuit_lib.pins(global_port)) {
BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
BasicPort non_clock_port = module_manager.module_port(top_module, fabric_global_port_info.global_module_port(global_port));
for (const size_t& pin : non_clock_port.pins()) {
BasicPort port_to_constrain(non_clock_port.get_name(), pin, pin);
print_pnr_sdc_clock_port(fp,
port_to_constrain,
@ -151,8 +155,9 @@ void print_pnr_sdc_global_non_clock_ports(std::fstream& fp,
void print_pnr_sdc_global_ports(const std::string& sdc_dir,
const float& programming_critical_path_delay,
const float& operating_critical_path_delay,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports,
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& global_ports,
const bool& constrain_non_clock_port) {
/* Create the file name for Verilog netlist */
@ -174,13 +179,13 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
print_pnr_sdc_global_clock_ports(fp,
programming_critical_path_delay,
operating_critical_path_delay,
circuit_lib,
module_manager, top_module,
global_ports);
if (true == constrain_non_clock_port) {
print_pnr_sdc_global_non_clock_ports(fp,
operating_critical_path_delay,
circuit_lib,
module_manager, top_module,
global_ports);
}

8
openfpga/src/fpga_sdc/pnr_sdc_global_port.h
View File

@ -6,7 +6,8 @@
*******************************************************************/
#include <string>
#include <vector>
#include "circuit_library.h"
#include "module_manager.h"
#include "fabric_global_port_info.h"
/********************************************************************
* Function declaration
@ -18,8 +19,9 @@ namespace openfpga {
void print_pnr_sdc_global_ports(const std::string& sdc_dir,
const float& programming_critical_path_delay,
const float& operating_critical_path_delay,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports,
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& global_ports,
const bool& constrain_non_clock_port);
} /* end namespace openfpga */

14
openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
View File

@ -327,22 +327,22 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
const ModuleManager& module_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports,
const FabricGlobalPortInfo& global_ports,
const bool& compact_routing_hierarchy) {
std::string top_module_name = generate_fpga_top_module_name();
ModuleId top_module = module_manager.find_module(top_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
/* Constrain global ports */
if (true == sdc_options.constrain_global_port()) {
print_pnr_sdc_global_ports(sdc_options.sdc_dir(),
programming_critical_path_delay,
operating_critical_path_delay,
circuit_lib, global_ports,
module_manager, top_module, global_ports,
sdc_options.constrain_non_clock_global_port());
}
std::string top_module_name = generate_fpga_top_module_name();
ModuleId top_module = module_manager.find_module(top_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
/* Output Design Constraints to disable outputs of memory cells */
if (true == sdc_options.constrain_configurable_memory_outputs()) {
print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(),

3
openfpga/src/fpga_sdc/pnr_sdc_writer.h
View File

@ -12,6 +12,7 @@
#include "module_manager.h"
#include "mux_library.h"
#include "circuit_library.h"
#include "fabric_global_port_info.h"
#include "pnr_sdc_option.h"
/********************************************************************
@ -30,7 +31,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
const ModuleManager& module_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports,
const FabricGlobalPortInfo& global_ports,
const bool& compact_routing_hierarchy);
} /* end namespace openfpga */