From 81e56d45d6ea7baf283be5d79060cd526a0e6bd8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 10 Nov 2020 21:17:17 -0700 Subject: [PATCH] [Tool] Update FPGA-SDC to use the new data structure for global ports --- openfpga/src/base/openfpga_sdc.cpp | 7 +--- openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp | 39 +++++++++++-------- openfpga/src/fpga_sdc/pnr_sdc_global_port.h | 8 ++-- openfpga/src/fpga_sdc/pnr_sdc_writer.cpp | 14 +++---- openfpga/src/fpga_sdc/pnr_sdc_writer.h | 3 +- 5 files changed, 37 insertions(+), 34 deletions(-) diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp index 5cb88220b..f82e0656f 100644 --- a/openfpga/src/base/openfpga_sdc.cpp +++ b/openfpga/src/base/openfpga_sdc.cpp @@ -80,11 +80,6 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx, options.set_generate_sdc_pnr(true); } - /* Collect global ports from the circuit library: - * TODO: should we place this in the OpenFPGA context? - */ - std::vector global_ports = find_circuit_library_global_ports(openfpga_ctx.arch().circuit_lib); - /* Execute only when sdc is enabled */ if (true == options.generate_sdc_pnr()) { print_pnr_sdc(options, @@ -96,7 +91,7 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx, openfpga_ctx.module_graph(), openfpga_ctx.mux_lib(), openfpga_ctx.arch().circuit_lib, - global_ports, + openfpga_ctx.fabric_global_port_info(), openfpga_ctx.flow_manager().compress_routing()); } diff --git a/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp b/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp index 4e6ef4925..d258ca640 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp @@ -61,21 +61,22 @@ static void print_pnr_sdc_global_clock_ports(std::fstream& fp, const float& programming_critical_path_delay, const float& operating_critical_path_delay, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports) { + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricGlobalPortInfo& fabric_global_port_info) { valid_file_stream(fp); /* Get clock port from the global port */ - for (const CircuitPortId& clock_port : global_ports) { - if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) { + for (const FabricGlobalPortId& global_port : fabric_global_port_info.global_ports()) { + if (false == fabric_global_port_info.global_port_is_clock(global_port)) { continue; } /* Reach here, it means a clock port and we need print constraints */ float clock_period = operating_critical_path_delay; /* For programming clock, we give a fixed period */ - if (true == circuit_lib.port_is_prog(clock_port)) { + if (true == fabric_global_port_info.global_port_is_prog(global_port)) { clock_period = programming_critical_path_delay; /* Print comments */ fp << "##################################################" << std::endl; @@ -88,8 +89,9 @@ void print_pnr_sdc_global_clock_ports(std::fstream& fp, fp << "##################################################" << std::endl; } - for (const size_t& pin : circuit_lib.pins(clock_port)) { - BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin); + BasicPort clock_port = module_manager.module_port(top_module, fabric_global_port_info.global_module_port(global_port)); + for (const size_t& pin : clock_port.pins()) { + BasicPort port_to_constrain(clock_port.get_name(), pin, pin); print_pnr_sdc_clock_port(fp, port_to_constrain, @@ -109,14 +111,15 @@ void print_pnr_sdc_global_clock_ports(std::fstream& fp, static void print_pnr_sdc_global_non_clock_ports(std::fstream& fp, const float& operating_critical_path_delay, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports) { + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricGlobalPortInfo& fabric_global_port_info) { valid_file_stream(fp); /* For non-clock port from the global port: give a fixed period */ - for (const CircuitPortId& global_port : global_ports) { - if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) { + for (const FabricGlobalPortId& global_port : fabric_global_port_info.global_ports()) { + if (true == fabric_global_port_info.global_port_is_clock(global_port)) { continue; } @@ -127,8 +130,9 @@ void print_pnr_sdc_global_non_clock_ports(std::fstream& fp, /* Reach here, it means a non-clock global port and we need print constraints */ float clock_period = operating_critical_path_delay; - for (const size_t& pin : circuit_lib.pins(global_port)) { - BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin); + BasicPort non_clock_port = module_manager.module_port(top_module, fabric_global_port_info.global_module_port(global_port)); + for (const size_t& pin : non_clock_port.pins()) { + BasicPort port_to_constrain(non_clock_port.get_name(), pin, pin); print_pnr_sdc_clock_port(fp, port_to_constrain, @@ -151,8 +155,9 @@ void print_pnr_sdc_global_non_clock_ports(std::fstream& fp, void print_pnr_sdc_global_ports(const std::string& sdc_dir, const float& programming_critical_path_delay, const float& operating_critical_path_delay, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricGlobalPortInfo& global_ports, const bool& constrain_non_clock_port) { /* Create the file name for Verilog netlist */ @@ -174,13 +179,13 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir, print_pnr_sdc_global_clock_ports(fp, programming_critical_path_delay, operating_critical_path_delay, - circuit_lib, + module_manager, top_module, global_ports); if (true == constrain_non_clock_port) { print_pnr_sdc_global_non_clock_ports(fp, operating_critical_path_delay, - circuit_lib, + module_manager, top_module, global_ports); } diff --git a/openfpga/src/fpga_sdc/pnr_sdc_global_port.h b/openfpga/src/fpga_sdc/pnr_sdc_global_port.h index 444482106..e17dd0d9b 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_global_port.h +++ b/openfpga/src/fpga_sdc/pnr_sdc_global_port.h @@ -6,7 +6,8 @@ *******************************************************************/ #include #include -#include "circuit_library.h" +#include "module_manager.h" +#include "fabric_global_port_info.h" /******************************************************************** * Function declaration @@ -18,8 +19,9 @@ namespace openfpga { void print_pnr_sdc_global_ports(const std::string& sdc_dir, const float& programming_critical_path_delay, const float& operating_critical_path_delay, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricGlobalPortInfo& global_ports, const bool& constrain_non_clock_port); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp index c02988462..d6596eba1 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp @@ -327,22 +327,22 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options, const ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::vector& global_ports, + const FabricGlobalPortInfo& global_ports, const bool& compact_routing_hierarchy) { - + + std::string top_module_name = generate_fpga_top_module_name(); + ModuleId top_module = module_manager.find_module(top_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + /* Constrain global ports */ if (true == sdc_options.constrain_global_port()) { print_pnr_sdc_global_ports(sdc_options.sdc_dir(), programming_critical_path_delay, operating_critical_path_delay, - circuit_lib, global_ports, + module_manager, top_module, global_ports, sdc_options.constrain_non_clock_global_port()); } - std::string top_module_name = generate_fpga_top_module_name(); - ModuleId top_module = module_manager.find_module(top_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(top_module)); - /* Output Design Constraints to disable outputs of memory cells */ if (true == sdc_options.constrain_configurable_memory_outputs()) { print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_writer.h index 1016d57da..38aff2a2c 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_writer.h +++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.h @@ -12,6 +12,7 @@ #include "module_manager.h" #include "mux_library.h" #include "circuit_library.h" +#include "fabric_global_port_info.h" #include "pnr_sdc_option.h" /******************************************************************** @@ -30,7 +31,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options, const ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::vector& global_ports, + const FabricGlobalPortInfo& global_ports, const bool& compact_routing_hierarchy); } /* end namespace openfpga */