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2
.github/workflows/build.yml vendored
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@ -210,6 +210,7 @@ jobs:
- name: fpga_bitstream_reg_test
- name: fpga_sdc_reg_test
- name: fpga_spice_reg_test
- name: micro_benchmark_reg_test
- name: quicklogic_reg_test
- name: vtr_benchmark_reg_test
- name: iwls_benchmark_reg_test
@ -257,6 +258,7 @@ jobs:
- name: fpga_bitstream_reg_test
- name: fpga_sdc_reg_test
- name: fpga_spice_reg_test
- name: micro_benchmark_reg_test
- name: quicklogic_reg_test
- name: vtr_benchmark_reg_test
- name: iwls_benchmark_reg_test

10
docs/source/manual/file_formats/pin_constraints_file.rst
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@ -10,7 +10,7 @@ An example of design constraints is shown as follows.
.. code-block:: xml
<pin_constraints>
<set_io pin="clk[0]" net="clk0"/>
<set_io pin="clk[0]" net="clk0" default_value="1"/>
<set_io pin="clk[1]" net="clk1"/>
<set_io pin="clk[2]" net="OPEN"/>
<set_io pin="clk[3]" net="OPEN"/>
@ -23,3 +23,11 @@ An example of design constraints is shown as follows.
.. option:: net="<string>"
The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file.
.. option:: default_value="<string>"
The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli.
.. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration.
.. note:: The default value in pin constraint file has a higher priority than the ``default_value`` syntax in the :ref:`circuit_library`.

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docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png
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35
docs/source/manual/fpga_verilog/testbench.rst
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@ -58,8 +58,8 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. _fig_verilog_testbench_hierarchy:
.. figure:: ./figures/verilog_testbench_hierarchy.png
:scale: 90%
.. figure:: ./figures/verilog_testbench_hierarchy.svg
:scale: 100%
Hierarchy of Verilog testbenches for a FPGA fabric implemented with an application
@ -73,37 +73,6 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. note:: Fabric Verilog netlists are included in this file.
.. option:: define_simulation.v
This file includes pre-processing flags required by the testbenches, to smooth HDL simulation.
It will include the folliwng pre-procesing flags:
- ```define AUTOCHECK_SIMULATION`` When enabled, testbench will include self-testing features. The FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.
.. note:: OpenFPGA always enable the self-testing feature. Users can disable it by commenting out the associated line in the ``define_simulation.v``.
- ```define ENABLE_FORMAL_VERFICATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the pre-configured FPGA netlist for formal verification usage. This flag is added when ``--print_formal_verification_top_netlist`` option is enabled when calling the ``write_verilog_testbench`` command.
- ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command.
.. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: <bench_name>_autocheck_top_tb.v
This is the netlist for full testbench.

54
docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
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@ -24,14 +24,6 @@ write_fabric_verilog
Output timing information to Verilog netlists for primitive modules
.. option:: --include_signal_init
Output signal initialization to Verilog netlists for primitive modules
.. option:: --support_icarus_simulator
Output Verilog netlists with syntax that iVerilog simulatorcan accept
.. option:: --print_user_defined_template
Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
@ -59,7 +51,9 @@ write_full_testbench
.. option:: --reference_benchmark_file_path <string>
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. note:: If not specified, the testbench will not include any self-checking feature!
.. option:: --pin_constraints_file <string> or -pcf <string>
@ -84,6 +78,11 @@ write_full_testbench
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --verbose
Show verbose log
@ -114,9 +113,25 @@ write_preconfigured_fabric_wrapper
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --support_icarus_simulator
.. option:: --embed_bitstream <string>
Output Verilog netlists with syntax that iVerilog simulator can accept
Specify if the bitstream should be embedded to the Verilog netlists in HDL codes. Available options are ``none``, ``iverilog`` and ``modelsim``. Default value: ``modelsim``.
.. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong!
.. warning:: Please specify ``iverilog`` if you are using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: --include_signal_init
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --verbose
@ -137,7 +152,9 @@ write_preconfigured_testbench
.. option:: --reference_benchmark_file_path <string>
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. note:: If not specified, the testbench will not include any self-checking feature!
.. option:: --pin_constraints_file <string> or -pcf <string>
@ -152,11 +169,6 @@ write_preconfigured_testbench
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --support_icarus_simulator
Output Verilog netlists with syntax that iVerilog simulator can accept
.. option:: --verbose
Show verbose log
@ -178,6 +190,14 @@ write_simulation_task_info
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. option:: --testbench_type <string>
Specify the type of testbenches [``preconfigured_testbench``|``full_testbench``]. By default, it is the ``preconfigured_testbench``.
.. option:: --time_unit <string>
Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``ms``).
.. option:: --verbose
Show verbose log

3
libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h
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@ -59,6 +59,9 @@ constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:";
constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
} /* end namespace openfpga */
#endif

51
libopenfpga/libpcf/src/pin_constraints.cpp
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@ -60,6 +60,36 @@ openfpga::BasicPort PinConstraints::net_pin(const std::string& net) const {
return constrained_pin;
}
PinConstraints::e_logic_level PinConstraints::net_default_value(const std::string& net) const {
PinConstraints::e_logic_level logic_level = PinConstraints::NUM_LOGIC_LEVELS;
for (const PinConstraintId& pin_constraint : pin_constraints()) {
if (net == pin_constraint_nets_[pin_constraint]) {
logic_level = pin_constraint_net_default_values_[pin_constraint];
break;
}
}
return logic_level;
}
std::string PinConstraints::net_default_value_to_string(const PinConstraintId& pin_constraint) const {
VTR_ASSERT(valid_pin_constraint_id(pin_constraint));
if (PinConstraints::LOGIC_HIGH == pin_constraint_net_default_values_[pin_constraint]) {
return std::string("1");
} else if (PinConstraints::LOGIC_LOW == pin_constraint_net_default_values_[pin_constraint]) {
return std::string("0");
}
return std::string();
}
size_t PinConstraints::net_default_value_to_int(const std::string& net) const {
if (PinConstraints::LOGIC_HIGH == net_default_value(net)) {
return 1;
} else if (PinConstraints::LOGIC_LOW == net_default_value(net)) {
return 0;
}
return -1;
}
bool PinConstraints::empty() const {
return 0 == pin_constraint_ids_.size();
}
@ -71,6 +101,7 @@ void PinConstraints::reserve_pin_constraints(const size_t& num_pin_constraints)
pin_constraint_ids_.reserve(num_pin_constraints);
pin_constraint_pins_.reserve(num_pin_constraints);
pin_constraint_nets_.reserve(num_pin_constraints);
pin_constraint_net_default_values_.reserve(num_pin_constraints);
}
PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& pin,
@ -81,10 +112,21 @@ PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort&
pin_constraint_ids_.push_back(pin_constraint_id);
pin_constraint_pins_.push_back(pin);
pin_constraint_nets_.push_back(net);
pin_constraint_net_default_values_.push_back(PinConstraints::NUM_LOGIC_LEVELS);
return pin_constraint_id;
}
void PinConstraints::set_net_default_value(const PinConstraintId& pin_constraint,
const std::string& default_value) {
VTR_ASSERT(valid_pin_constraint_id(pin_constraint));
if (default_value == std::string("1")) {
pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_HIGH;
} else if (default_value == std::string("0")) {
pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_LOW;
}
}
/************************************************************************
* Internal invalidators/validators
***********************************************************************/
@ -100,3 +142,12 @@ bool PinConstraints::unconstrained_net(const std::string& net) const {
bool PinConstraints::unmapped_net(const std::string& net) const {
return std::string(PIN_CONSTRAINT_OPEN_NET) == net;
}
bool PinConstraints::valid_net_default_value(const PinConstraintId& pin_constraint) const {
VTR_ASSERT(valid_pin_constraint_id(pin_constraint));
return PinConstraints::NUM_LOGIC_LEVELS != pin_constraint_net_default_values_[pin_constraint];
}
bool PinConstraints::valid_net_default_value(const std::string& net) const {
return PinConstraints::NUM_LOGIC_LEVELS != net_default_value(net);
}

38
libopenfpga/libpcf/src/pin_constraints.h
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@ -41,6 +41,12 @@ class PinConstraints {
typedef vtr::vector<PinConstraintId, PinConstraintId>::const_iterator pin_constraint_iterator;
/* Create range */
typedef vtr::Range<pin_constraint_iterator> pin_constraint_range;
/* Logic value */
enum e_logic_level {
LOGIC_HIGH,
LOGIC_LOW,
NUM_LOGIC_LEVELS
};
public: /* Constructors */
PinConstraints();
public: /* Accessors: aggregates */
@ -63,6 +69,21 @@ class PinConstraints {
*/
openfpga::BasicPort net_pin(const std::string& net) const;
/* Find the default value that a net is constrained to
* If not found, return an invalid value
*/
e_logic_level net_default_value(const std::string& net) const;
/* Generate the string of the default value
* If not found, return an empty string
*/
std::string net_default_value_to_string(const PinConstraintId& pin_constraint) const;
/* Generate the integer representation of the default value
* If not found, return -1
*/
size_t net_default_value_to_int(const std::string& net) const;
/* Check if there are any pin constraints */
bool empty() const;
@ -74,6 +95,10 @@ class PinConstraints {
PinConstraintId create_pin_constraint(const openfpga::BasicPort& pin,
const std::string& net);
/* Set the default value for the net under a given pin constraint */
void set_net_default_value(const PinConstraintId& pin_constraint,
const std::string& default_value);
public: /* Public invalidators/validators */
/* Show if the pin constraint id is a valid for data queries */
bool valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const;
@ -91,6 +116,16 @@ class PinConstraints {
* - net()
*/
bool unmapped_net(const std::string& net) const;
/* Check if default value is a valid one or not
* This is to check if the default value is constrained or not
*/
bool valid_net_default_value(const PinConstraintId& pin_constraint) const;
/* Check if default value is a valid one or not
* This is to check if the default value is constrained or not
*/
bool valid_net_default_value(const std::string& net) const;
private: /* Internal data */
/* Unique ids for each design constraint */
vtr::vector<PinConstraintId, PinConstraintId> pin_constraint_ids_;
@ -100,6 +135,9 @@ class PinConstraints {
/* Nets to constraint */
vtr::vector<PinConstraintId, std::string> pin_constraint_nets_;
/* Default value of the nets to constraint */
vtr::vector<PinConstraintId, e_logic_level> pin_constraint_net_default_values_;
};
#endif

8
libopenfpga/libpcf/src/read_xml_pin_constraints.cpp
View File

@ -41,6 +41,14 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint,
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint),
"Fail to create pin constraint!\n");
}
/* Set default value if defined */
std::string default_value = get_attribute(xml_pin_constraint, "default_value", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
pin_constraints.set_net_default_value(pin_constraint_id, default_value);
if (!default_value.empty() && !pin_constraints.valid_net_default_value(pin_constraint_id)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint),
"Invalid default value for pin constraints. Expect [0|1]!\n");
}
}
/********************************************************************

1
libopenfpga/libpcf/src/write_xml_pin_constraints.cpp
View File

@ -44,6 +44,7 @@ int write_xml_pin_constraint(std::fstream& fp,
write_xml_attribute(fp, "pin", generate_xml_port_name(pin_constraints.pin(pin_constraint)).c_str());
write_xml_attribute(fp, "net", pin_constraints.net(pin_constraint).c_str());
write_xml_attribute(fp, "default_value", pin_constraints.net_default_value_to_string(pin_constraint).c_str());
fp << "/>" << "\n";

9
openfpga/src/base/openfpga_bitstream.cpp
View File

@ -10,6 +10,7 @@
/* Headers from openfpgautil library */
#include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
/* Headers from fpgabitstream library */
#include "read_xml_arch_bitstream.h"
@ -153,6 +154,11 @@ int write_io_mapping(const OpenfpgaContext& openfpga_ctx,
ModuleId top_module = openfpga_ctx.module_graph().find_module(top_module_name);
VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module));
/* VPR added a prefix to the output ports, remove them here */
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
IoMap io_map = build_fpga_io_mapping_info(openfpga_ctx.module_graph(),
top_module,
g_vpr_ctx.atom(),
@ -160,7 +166,8 @@ int write_io_mapping(const OpenfpgaContext& openfpga_ctx,
openfpga_ctx.io_location_map(),
openfpga_ctx.vpr_netlist_annotation(),
std::string(),
std::string());
std::string(),
prefix_to_remove);
status = write_io_mapping_to_xml_file(io_map,
cmd_context.option_value(cmd, opt_file),

43
openfpga/src/base/openfpga_verilog.cpp
View File

@ -8,6 +8,9 @@
/* Headers from openfpgashell library */
#include "command_exit_codes.h"
/* Headers from openfpgautil library */
#include "openfpga_scale.h"
#include "verilog_api.h"
#include "openfpga_verilog.h"
@ -127,7 +130,8 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -138,12 +142,17 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_print_formal_verification_top_netlist(true);
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
}
if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) {
options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream));
}
/* If pin constraints are enabled by command options, read the file */
PinConstraints pin_constraints;
if (true == cmd_context.option_enable(cmd, opt_pcf)) {
@ -173,7 +182,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_verbose = cmd.option("verbose");
@ -185,7 +193,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_preconfig_top_testbench(true);
@ -217,6 +224,8 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_file = cmd.option("file");
CommandOptionId opt_hdl_dir = cmd.option("hdl_dir");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_tb_type = cmd.option("testbench_type");
CommandOptionId opt_time_unit = cmd.option("time_unit");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -228,6 +237,32 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file));
if (true == cmd_context.option_enable(cmd, opt_time_unit)) {
options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));
}
/* Identify testbench type */
std::string full_tb_tag("full_testbench");
std::string preconfig_tb_tag("preconfigured_testbench");
if (true == cmd_context.option_enable(cmd, opt_tb_type)) {
if (std::string("preconfigured_testbench") == cmd_context.option_value(cmd, opt_tb_type)) {
options.set_print_preconfig_top_testbench(true);
} else if (std::string("full_testbench") == cmd_context.option_value(cmd, opt_tb_type)) {
options.set_print_preconfig_top_testbench(false);
options.set_print_top_testbench(true);
} else {
/* Invalid option, error out */
VTR_LOG_ERROR("Invalid option value for testbench type: '%s'! Should be either '%s' or '%s'\n",
cmd_context.option_value(cmd, opt_tb_type).c_str(),
full_tb_tag.c_str(),
preconfig_tb_tag.c_str());
return CMD_EXEC_FATAL_ERROR;
}
} else {
/* Deposit default type which is the preconfigured testbench */
options.set_print_preconfig_top_testbench(true);
}
return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(),
openfpga_ctx.bitstream_manager(),
g_vpr_ctx.atom(),

28
openfpga/src/base/openfpga_verilog_command.cpp
View File

@ -84,7 +84,7 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
/* add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "specify the file path to the reference verilog netlist");
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "specify the file path to the reference verilog netlist. If specified, the testbench will include self-checking codes");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* add an option '--fast_configuration' */
@ -97,6 +97,9 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--no_self_checking' */
shell_cmd.add_option("no_self_checking", false, "Do not generate self-checking codes for Verilog testbenches.");
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
@ -146,8 +149,12 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga:
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--support_icarus_simulator' */
shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
/* Add an option '--embed_bitstream' */
CommandOptionId embed_bitstream_opt = shell_cmd.add_option("embed_bitstream", false, "Embed bitstream to the Verilog wrapper netlist; This may cause a large netlist file size");
shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING);
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
/* add an option '--verbose' */
shell_cmd.add_option("verbose", false, "enable verbose output");
@ -189,12 +196,9 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
/* Add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* Add an option '--support_icarus_simulator' */
shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
/* Add an option '--explicit_port_mapping' */
shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
@ -237,9 +241,17 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell<O
shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING);
/* Add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* Add an option '--testbench_type'*/
CommandOptionId tb_type_opt = shell_cmd.add_option("testbench_type", false, "Specify the type of testbenches to be considered. Different testbenches have different simulation parameters.");
shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING);
/* Add an option '--time_unit' */
CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit to be used in HDL simulation. Acceptable is [a|f|p|n|u|m|k|M]s");
shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");

1
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -747,6 +747,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
/* Find the port of the grid module according to the tile annotation */
int grid_pin_start_index = physical_tile->num_pins;
t_physical_tile_port physical_tile_port;
physical_tile_port.num_pins = 0;
for (const t_physical_tile_port& tile_port : physical_tile->ports) {
if (std::string(tile_port.name) == tile_port_to_connect.get_name()) {
BasicPort ref_tile_port(tile_port.name, tile_port.num_pins);

16
openfpga/src/fpga_bitstream/build_io_mapping_info.cpp
View File

@ -37,7 +37,8 @@ IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix) {
const std::string& io_output_port_name_postfix,
const std::vector<std::string>& output_port_prefix_to_remove) {
IoMap io_map;
/* Only mappable i/o ports can be considered */
@ -129,7 +130,18 @@ IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager,
benchmark_io_port.set_width(1);
} else {
VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
benchmark_io_port.set_name(std::string(block_name + io_output_port_name_postfix));
/* VPR may have added a prefix to the output ports, remove them here */
std::string output_block_name = block_name;
for (const std::string& prefix_to_remove : output_port_prefix_to_remove) {
if (!prefix_to_remove.empty()) {
if (0 == output_block_name.find(prefix_to_remove)) {
output_block_name.erase(0, prefix_to_remove.length());
break;
}
}
}
benchmark_io_port.set_name(std::string(output_block_name + io_output_port_name_postfix));
benchmark_io_port.set_width(1);
}

3
openfpga/src/fpga_bitstream/build_io_mapping_info.h
View File

@ -26,7 +26,8 @@ IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix);
const std::string& io_output_port_name_postfix,
const std::vector<std::string>& output_port_prefix_to_remove);
} /* end namespace openfpga */

4
openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
View File

@ -103,7 +103,7 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
VTR_ASSERT(!sink_instance_name.empty());
/* Get the input id that is used! Disable the unused inputs! */
fp << "set_disable_timing ";
fp << parent_instance_name;
fp << parent_instance_name << "/";
fp << sink_instance_name << "/";
fp << generate_sdc_port(sink_port);
fp << std::endl;
@ -228,7 +228,7 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
VTR_ASSERT(!sink_instance_name.empty());
/* Get the input id that is used! Disable the unused inputs! */
fp << "set_disable_timing ";
fp << parent_instance_name;
fp << parent_instance_name << "/";
fp << sink_instance_name << "/";
fp << generate_sdc_port(sink_port);
fp << std::endl;

16
openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
View File

@ -83,7 +83,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
t_pb_graph_node* des_pb_graph_node = des_pb_graph_pin->parent_node;
/* Find the src module in module manager */
std::string src_module_name = generate_physical_block_module_name(src_pb_graph_pin->parent_node->pb_type);
std::string src_module_name = generate_physical_block_module_name(src_pb_graph_node->pb_type);
ModuleId src_module = module_manager.find_module(src_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(src_module));
@ -104,6 +104,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
src_instance_name += std::to_string(instance_id);
src_instance_name += "_";
} else {
VTR_ASSERT_SAFE(true == module_manager.instance_name(parent_module, src_module, instance_id).empty());
src_instance_name += module_manager.instance_name(parent_module, src_module, instance_id);
}
}
@ -113,7 +114,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
src_port.set_width(src_pb_graph_pin->pin_number, src_pb_graph_pin->pin_number);
/* Find the des module in module manager */
std::string des_module_name = generate_physical_block_module_name(des_pb_graph_pin->parent_node->pb_type);
std::string des_module_name = generate_physical_block_module_name(des_pb_graph_node->pb_type);
ModuleId des_module = module_manager.find_module(des_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(des_module));
ModulePortId des_module_port_id = module_manager.find_module_port(des_module, generate_pb_type_port_name(des_pb_graph_pin->port));
@ -133,6 +134,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
des_instance_name += std::to_string(instance_id);
des_instance_name += "_";
} else {
VTR_ASSERT_SAFE(true != module_manager.instance_name(parent_module, des_module, instance_id).empty());
des_instance_name += module_manager.instance_name(parent_module, des_module, instance_id);
}
}
@ -150,17 +152,11 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
/* Give full path if hierarchical is not enabled */
std::string src_module_path = src_instance_name;
if (false == hierarchical) {
if (true == src_instance_name.empty()) {
src_instance_name = generate_instance_name(src_module_name, 0);
}
src_module_path = module_path + src_instance_name;
}
std::string des_module_path = des_instance_name;
if (false == hierarchical) {
if (true == des_instance_name.empty()) {
des_instance_name = generate_instance_name(des_module_name, 0);
}
des_module_path = module_path + des_instance_name;
}
@ -521,7 +517,7 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,
hierarchical,
format_dir_path(module_path + std::string(physical_mode->pb_type_children[ipb].name)),
format_dir_path(module_path + generate_physical_block_instance_name(&(physical_mode->pb_type_children[ipb]), ipb)),
module_manager,
device_annotation,
&(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
@ -582,6 +578,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
std::string module_path = format_dir_path(root_path + grid_module_name);
module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index));
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,
@ -603,6 +600,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
std::string module_path = format_dir_path(root_path + grid_module_name);
module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index));
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,

19
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -170,10 +170,6 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
/* Create directories */
create_directory(src_dir_path);
/* Output preprocessing flags for HDL simulations */
print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
options);
/* Generate full testbench for verification, including configuration phase and operating phase */
std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
print_verilog_full_testbench(module_manager,
@ -192,10 +188,11 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
options);
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_testbench_include_netlists(src_dir_path,
print_verilog_full_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
options.reference_benchmark_file_path(),
options.no_self_checking());
return status;
}
@ -269,10 +266,6 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
/* Create directories */
create_directory(src_dir_path);
/* Output preprocessing flags for HDL simulations */
print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
options);
/* Generate top-level testbench using random vectors */
std::string random_top_testbench_file_path = src_dir_path + netlist_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
print_verilog_random_top_testbench(netlist_name,
@ -286,10 +279,11 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
options);
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_testbench_include_netlists(src_dir_path,
print_verilog_preconfigured_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
options.reference_benchmark_file_path(),
options.no_self_checking());
return status;
}
@ -323,6 +317,7 @@ int fpga_verilog_simulation_task_info(const ModuleManager &module_manager,
std::string simulation_ini_file_name = options.simulation_ini_path();
VTR_ASSERT(true != options.simulation_ini_path().empty());
print_verilog_simulation_info(simulation_ini_file_name,
options,
netlist_name,
src_dir_path,
atom_ctx, place_ctx, io_location_map,

139
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -90,14 +90,15 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
/********************************************************************
* Print a file that includes all the netlists
* including the fabric netlists and testbenches
* including the fabric netlists and full testbenches
* that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_verilog_testbench_include_netlists(const std::string& src_dir,
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file) {
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */
@ -110,11 +111,52 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir,
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
/* Print preprocessing flags */
print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {
print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
} else {
VTR_ASSERT_SAFE(false == fabric_netlist_file.empty());
print_verilog_include_netlist(fp, fabric_netlist_file);
}
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */
if (!no_self_checking) {
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
fp << std::endl;
}
/* Include top-level testbench only when auto-check flag is enabled */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
/* Close the file stream */
fp.close();
}
/********************************************************************
* Print a file that includes all the netlists
* including the fabric netlists and preconfigured testbenches
* that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
/* Validate the file stream */
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {
@ -126,34 +168,16 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir,
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
fp << "\t";
if (!no_self_checking) {
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
}
/* Include formal verification netlists only when formal verification flag is enable */
print_verilog_preprocessing_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG));
fp << "\t";
/* Include formal verification netlists */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX));
/* Include formal verification testbench only when formal simulation flag is enabled */
fp << "\t";
print_verilog_preprocessing_flag(fp, std::string(FORMAL_SIMULATION_FLAG));
fp << "\t\t";
/* Include formal verification testbench */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
fp << "\t";
print_verilog_endif(fp);
print_verilog_endif(fp);
fp << std::endl;
/* Include top-level testbench only when auto-check flag is enabled */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
fp << "\t";
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
print_verilog_endif(fp);
fp << std::endl;
/* Close the file stream */
fp.close();
@ -188,63 +212,4 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
fp.close();
}
/********************************************************************
* Print a Verilog file containing simulation-related preprocessing flags
*******************************************************************/
void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
const VerilogTestbenchOption& verilog_testbench_opts) {
std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME);
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
/* Validate the file stream */
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features"));
/* To enable signal initialization */
if (true == verilog_testbench_opts.include_signal_init()) {
print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1);
fp << std::endl;
}
/* To enable functional verfication with Icarus */
if (true == verilog_testbench_opts.support_icarus_simulator()) {
print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
fp << std::endl;
}
/* To enable manualy checked simulation */
if (true == verilog_testbench_opts.print_top_testbench()) {
print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* To enable auto-checked simulation */
if ( (true == verilog_testbench_opts.print_preconfig_top_testbench())
|| (true == verilog_testbench_opts.print_top_testbench()) ) {
print_verilog_define_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* To enable pre-configured FPGA simulation */
if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) {
print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
fp << std::endl;
}
/* To enable pre-configured FPGA simulation */
if (true == verilog_testbench_opts.print_preconfig_top_testbench()) {
print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* Close the file stream */
fp.close();
}
} /* end namespace openfpga */

14
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
View File

@ -21,17 +21,21 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir,
const CircuitLibrary& circuit_lib);
void print_verilog_testbench_include_netlists(const std::string& src_dir,
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file);
const std::string& reference_benchmark_file,
const bool& no_self_checking);
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
const FabricVerilogOption& fabric_verilog_opts);
void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
const VerilogTestbenchOption& verilog_testbench_opts);
} /* end namespace openfpga */
#endif

11
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -7,18 +7,8 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v";
constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation
constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification
constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
// Icarus variables and flag
constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
// End of Icarus variables and flag
constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v";
constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
@ -27,7 +17,6 @@ constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be
constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_autocheck_top_tb.v"; /* !!! must be consist with the modelsim_autocheck_testbench_module_postfix */
constexpr char* RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_formal_random_top_tb.v";
constexpr char* DEFINES_VERILOG_FILE_NAME = "fpga_defines.v";
constexpr char* DEFINES_VERILOG_SIMULATION_FILE_NAME = "define_simulation.v";
constexpr char* SUBMODULE_VERILOG_FILE_NAME = "sub_module.v";
constexpr char* LOGIC_BLOCK_VERILOG_FILE_NAME = "logic_blocks.v";
constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v";

43
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -16,6 +16,7 @@
/* Headers from openfpgautil library */
#include "openfpga_port.h"
#include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
#include "openfpga_atom_netlist_utils.h"
#include "simulation_utils.h"
@ -40,7 +41,6 @@ constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT";
constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT";
constexpr char* ERROR_COUNTER = "nb_error";
constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start";
constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200;
/********************************************************************
* Print the module ports for the Verilog testbench
@ -57,12 +57,12 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const e_verilog_default_net_type& default_net_type) {
const VerilogTestbenchOption& options) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_default_net_type_declaration(fp,
default_net_type);
options.default_net_type());
/* Print the declaration for the module */
fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl;
@ -84,16 +84,17 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(AUTOCHECKED_SIMULATION_FLAG));
options.no_self_checking());
/* Instantiate an integer to count the number of error
* and determine if the simulation succeed or failed
*/
if (!options.no_self_checking()) {
print_verilog_comment(fp, std::string("----- Error counter -------"));
fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl;
/* Add an empty line as splitter */
fp << std::endl;
}
}
/********************************************************************
@ -104,13 +105,12 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
const std::string& reference_verilog_top_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
/* Instanciate benchmark */
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
@ -126,18 +126,13 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
prefix_to_remove,
std::string(BENCHMARK_PORT_POSTFIX),
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************
@ -162,6 +157,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
std::vector<std::string>(),
std::string(FPGA_PORT_POSTFIX),
atom_ctx, netlist_annotation,
PinConstraints(),
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
@ -237,7 +233,7 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp,
*/
fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl;
fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl;
print_verilog_wire_connection(fp, reset_port, reset_port, true);
print_verilog_register_connection(fp, reset_port, reset_port, true);
fp << "\tend" << std::endl;
}
@ -300,7 +296,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
/* Start of testbench */
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options.default_net_type());
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options);
/* Call defined top-level module */
print_verilog_random_testbench_fpga_instance(fp, circuit_name,
@ -308,9 +304,12 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
options.explicit_port_mapping());
/* Call defined benchmark */
if (!options.no_self_checking()) {
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
atom_ctx, netlist_annotation,
pin_constraints,
options.explicit_port_mapping());
}
/* Find clock port to be used */
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
@ -339,10 +338,11 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
pin_constraints,
clock_port_names,
std::string(CHECKFLAG_PORT_POSTFIX),
clock_ports);
clock_ports,
options.no_self_checking());
if (!options.no_self_checking()) {
print_verilog_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(FORMAL_TB_SIM_START_PORT_NAME),
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
@ -352,9 +352,9 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
netlist_annotation,
clock_port_names,
std::string(DEFAULT_CLOCK_NAME));
}
float simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
simulation_parameters.num_clock_cycles(),
float simulation_time = find_operating_phase_simulation_time(simulation_parameters.num_clock_cycles(),
1./simulation_parameters.default_operating_clock_frequency(),
VERILOG_SIM_TIMESCALE);
@ -364,7 +364,8 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::string(circuit_name + std::string("_formal.vcd")),
std::string(FORMAL_TB_SIM_START_PORT_NAME),
std::string(ERROR_COUNTER),
simulation_time);
simulation_time,
options.no_self_checking());
/* Testbench ends*/
print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX));

61
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -204,7 +204,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
* while uses 'force' syntax to impost the bitstream at mem_inv port
*******************************************************************/
static
void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
void print_verilog_preconfig_top_module_force_bitstream(std::fstream &fp,
const ModuleManager &module_manager,
const ModuleId &top_module,
const BitstreamManager &bitstream_manager,
@ -214,6 +214,8 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----"));
fp << "initial begin" << std::endl;
for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) {
/* We only cares blocks with configuration bits */
if (0 == bitstream_manager.block_bits(config_block_id).size()) {
@ -242,31 +244,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) {
config_data_values.push_back(bitstream_manager.bit_value(config_bit));
}
print_verilog_wire_constant_values(fp, config_data_port, config_data_values);
}
print_verilog_force_wire_constant_values(fp, config_data_port, config_data_values);
if (true == output_datab_bits) {
fp << "initial begin" << std::endl;
for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) {
/* We only cares blocks with configuration bits */
if (0 == bitstream_manager.block_bits(config_block_id).size()) {
continue;
}
/* Build the hierarchical path of the configuration bit in modules */
std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id);
/* Drop the first block, which is the top module, it should be replaced by the instance name here */
/* Ensure that this is the module we want to drop! */
VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0])));
block_hierarchy.erase(block_hierarchy.begin());
/* Build the full hierarchy path */
std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
for (const ConfigBlockId &temp_block : block_hierarchy) {
bit_hierarchy_path += std::string(".");
bit_hierarchy_path += bitstream_manager.block_name(temp_block);
}
bit_hierarchy_path += std::string(".");
/* Find the bit index in the parent block */
BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(),
bitstream_manager.block_bits(config_block_id).size());
@ -277,9 +257,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
}
print_verilog_force_wire_constant_values(fp, config_datab_port, config_datab_values);
}
}
fp << "end" << std::endl;
}
print_verilog_comment(fp, std::string("----- End assign bitstream to configuration memories -----"));
}
@ -364,7 +344,8 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
const ModuleId &top_module,
const CircuitLibrary& circuit_lib,
const CircuitModelId& mem_model,
const BitstreamManager &bitstream_manager) {
const BitstreamManager &bitstream_manager,
const e_embedded_bitstream_hdl_type& embedded_bitstream_hdl_type) {
/* Skip the datab port if there is only 1 output port in memory model
* Currently, it assumes that the data output port is always defined while datab is optional
@ -379,21 +360,17 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----"));
print_verilog_preprocessing_flag(fp, std::string(ICARUS_SIMULATOR_FLAG));
/* Use assign syntax for Icarus simulator */
print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module,
if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) {
print_verilog_preconfig_top_module_force_bitstream(fp, module_manager, top_module,
bitstream_manager,
output_datab_bits);
fp << "`else" << std::endl;
/* Use assign syntax for Icarus simulator */
/* Use deposit syntax for other simulators */
} else if (EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type) {
print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module,
bitstream_manager,
output_datab_bits);
print_verilog_endif(fp);
}
print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----"));
}
@ -502,17 +479,23 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
CircuitModelId sram_model = config_protocol.memory_model();
VTR_ASSERT(true == circuit_lib.valid_model_id(sram_model));
/* Assign FPGA internal SRAM/Memory ports to bitstream values */
/* Assign FPGA internal SRAM/Memory ports to bitstream values, only output when needed */
print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module,
circuit_lib, sram_model,
bitstream_manager);
bitstream_manager,
options.embedded_bitstream_hdl_type());
/* Add signal initialization */
/* Add signal initialization:
* Bypass writing codes to files due to the autogenerated codes are very large.
*/
if (true == options.include_signal_init()) {
print_verilog_testbench_signal_initialization(fp,
std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME),
circuit_lib,
module_manager,
top_module);
top_module,
false);
}
/* Testbench ends*/
print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX));

31
openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
View File

@ -13,6 +13,7 @@
#include "vtr_time.h"
/* Headers from openfpgautil library */
#include "openfpga_scale.h"
#include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
@ -31,6 +32,7 @@ namespace openfpga {
* information, in order to interface different Verilog simulators
********************************************************************/
void print_verilog_simulation_info(const std::string& ini_fname,
const VerilogTestbenchOption& options,
const std::string& circuit_name,
const std::string& src_dir,
const AtomContext& atom_ctx,
@ -57,24 +59,39 @@ void print_verilog_simulation_info(const std::string& ini_fname,
VTR_ASSERT(true != ini_fname.empty());
mINI::INIStructure ini;
// std::map<char, int> units_map;
// units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6;
// units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15;
/* Compute simulation time period */
float simulation_time_period = find_simulation_time_period(1E-3,
/* Compute simulation time period: full testbench and pre-configured testbench has different length
* Currently, we only support the two types. And one of them must be enabled when outputting this file
*/
float simulation_time_period = 0.;
if (options.print_top_testbench()) {
simulation_time_period = find_simulation_time_period(options.time_unit(),
num_program_clock_cycles,
1. / prog_clock_freq,
num_operating_clock_cycles,
1. / op_clock_freq);
} else {
VTR_ASSERT(options.print_preconfig_top_testbench());
simulation_time_period = find_operating_phase_simulation_time(num_operating_clock_cycles,
1. / op_clock_freq,
options.time_unit());
}
/* Identify the testbench file name depending on the type */
std::string top_tb_name;
if (options.print_top_testbench()) {
top_tb_name = circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
} else {
VTR_ASSERT(options.print_preconfig_top_testbench());
top_tb_name = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
}
/* Basic information */
ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name;
ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
ini["SIMULATION_DECK"]["TOP_TB"] = top_tb_name;
ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period);
ini["SIMULATION_DECK"]["UNIT "] = "ms";
ini["SIMULATION_DECK"]["UNIT "] = unit_to_string(options.time_unit());
ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX));

2
openfpga/src/fpga_verilog/verilog_simulation_info_writer.h
View File

@ -9,6 +9,7 @@
#include "config_protocol.h"
#include "vpr_context.h"
#include "io_location_map.h"
#include "verilog_testbench_options.h"
/********************************************************************
* Function declaration
@ -18,6 +19,7 @@
namespace openfpga {
void print_verilog_simulation_info(const std::string& ini_fname,
const VerilogTestbenchOption& options,
const std::string& circuit_name,
const std::string& src_dir,
const AtomContext& atom_ctx,

40
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -21,9 +21,10 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
print_top_testbench_ = false;
simulation_ini_path_.clear();
explicit_port_mapping_ = false;
support_icarus_simulator_ = false;
include_signal_init_ = false;
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
time_unit_ = 1E-3;
verbose_output_ = false;
}
@ -74,14 +75,22 @@ bool VerilogTestbenchOption::include_signal_init() const {
return include_signal_init_;
}
bool VerilogTestbenchOption::support_icarus_simulator() const {
return support_icarus_simulator_;
bool VerilogTestbenchOption::no_self_checking() const {
return reference_benchmark_file_path_.empty();
}
e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const {
return default_net_type_;
}
float VerilogTestbenchOption::time_unit() const {
return time_unit_;
}
e_embedded_bitstream_hdl_type VerilogTestbenchOption::embedded_bitstream_hdl_type() const {
return embedded_bitstream_hdl_type_;
}
bool VerilogTestbenchOption::verbose_output() const {
return verbose_output_;
}
@ -142,10 +151,6 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) {
include_signal_init_ = enabled;
}
void VerilogTestbenchOption::set_support_icarus_simulator(const bool& enabled) {
support_icarus_simulator_ = enabled;
}
void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) {
/* Decode from net type string */;
if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) {
@ -160,6 +165,27 @@ void VerilogTestbenchOption::set_default_net_type(const std::string& default_net
}
}
void VerilogTestbenchOption::set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type) {
/* Decode from HDL type string */;
if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES])) {
embedded_bitstream_hdl_type_ = NUM_EMBEDDED_BITSTREAM_HDL_TYPES;
} else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG])) {
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_IVERILOG;
} else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM])) {
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
} else {
VTR_LOG_WARN("Invalid embedded bitstream type: '%s'! Expect ['%s'|'%s'|'%s']\n",
embedded_bitstream_hdl_type.c_str(),
EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES],
EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG],
EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM]);
}
}
void VerilogTestbenchOption::set_time_unit(const float& time_unit) {
time_unit_ = time_unit;
}
void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}

19
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -10,6 +10,15 @@
/* Begin namespace openfpga */
namespace openfpga {
/* Embedded bitstream code style */
enum e_embedded_bitstream_hdl_type {
EMBEDDED_BITSTREAM_HDL_IVERILOG,
EMBEDDED_BITSTREAM_HDL_MODELSIM,
NUM_EMBEDDED_BITSTREAM_HDL_TYPES
};
constexpr std::array<const char*, NUM_EMBEDDED_BITSTREAM_HDL_TYPES + 1> EMBEDDED_BITSTREAM_HDL_TYPE_STRING = {{"iverilog", "modelsim", "none"}}; //String versions of default net types
/********************************************************************
* Options for Verilog Testbench generator
* Typicall usage:
@ -34,8 +43,10 @@ class VerilogTestbenchOption {
std::string simulation_ini_path() const;
bool explicit_port_mapping() const;
bool include_signal_init() const;
bool support_icarus_simulator() const;
bool no_self_checking() const;
e_verilog_default_net_type default_net_type() const;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
float time_unit() const;
bool verbose_output() const;
public: /* Public validator */
bool validate() const;
@ -59,8 +70,9 @@ class VerilogTestbenchOption {
void set_print_simulation_ini(const std::string& simulation_ini_path);
void set_explicit_port_mapping(const bool& enabled);
void set_include_signal_init(const bool& enabled);
void set_support_icarus_simulator(const bool& enabled);
void set_default_net_type(const std::string& default_net_type);
void set_time_unit(const float& time_unit);
void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
std::string output_directory_;
@ -73,9 +85,10 @@ class VerilogTestbenchOption {
/* Print simulation ini is enabled only when the path is not empty */
std::string simulation_ini_path_;
bool explicit_port_mapping_;
bool support_icarus_simulator_;
bool include_signal_init_;
e_verilog_default_net_type default_net_type_;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
float time_unit_;
bool verbose_output_;
};

88
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -69,6 +69,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& output_port_postfix,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const bool& use_explicit_port_map) {
/* Validate the file stream */
valid_file_stream(fp);
@ -99,6 +100,15 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
if (true == use_explicit_port_map) {
fp << "." << block_name << module_input_port_postfix << "(";
}
/* Polarity of some input may have to be inverted, as defined in pin constraints
* For example, the reset signal of the benchmark is active low
* while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted)
* However, to ensure correct stimuli to the benchmark, we have to invert the signal
*/
if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) {
fp << "~";
}
fp << block_name;
if (true == use_explicit_port_map) {
fp << ")";
@ -304,7 +314,8 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
const std::string& vcd_fname,
const std::string& simulation_start_counter_name,
const std::string& error_counter_name,
const float& simulation_time) {
const float& simulation_time,
const bool& no_self_checking) {
/* Validate the file stream */
valid_file_stream(fp);
@ -323,16 +334,27 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
BasicPort sim_start_port(simulation_start_counter_name, 1);
fp << "initial begin" << std::endl;
if (!no_self_checking) {
fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl;
}
fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl;
fp << "\t$display(\"Simulation start\");" << std::endl;
print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------"));
fp << "\t#" << std::setprecision(10) << simulation_time << std::endl;
if (!no_self_checking) {
fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl;
fp << "\t\t$display(\"Simulation Succeed\");" << std::endl;
fp << "\tend else begin" << std::endl;
fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << error_counter_name << ");" << std::endl;
fp << "\tend" << std::endl;
} else {
VTR_ASSERT_SAFE(no_self_checking);
fp << "\t$display(\"Simulation Succeed\");" << std::endl;
}
fp << "\t$finish;" << std::endl;
fp << "end" << std::endl;
@ -366,7 +388,6 @@ std::vector<BasicPort> generate_verilog_testbench_clock_port(const std::vector<s
* Restriction: this function only supports single clock benchmarks!
*******************************************************************/
void print_verilog_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& simulation_start_counter_name,
const std::string& benchmark_port_postfix,
const std::string& fpga_port_postfix,
@ -380,9 +401,7 @@ void print_verilog_testbench_check(std::fstream& fp,
/* Validate the file stream */
valid_file_stream(fp);
/* Add output autocheck conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag);
/* Add output autocheck */
print_verilog_comment(fp, std::string("----- Begin checking output vectors -------"));
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name);
@ -460,9 +479,6 @@ void print_verilog_testbench_check(std::fstream& fp,
fp << std::endl;
}
/* Condition ends */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
@ -536,7 +552,8 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
const std::string& check_flag_port_postfix,
const std::vector<BasicPort>& clock_ports) {
const std::vector<BasicPort>& clock_ports,
const bool& no_self_checking) {
/* Validate the file stream */
valid_file_stream(fp);
@ -575,10 +592,11 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
}
}
/* Set 0 to registers for checking flags */
if (!no_self_checking) {
/* Add an empty line as splitter */
fp << std::endl;
/* Set 0 to registers for checking flags */
for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
/* Bypass non-I/O atom blocks ! */
if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
@ -595,6 +613,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1);
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl;
}
}
fp << "\tend" << std::endl;
/* Finish initialization */
@ -664,7 +683,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,
const std::string& autocheck_preprocessing_flag) {
const bool& no_self_checking) {
/* Validate the file stream */
valid_file_stream(fp);
@ -718,11 +737,9 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(autocheck_preprocessing_flag));
/* Add an empty line as splitter */
fp << std::endl;
if (no_self_checking) {
return;
}
/* Instantiate wire for benchmark output */
print_verilog_comment(fp, std::string("----- Benchmark outputs -------"));
@ -767,12 +784,6 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************
@ -791,7 +802,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
const std::vector<CircuitPortId>& circuit_input_ports,
const ModuleManager& module_manager,
const ModuleId& parent_module,
const ModuleId& primitive_module) {
const ModuleId& primitive_module,
const bool& deposit_random_values) {
/* Validate the file stream */
valid_file_stream(fp);
@ -819,7 +831,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
child_hie_path,
circuit_lib, circuit_model, circuit_input_ports,
module_manager, child_module,
primitive_module);
primitive_module,
deposit_random_values);
} else {
/* If the child module is the primitive module,
* we output the signal initialization codes for the input ports
@ -828,7 +841,6 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----"));
fp << "\tinitial begin" << std::endl;
fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl;
for (const auto& input_port : circuit_input_ports) {
/* Only for formal verification: deposite a zero signal values */
@ -838,22 +850,17 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
fp << "\t\t$deposit(";
fp << child_hie_path << ".";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false);
if (!deposit_random_values) {
fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0');
fp << ");" << std::endl;
}
fp << "\t`else" << std::endl;
/* Regular case: deposite initial signal values: a random value */
for (const auto& input_port : circuit_input_ports) {
BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
input_port_info.set_origin_port_width(input_port_info.get_width());
fp << "\t\t$deposit(";
fp << child_hie_path << ".";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false);
} else {
VTR_ASSERT_SAFE(deposit_random_values);
fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl;
}
}
fp << "\t`endif\n" << std::endl;
fp << "\tend" << std::endl;
print_verilog_comment(fp, std::string("------ END driver initialization -----"));
}
@ -871,7 +878,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
const std::string& top_instance_name,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const ModuleId& top_module) {
const ModuleId& top_module,
const bool& deposit_random_values) {
/* Validate the file stream */
valid_file_stream(fp);
@ -911,7 +919,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
/* Add signal initialization Verilog codes */
fp << std::endl;
fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl;
for (const CircuitModelId& signal_init_circuit_model : signal_init_circuit_models) {
/* Find the module id corresponding to the circuit model from module graph */
ModuleId primitive_module = module_manager.find_module(circuit_lib.model_name(signal_init_circuit_model));
@ -922,10 +929,9 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
top_instance_name,
circuit_lib, signal_init_circuit_model, signal_init_circuit_ports.at(signal_init_circuit_model),
module_manager, top_module,
primitive_module);
primitive_module,
deposit_random_values);
}
fp << "`endif" << std::endl;
}
} /* end namespace openfpga */

16
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -23,9 +23,6 @@
/* begin namespace openfpga */
namespace openfpga {
constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:";
constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
void print_verilog_testbench_fpga_instance(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
@ -41,6 +38,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& output_port_postfix,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const bool& use_explicit_port_map);
void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
@ -59,13 +57,13 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
const std::string& vcd_fname,
const std::string& simulation_start_counter_name,
const std::string& error_counter_name,
const float& simulation_time);
const float& simulation_time,
const bool& no_self_checking);
std::vector<BasicPort> generate_verilog_testbench_clock_port(const std::vector<std::string>& clock_port_names,
const std::string& default_clock_name);
void print_verilog_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& simulation_start_counter_name,
const std::string& benchmark_port_postfix,
const std::string& fpga_port_postfix,
@ -89,7 +87,8 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
const std::string& check_flag_port_postfix,
const std::vector<BasicPort>& clock_ports);
const std::vector<BasicPort>& clock_ports,
const bool& no_self_checking);
void print_verilog_testbench_shared_ports(std::fstream& fp,
const AtomContext& atom_ctx,
@ -98,13 +97,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,
const std::string& autocheck_preprocessing_flag);
const bool& no_self_checking);
void print_verilog_testbench_signal_initialization(std::fstream& fp,
const std::string& top_instance_name,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const ModuleId& top_module);
const ModuleId& top_module,
const bool& deposit_random_values);
} /* end namespace openfpga */

49
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -702,12 +702,12 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
const SimulationSetting& simulation_parameters,
const ConfigProtocol& config_protocol,
const std::string& circuit_name,
const e_verilog_default_net_type& default_net_type) {
const VerilogTestbenchOption& options) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_default_net_type_declaration(fp,
default_net_type);
options.default_net_type());
/* Print module definition */
fp << "module " << circuit_name << std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX);
@ -808,13 +808,15 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(AUTOCHECKED_SIMULATION_FLAG));
options.no_self_checking());
/* Instantiate an integer to count the number of error and
* determine if the simulation succeed or failed
*/
if (!options.no_self_checking()) {
print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----"));
fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl;
}
}
/********************************************************************
@ -910,13 +912,12 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
const std::string& reference_verilog_top_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
/* Instanciate benchmark */
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
@ -932,18 +933,13 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
prefix_to_remove,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************
@ -1795,11 +1791,13 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp,
continue;
}
size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)));
/* Connect stimuli to greset with an optional inversion, depending on the default value */
BasicPort reset_port(block_name, 1);
print_verilog_wire_connection(fp, reset_port,
BasicPort(TOP_TB_RESET_PORT_NAME, 1),
1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name))));
1 == initial_value);
}
}
@ -1811,16 +1809,12 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp,
*******************************************************************/
static
void print_verilog_top_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& config_done_port_name,
const std::string& error_counter_name) {
/* Validate the file stream */
valid_file_stream(fp);
/* Add output autocheck conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag);
print_verilog_comment(fp, std::string("----- Configuration done must be raised in the end -------"));
BasicPort config_done_port(config_done_port_name, 1);
@ -1834,9 +1828,6 @@ void print_verilog_top_testbench_check(std::fstream& fp,
write_tab_to_file(fp, 1);
fp << "end" << std::endl;
/* Condition ends */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
@ -1925,7 +1916,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
pin_constraints,
simulation_parameters, config_protocol,
circuit_name,
options.default_net_type());
options);
/* Find the clock period */
float prog_clock_period = (1./simulation_parameters.programming_clock_frequency());
@ -2006,11 +1997,14 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Instanciate input benchmark */
if (!options.no_self_checking()) {
print_verilog_top_testbench_benchmark_instance(fp,
circuit_name,
atom_ctx,
netlist_annotation,
pin_constraints,
explicit_port_mapping);
}
/* load bitstream to FPGA fabric in a configuration phase */
print_verilog_full_testbench_bitstream(fp,
@ -2029,7 +2023,8 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
circuit_lib,
module_manager,
top_module);
top_module,
true);
}
@ -2048,11 +2043,12 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
pin_constraints,
clock_port_names,
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::vector<BasicPort>(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)));
std::vector<BasicPort>(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)),
options.no_self_checking());
if (!options.no_self_checking()) {
/* Add output autocheck */
print_verilog_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
@ -2065,9 +2061,9 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
/* Add autocheck for configuration phase */
print_verilog_top_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(TOP_TB_CONFIG_DONE_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER));
}
/* Find simulation time */
float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE,
@ -2085,7 +2081,8 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
std::string(circuit_name + std::string("_formal.vcd")),
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
std::ceil(simulation_time));
std::ceil(simulation_time),
options.no_self_checking());
/* Testbench ends*/

5
openfpga/src/utils/simulation_utils.cpp
View File

@ -14,14 +14,13 @@ namespace openfpga {
/********************************************************************
* Compute the time period for the simulation
*******************************************************************/
float find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
float find_operating_phase_simulation_time(const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale) {
/* Take into account the prog_reset and reset cycles
* 1e9 is to change the unit to ns rather than second
*/
return ((float)factor * (float)num_op_clock_cycles * op_clock_period) / timescale;
return ((float)num_op_clock_cycles * op_clock_period) / timescale;
}
/********************************************************************

3
openfpga/src/utils/simulation_utils.h
View File

@ -12,8 +12,7 @@
/* begin namespace openfpga */
namespace openfpga {
float find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
float find_operating_phase_simulation_time(const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale);

21
openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v Normal file
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@ -0,0 +1,21 @@
// Creating a scaleable adder
module adder_16(cout, sum, a, b, cin);
parameter size = 6; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule

21
openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v Normal file
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@ -0,0 +1,21 @@
// Creating a scaleable adder
module adder_4(cout, sum, a, b, cin);
parameter size = 4; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule

21
openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v Normal file
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@ -0,0 +1,21 @@
// Creating a scaleable adder
module adder_6(cout, sum, a, b, cin);
parameter size = 6; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule

0
openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act → openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act
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0
openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif → openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif
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0
openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v → openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
View File

0
openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v → openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v
View File

22
openfpga_flow/benchmarks/micro_benchmark/and4/and4.v Normal file
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@ -0,0 +1,22 @@
/////////////////////////////////////////
// Functionality: 4-input AND
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and4(
a,
b,
c,
d,
e);
input wire a;
input wire b;
input wire c;
input wire d;
output wire e;
assign e = a & b & c & d;
endmodule

114
openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v Normal file
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@ -0,0 +1,114 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/05/2021 09:43:10 AM
// Design Name:
// Module Name: bitstream_loader
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bitstream_loader(
input prog_clk,
input start,
output config_chain_head,
output reg done
);
parameter BITSTREAM_FILE="";
parameter BITSTREAM_SIZE=6140;
reg [BITSTREAM_SIZE<=2 ? 2 : $clog2(BITSTREAM_SIZE):0] bitstream_index;
reg [13:0] bram_addr;
reg [3:0] bram_line_index;
wire bram_output;
assign config_chain_head = bram_output;
EFX_RAM_5K #(
.READ_WIDTH(1),
.WRITE_WIDTH(0),
.INIT_0(256'h00000000000000000000000000000000000000000000007f00000000000000ff),
.INIT_1(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000),
.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4(256'h00000003f8000000000000000000000000000000000000000000000000000000),
.INIT_5(256'h0000000000000000078000000000000000000000000000000000000000000000),
.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000),
)
EFX_RAM_5K_inst (
// Port A Data: 16-bit (each) output: Port A data
.WDATA(0), // Write data
.WADDR(0), // Write address
.WE(0), // Write enable
.WCLK(0),
.WCLKE(0),
.RDATA(bram_output),
.RADDR(bram_addr),
.RE(1'b1),
.RCLK(prog_clk)
);
initial begin
bram_addr <= 0;
bram_line_index <= 0;
bitstream_index <= 0;
done <= 1'b0;
end
always @(posedge prog_clk) begin
if (start && !done) begin
bram_addr <= bram_addr + 1;
bitstream_index <= bitstream_index + 1;
end
if (bitstream_index == BITSTREAM_SIZE) begin
done <= 1'b1;
end
end
endmodule

71
openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v Normal file
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@ -0,0 +1,71 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/05/2021 10:29:55 AM
// Design Name:
// Module Name: configuration_manager
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "clock_divider.v"
`include "pulse_generator.v"
module configuration_manager(
input clk_in,
output prog_reset,
output prog_clk,
output ccff_head,
output configuration_done
);
parameter START_CYCLE=3; // Start configuration on cycle 3 of prog_clk
parameter CONFIGURATION_CLK_DIV_SIZE=12; // Divide clk_in (50MHz) by 4096 (2^12) times
wire prog_clk_out; // prog_clk signal from clk_divider
wire ccff_head_out;
assign ccff_head = ccff_head_out & ~prog_reset;
assign prog_clk = prog_clk_out & ~configuration_done; // prog_clk will stop when configuration done
// PRESET
// Programming reset will be enabled until START_CYCLE
reset_generator #(
.INITIAL_VALUE(1),
.ACTIVE_CYCLES(START_CYCLE)
) prog_reset_generator(
.clk(~prog_clk),
.pulse(prog_reset)
);
// PROG_CLK
// Divide pl_clk (50MHz) by 4096 (2^12) times
clock_divider #(
.CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE)
) prog_clk_divider (
.clk_in(clk_in),
.clk_out(prog_clk_out)
);
// Instantiate bitstream loader
bitstream_loader loader (
.prog_clk(prog_clk),
.config_chain_head(ccff_head_out),
.start(~prog_reset),
.done(configuration_done)
);
endmodule

22
openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act
View File

@ -1,22 +0,0 @@
clk0 0.505000 0.204400
rst0 0.491000 0.206000
clk1 0.472000 0.204400
rst1 0.501400 0.204600
q1[0] 0.278800 0.557400
q1[1] 0.240600 0.268800
q1[2] 0.178200 0.120000
q1[3] 0.098400 0.041600
q0[0] 0.283400 0.566600
q0[1] 0.246800 0.272000
q0[2] 0.181000 0.122200
q0[3] 0.093200 0.048800
n34 0.178200 0.068356
n38 0.098400 0.002698
$abc$226$new_n22_ 0.880800 0.004943
n42 0.283400 0.129291
n46 0.246800 0.084119
n50 0.181000 0.067113
n54 0.093200 0.002644
$abc$226$new_n27_ 0.883200 0.005398
n26 0.278800 0.038636
n30 0.240600 0.082416

48
openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif
View File

@ -1,48 +0,0 @@
# Benchmark "counter4bit_2clock" written by ABC on Wed Jan 13 13:27:00 2021
.model counter4bit_2clock
.inputs clk0 rst0 clk1 rst1
.outputs q0[0] q0[1] q0[2] q0[3] q1[0] q1[1] \
q1[2] q1[3]
.latch n26 q1[0] re clk1 2
.latch n30 q1[1] re clk1 2
.latch n34 q1[2] re clk1 2
.latch n38 q1[3] re clk1 2
.latch n42 q0[0] re clk0 2
.latch n46 q0[1] re clk0 2
.latch n50 q0[2] re clk0 2
.latch n54 q0[3] re clk0 2
.names q1[0] q1[1] rst1 q1[2] n34
-001 1
0-01 1
1100 1
.names rst1 $abc$226$new_n22_ n38
00 1
.names q1[2] q1[0] q1[1] q1[3] $abc$226$new_n22_
--00 1
-0-0 1
0--0 1
1111 1
.names rst0 q0[0] n42
00 1
.names rst0 q0[1] q0[0] n46
001 1
010 1
.names q0[1] q0[0] rst0 q0[2] n50
-001 1
0-01 1
1100 1
.names rst0 $abc$226$new_n27_ n54
00 1
.names q0[2] q0[1] q0[0] q0[3] $abc$226$new_n27_
--00 1
-0-0 1
0--0 1
1111 1
.names q1[0] rst1 n26
00 1
.names rst1 q1[0] q1[1] n30
001 1
010 1
.end

60
openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v
View File

@ -1,60 +0,0 @@
/* Generated by Yosys 0.9+2406 (git sha1 a0606e09, gcc 8.4.0 -fPIC -Os) */
module counter4bit_2clock(clk0, rst0, clk1, rst1, \q0[0] , \q0[1] , \q0[2] , \q0[3] , \q1[0] , \q1[1] , \q1[2] , \q1[3] );
wire _00_;
wire _01_;
input clk0;
input clk1;
wire n26;
wire n30;
wire n34;
wire n38;
wire n42;
wire n46;
wire n50;
wire n54;
output \q0[0] ;
reg \q0[0] ;
output \q0[1] ;
reg \q0[1] ;
output \q0[2] ;
reg \q0[2] ;
output \q0[3] ;
reg \q0[3] ;
output \q1[0] ;
reg \q1[0] ;
output \q1[1] ;
reg \q1[1] ;
output \q1[2] ;
reg \q1[2] ;
output \q1[3] ;
reg \q1[3] ;
input rst0;
input rst1;
always @(posedge clk1)
\q1[0] <= n26;
always @(posedge clk1)
\q1[1] <= n30;
always @(posedge clk1)
\q1[2] <= n34;
always @(posedge clk1)
\q1[3] <= n38;
always @(posedge clk1)
\q0[0] <= n42;
always @(posedge clk1)
\q0[1] <= n46;
always @(posedge clk1)
\q0[2] <= n50;
always @(posedge clk1)
\q0[3] <= n54;
assign n38 = 4'h1 >> { _00_, rst1 };
assign _00_ = 16'h807f >> { \q1[3] , \q1[1] , \q1[0] , \q1[2] };
assign n42 = 4'h1 >> { \q0[0] , rst0 };
assign n46 = 8'h14 >> { \q0[0] , \q0[1] , rst0 };
assign n50 = 16'h0708 >> { \q0[2] , rst0, \q0[0] , \q0[1] };
assign n54 = 4'h1 >> { _01_, rst0 };
assign _01_ = 16'h807f >> { \q0[3] , \q0[0] , \q0[1] , \q0[2] };
assign n26 = 4'h1 >> { rst1, \q1[0] };
assign n30 = 8'h14 >> { \q1[1] , \q1[0] , rst1 };
assign n34 = 16'h0708 >> { \q1[2] , rst1, \q1[1] , \q1[0] };
endmodule

25
openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v Normal file
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@ -0,0 +1,25 @@
///////////////////////////////////////////
// Functionality: Counter with asynchronous reset
// Author: Xifan Tang
////////////////////////////////////////
module counter (
clk,
reset,
result
);
input clk;
input reset;
output [127:0] result;
reg [127:0] result;
always @(posedge clk or posedge reset)
begin
if (reset)
result = 0;
else
result = result + 1;
end
endmodule

25
openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v Normal file
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@ -0,0 +1,25 @@
module counter_tb;
reg clk, reset;
wire [127:0] result;
counter DUT(
.clk(clk),
.reset(reset),
.result(result)
);
initial begin
#0 reset = 1'b1; clk = 1'b0;
#100 reset = 1'b0;
end
always begin
#10 clk = ~clk;
end
initial begin
#5000 $stop;
end
endmodule

25
openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v Normal file
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@ -0,0 +1,25 @@
///////////////////////////////////////////
// Functionality: Counter with asynchronous reset
// Author: Xifan Tang
////////////////////////////////////////
module counter (
clk,
resetb,
result
);
input clk;
input resetb;
output [127:0] result;
reg [127:0] result;
always @(posedge clk or negedge resetb)
begin
if (~resetb)
result = 0;
else
result = result + 1;
end
endmodule

25
openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v Normal file
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@ -0,0 +1,25 @@
module counter_tb;
reg clk, resetb;
wire [127:0] result;
counter DUT(
.clk(clk),
.resetb(resetb),
.result(result)
);
initial begin
#0 reset = 1'b0; clk = 1'b0;
#100 reset = 1'b1;
end
always begin
#10 clk = ~clk;
end
initial begin
#5000 $stop;
end
endmodule

2
openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v → openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v
View File

@ -1,4 +1,4 @@
module counter4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
input clk0;
input rst0;

6
openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v → openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v
View File

@ -1,4 +1,4 @@
module counter4bit_2clock_tb;
module counter_4bit_2clock_tb;
reg clk0, rst0;
wire [3:0] q0;
@ -6,12 +6,12 @@ module counter4bit_2clock_tb;
reg clk1, rst1;
wire [3:0] q1;
counter_2clock C_1(
counter_4bit_2clock C_1(
clk0,
q0,
rst0);
counter_2clock C_1(
counter_4bit_2clock C_1(
clk1,
q1,
rst1);

0
openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v → openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
View File

0
openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter_tb.v → openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v
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25
openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v Normal file
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@ -0,0 +1,25 @@
///////////////////////////////////////////
// Functionality: Counter with asynchronous reset
// Author: Xifan Tang
////////////////////////////////////////
module counter (
clk,
resetb,
result
);
input clk;
input resetb;
output [7:0] result;
reg [7:0] result;
always @(posedge clk or negedge resetb)
begin
if (!resetb)
result = 0;
else
result = result + 1;
end
endmodule

25
openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v Normal file
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@ -0,0 +1,25 @@
module counter_tb;
reg clk, resetb;
wire [7:0] result;
counter DUT(
.clk(clk),
.resetb(resetb),
.result(result)
);
initial begin
#0 resetb = 1'b0; clk = 1'b0;
#100 resetb = 1'b1;
end
always begin
#10 clk = ~clk;
end
initial begin
#5000 $stop;
end
endmodule

0
openfpga_flow/benchmarks/micro_benchmark/counter/counter.v → openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v
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0
openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v → openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v
View File

22
openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v Normal file
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@ -0,0 +1,22 @@
//-------------------------------------------------------
// Functionality: A 18-bit multiply-acculumate circuit
// Author: Xifan Tang
//-------------------------------------------------------
module mac_18(a, b, c, out);
parameter DATA_WIDTH = 18; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule

22
openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v Normal file
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@ -0,0 +1,22 @@
//-------------------------------------------------------
// Functionality: A 20-bit multiply-acculumate circuit
// Author: Xifan Tang
//-------------------------------------------------------
module mac_20(a, b, c, out);
parameter DATA_WIDTH = 20; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule

22
openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v Normal file
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@ -0,0 +1,22 @@
//-------------------------------------------------------
// Functionality: A 36-bit multiply-acculumate circuit
// Author: Xifan Tang
//-------------------------------------------------------
module mac_36(a, b, c, out);
parameter DATA_WIDTH = 4; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule

25
openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v Normal file
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@ -0,0 +1,25 @@
//-------------------------------------------------------
// Functionality:
// - A 8-bit multiply-acculumate circuit
// - A 9-bit multiply-acculumate circuit
// Author: Xifan Tang
//-------------------------------------------------------
module mac_8_9(a, b, c, out);
parameter DATA_WIDTH = 18; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out[8:0] = a[8:0] * b[8:0] + c[8:0];
assign out[17:9] = a[17:9] * b[17:9] + c[17:9];
endmodule

22
openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v Normal file
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@ -0,0 +1,22 @@
//-------------------------------------------------------
// Functionality: A 9-bit multiply-acculumate circuit
// Author: Xifan Tang
//-------------------------------------------------------
module mac_9(a, b, c, out);
parameter DATA_WIDTH = 9; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule

50
openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v Normal file
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@ -0,0 +1,50 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/03/2021 03:25:29 PM
// Design Name:
// Module Name: clk_divider
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Uncomment if using Vivado to synthesize the design. This will enable the initial block
// If using Yosys, initial blocks are not supported, and cannot be included.
// `define VIVADO_SYNTHESIS
module clock_divider (
input clk_in,
output reg clk_out
);
parameter CLK_DIVIDER_SIZE=8;
reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter;
`ifdef VIVADO_SYNTHESIS
initial begin
clkdiv_counter <= 0;
clk_out <= 0;
end
`endif
// Divide pl_clk (50MHz) to 1MHz
always @(posedge clk_in) begin
if (clkdiv_counter == 1 << CLK_DIVIDER_SIZE - 1) begin
clk_out <= ~clk_out;
end
clkdiv_counter <= clkdiv_counter +1;
end
endmodule

82
openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v Normal file
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@ -0,0 +1,82 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/03/2021 03:37:44 PM
// Design Name:
// Module Name: pulse_generator
// Project Name:
// Target Devices:
// Tool Versions:
// Description: A simple pulse generator with configurable initial values and waiting cycles
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Uncomment if using Vivado to synthesize the design. This will enable the initial block
// If using Yosys, initial blocks are not supported, and cannot be included.
// `define VIVADO_SYNTHESIS
module pulse_generator(
input clk_in,
input repeated, // Specify if the pulse should be generated repeatedly
output reg pulse
);
parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value
parameter WAIT_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied
parameter PULSE_WIDTH=1; // Define the length of the pulse width
parameter PULSE_COUNTER_SIZE=10; // Define the size of the pulse width counter
reg [WAIT_CYCLES<=2 ? 2 : $clog2(WAIT_CYCLES) : 0] wait_cycle_counter; // Size of wait counter is determined by WAIT_CYCLES
reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter;
reg pulse_start;
reg pulse_end;
`ifdef VIVADO_SYNTHESIS
initial begin
pulse <= INITIAL_VALUE;
pulse_start <= 1'b0;
pulse_end <= 1'b0;
wait_cycle_counter <= 0;
pulse_width_counter <= 0;
end
`endif
// Wait a number of clock cycles, hold the initial value
always @(posedge clk_in) begin
if (wait_cycle_counter == WAIT_CYCLES) begin
pulse_start <= 1'b1;
end
if (~pulse_start) begin
wait_cycle_counter <= wait_cycle_counter + 1;
end
end
// Wait a number of clock cycles, hold the initial value
always @(posedge clk_in) begin
pulse <= INITIAL_VALUE;
if (pulse_start && ~pulse_end) begin
// Reach the pulse width limit, stop counting
if (pulse_width_counter < PULSE_WIDTH) begin
pulse <= ~INITIAL_VALUE;
if (~repeated) begin
pulse_end = 1'b1;
end
end
// When pulse ends, flip to initial value
if (pulse_end) begin
pulse <= INITIAL_VALUE;
end
pulse_width_counter <= pulse_width_counter + 1;
end
end
endmodule

53
openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v Normal file
View File

@ -0,0 +1,53 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/03/2021 04:52:18 PM
// Design Name:
// Module Name: reset_generator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Uncomment if using Vivado to synthesize the design. This will enable the initial block
// If using Yosys, initial blocks are not supported, and cannot be included.
// `define VIVADO_SYNTHESIS
module reset_generator(
input clk,
output reg pulse
);
parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value
parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied
reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter;
`ifdef VIVADO_SYNTHESIS
initial begin
clkdiv_counter <= 0;
active_cycle_counter <= 0;
pulse <= INITIAL_VALUE;
end
`endif
// Wait a number of clock cycles, hold the initial value
always @(posedge clk) begin
if (active_cycle_counter == ACTIVE_CYCLES) begin
pulse <= ~pulse;
end else begin
active_cycle_counter <= active_cycle_counter + 1;
end
end
endmodule

24
openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
View File

@ -139,15 +139,15 @@
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
</circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
@ -220,20 +220,34 @@
</pb_type>
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFRQ" mode_bits="0"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:2]"/>
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0">
<port name="clk" physical_mode_port="C"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0"/>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1">
<port name="RN" physical_mode_port="R"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
<port name="clk" physical_mode_port="C"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="0" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="1" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
<port name="RN" physical_mode_port="R"/>
</pb_type>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

127
openfpga_flow/openfpga_cell_library/verilog/dff.v
View File

@ -20,12 +20,7 @@ always @ (posedge CK) begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
`else
assign Q = 1'bZ;
`endif
assign Q = q_reg;
endmodule //End Of Module
@ -46,14 +41,8 @@ always @ (posedge CK) begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -79,12 +68,7 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
`else
assign Q = 1'bZ;
`endif
assign Q = q_reg;
endmodule //End Of Module
@ -111,14 +95,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -144,14 +122,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -178,14 +150,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -211,14 +177,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -249,14 +209,8 @@ end else begin
q_reg <= D;
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module
@ -292,9 +246,9 @@ endmodule //End Of Module
//-----------------------------------------------------
// Function : A multi-functional D-type flip-flop with
// - asynchronous reset
// which can be switched between active-low and active hight
// - asynchronous set which can be switched
// which can be switched between active-low and active hight
// which can be switched between active-low and active high
// - asynchronous set
// which can be switched between active-low and active high
//-----------------------------------------------------
module MULTI_MODE_DFFSRQ (
input SET, // Set input
@ -305,8 +259,8 @@ module MULTI_MODE_DFFSRQ (
input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
);
wire post_set = mode ? ~SET : SET;
wire post_reset = mode ? ~RST : RST;
wire post_set = mode[1] ? ~SET : SET;
wire post_reset = mode[0] ? ~RST : RST;
DFFSRQ FF_CORE (.SET(post_set),
.RST(post_rst),
@ -317,6 +271,29 @@ DFFSRQ FF_CORE (.SET(post_set),
endmodule //End Of Module
//-----------------------------------------------------
// Function : A multi-functional D-type flip-flop with
// - asynchronous reset
// which can be switched between active-low and active high
//-----------------------------------------------------
module MULTI_MODE_DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
);
wire post_reset = mode ? ~RST : RST;
DFFRQ FF_CORE (.RST(post_rst),
.CK(CK),
.D(D),
.Q(Q)
);
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
@ -349,14 +326,8 @@ end else begin
q_reg <= D;
end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign QN = !Q;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = !Q;
endmodule //End Of Module
@ -462,13 +433,7 @@ end
assign CFGQ = CFGE ? Q : 1'b0;
assign CFGQN = CFGE ? QN : 1'b1;
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign QN = !Q;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
assign Q = q_reg;
assign QN = !Q;
endmodule //End Of Module

4
openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga
View File

@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
# Finish and exit OpenFPGA
exit

4
openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
View File

@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
View File

@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga
View File

@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga
View File

@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga
View File

@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

6
openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
View File

@ -55,9 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitsream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

74
openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga Normal file
View File

@ -0,0 +1,74 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

2
openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga
View File

@ -59,8 +59,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
View File

@ -59,8 +59,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
View File

@ -52,8 +52,6 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --support_icarus_simulator
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis

5
openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
View File

@ -57,9 +57,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

76
openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga Normal file
View File

@ -0,0 +1,76 @@
# Run VPR for the 'and' design
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
# This is due to the Fc_in of clock port is set to 0 for global wiring
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

5
openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga
View File

@ -61,9 +61,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here

20
openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga
View File

@ -37,7 +37,7 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_architecture_bitstream --verbose
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
@ -46,9 +46,7 @@ build_fabric_bitstream --verbose
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC \
--explicit_port_mapping \
--include_timing \
--include_signal_init
# --support_icarus_simulator
--include_timing
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
@ -56,18 +54,8 @@ write_fabric_verilog --file ./SRC \
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Finish and exit OpenFPGA
exit

57
openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga Normal file
View File

@ -0,0 +1,57 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream ${OPENFPGA_EMBEDDED_BITSTREAM_HDL_TYPE} --file ./SRC --explicit_port_mapping
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

75
openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga Normal file
View File

@ -0,0 +1,75 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

12
openfpga_flow/openfpga_shell_scripts/rename_scripts.sh
View File

@ -1,4 +1,12 @@
foreach i (*.openfpga)
sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i
sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i
# sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i
# sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i
end
foreach i (*.openfpga)
sed -i 's/--support_icarus_simulator//g' $i
end
foreach i (*.openfpga)
sed -i 's/write_preconfigured_fabric_wrapper/write_preconfigured_fabric_wrapper --embed_bitstream iverilog/g' $i
end

4
openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

4
openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga
View File

@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
# Write the SDC files for PnR backend
# - Turn on every options here

10
openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
View File

@ -17,6 +17,16 @@ module \$_DFF_PP0_ (D, C, R, Q);
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Async active-low reset
module \$_DFF_PN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
endmodule
// Async reset, enable
module \$_DFFE_PP0P_ (D, C, E, R, Q);
input D;

31
openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
View File

@ -76,6 +76,37 @@ module dffre(
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-low asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffrn(
output reg Q,
input D,
input RN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
(* abc9_flop, lib_whitebox *)
module latchre (
output reg Q,

4
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -53,6 +53,10 @@ run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread
run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
echo -e "Testing testbenches without self checking features";
run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs
run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking --debug --show_thread_logs
echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs

8
openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
View File

@ -137,8 +137,6 @@ echo -e "Testing through channels in tileable routing";
run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
# Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail
#run-task fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators";
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --show_thread_logs
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs

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