From 07257d0ff07517e47ecf0cfae283df42e30c3145 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 13 Mar 2021 10:58:03 -0700 Subject: [PATCH 01/89] [Tool] Patch wrong paths in FPGA-SDC --- .../src/fpga_sdc/analysis_sdc_writer_utils.cpp | 4 ++-- openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 16 +++++++--------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp index 1491d161d..29cd5eae2 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp @@ -103,7 +103,7 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp, VTR_ASSERT(!sink_instance_name.empty()); /* Get the input id that is used! Disable the unused inputs! */ fp << "set_disable_timing "; - fp << parent_instance_name; + fp << parent_instance_name << "/"; fp << sink_instance_name << "/"; fp << generate_sdc_port(sink_port); fp << std::endl; @@ -228,7 +228,7 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp, VTR_ASSERT(!sink_instance_name.empty()); /* Get the input id that is used! Disable the unused inputs! */ fp << "set_disable_timing "; - fp << parent_instance_name; + fp << parent_instance_name << "/"; fp << sink_instance_name << "/"; fp << generate_sdc_port(sink_port); fp << std::endl; diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp index b56f8acf0..352658d2e 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp @@ -83,7 +83,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, t_pb_graph_node* des_pb_graph_node = des_pb_graph_pin->parent_node; /* Find the src module in module manager */ - std::string src_module_name = generate_physical_block_module_name(src_pb_graph_pin->parent_node->pb_type); + std::string src_module_name = generate_physical_block_module_name(src_pb_graph_node->pb_type); ModuleId src_module = module_manager.find_module(src_module_name); VTR_ASSERT(true == module_manager.valid_module_id(src_module)); @@ -104,6 +104,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, src_instance_name += std::to_string(instance_id); src_instance_name += "_"; } else { + VTR_ASSERT_SAFE(true == module_manager.instance_name(parent_module, src_module, instance_id).empty()); src_instance_name += module_manager.instance_name(parent_module, src_module, instance_id); } } @@ -113,7 +114,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, src_port.set_width(src_pb_graph_pin->pin_number, src_pb_graph_pin->pin_number); /* Find the des module in module manager */ - std::string des_module_name = generate_physical_block_module_name(des_pb_graph_pin->parent_node->pb_type); + std::string des_module_name = generate_physical_block_module_name(des_pb_graph_node->pb_type); ModuleId des_module = module_manager.find_module(des_module_name); VTR_ASSERT(true == module_manager.valid_module_id(des_module)); ModulePortId des_module_port_id = module_manager.find_module_port(des_module, generate_pb_type_port_name(des_pb_graph_pin->port)); @@ -133,6 +134,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, des_instance_name += std::to_string(instance_id); des_instance_name += "_"; } else { + VTR_ASSERT_SAFE(true != module_manager.instance_name(parent_module, des_module, instance_id).empty()); des_instance_name += module_manager.instance_name(parent_module, des_module, instance_id); } } @@ -150,17 +152,11 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, /* Give full path if hierarchical is not enabled */ std::string src_module_path = src_instance_name; if (false == hierarchical) { - if (true == src_instance_name.empty()) { - src_instance_name = generate_instance_name(src_module_name, 0); - } src_module_path = module_path + src_instance_name; } std::string des_module_path = des_instance_name; if (false == hierarchical) { - if (true == des_instance_name.empty()) { - des_instance_name = generate_instance_name(des_module_name, 0); - } des_module_path = module_path + des_instance_name; } @@ -521,7 +517,7 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir, rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, time_unit, hierarchical, - format_dir_path(module_path + std::string(physical_mode->pb_type_children[ipb].name)), + format_dir_path(module_path + generate_physical_block_instance_name(&(physical_mode->pb_type_children[ipb]), ipb)), module_manager, device_annotation, &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]), @@ -582,6 +578,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir, VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); std::string module_path = format_dir_path(root_path + grid_module_name); + module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index)); rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, time_unit, @@ -603,6 +600,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir, VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); std::string module_path = format_dir_path(root_path + grid_module_name); + module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index)); rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, time_unit, From 12b44e0eca0c2164d89baff6ceb455d4cac38138 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 13 May 2021 10:04:23 -0600 Subject: [PATCH 02/89] added configuration benchmark files --- .../config_loader/bitstream_loader.v | 195 ++++++++++++++++++ .../benchmarks/config_loader/clock_divider.v | 45 ++++ .../config_loader/configuration_manager.v | 71 +++++++ .../config_loader/pulse_generator.v | 76 +++++++ .../config_loader/reset_generator.v | 47 +++++ .../benchmarks/config_loader/test_top.v | 176 ++++++++++++++++ 6 files changed, 610 insertions(+) create mode 100644 openfpga_flow/benchmarks/config_loader/bitstream_loader.v create mode 100644 openfpga_flow/benchmarks/config_loader/clock_divider.v create mode 100644 openfpga_flow/benchmarks/config_loader/configuration_manager.v create mode 100644 openfpga_flow/benchmarks/config_loader/pulse_generator.v create mode 100644 openfpga_flow/benchmarks/config_loader/reset_generator.v create mode 100644 openfpga_flow/benchmarks/config_loader/test_top.v diff --git a/openfpga_flow/benchmarks/config_loader/bitstream_loader.v b/openfpga_flow/benchmarks/config_loader/bitstream_loader.v new file mode 100644 index 000000000..68b04aee1 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/bitstream_loader.v @@ -0,0 +1,195 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/05/2021 09:43:10 AM +// Design Name: +// Module Name: bitstream_loader +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module bitstream_loader( + input prog_clk, + input start, + output config_chain_head, + output reg done + ); + + parameter BITSTREAM_FILE=""; + parameter BITSTREAM_SIZE=6140; + + reg [BITSTREAM_SIZE<=2 ? 2 : $clog2(BITSTREAM_SIZE):0] bitstream_index; + + reg [13:0] bram_addr; + reg [3:0] bram_line_index; + + wire bram_output; + assign config_chain_head = bram_output; + + RAMB18E1 #( + // Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE" + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + // Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") + .SIM_COLLISION_CHECK("ALL"), + // RAM Mode: "SDP" or "TDP" + .RAM_MODE("TDP"), + // READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port + .READ_WIDTH_A(1), // 0-72 + .READ_WIDTH_B(0), // 0-18 + .WRITE_WIDTH_A(0), // 0-18 + .WRITE_WIDTH_B(0), // 0-72 + + .INIT_00(256'h00000000000000000000000000000000000000000000007f00000000000000ff), + .INIT_01(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h00000003f8000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000078000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + + + + // RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE") + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + // SRVAL_A, SRVAL_B: Set/reset value for output + .SRVAL_A(18'hFFFFF), + .SRVAL_B(18'h00000), + // Simulation Device: Must be set to "7SERIES" for simulation behavior + .SIM_DEVICE("7SERIES"), + // WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE") + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST") + ) + RAMB18E1_inst ( + // Port A Data: 16-bit (each) output: Port A data + .DOADO(bram_output), // 16-bit output: A port data/LSB data + .DOPADOP(), // 2-bit output: A port parity/LSB parity + // Port B Data: 16-bit (each) output: Port B data + .DOBDO(), // 16-bit output: B port data/MSB data + .DOPBDOP(), // 2-bit output: B port parity/MSB parity + // Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port + // when RAM_MODE="SDP") + .ADDRARDADDR(bram_addr), // 14-bit input: A port address/Read address + .CLKARDCLK(~prog_clk), // 1-bit input: A port clock/Read clock + .ENARDEN(1'b1), // 1-bit input: A port enable/Read enable + .REGCEAREGCE(1'b1), // 1-bit input: A port register enable/Register enable + .RSTRAMARSTRAM(0), // 1-bit input: A port set/reset + .RSTREGARSTREG(0), // 1-bit input: A port register set/reset + .WEA(2'b00), // 2-bit input: A port write enable + // Port A Data: 16-bit (each) input: Port A data + .DIADI(0), // 16-bit input: A port data/LSB data + .DIPADIP(0), // 2-bit input: A port parity/LSB parity + // Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port + // when RAM_MODE="SDP") + .ADDRBWRADDR(0), // 14-bit input: B port address/Write address + .CLKBWRCLK(0), // 1-bit input: B port clock/Write clock + .ENBWREN(0), // 1-bit input: B port enable/Write enable + .REGCEB(0), // 1-bit input: B port register enable + .RSTRAMB(0), // 1-bit input: B port set/reset + .RSTREGB(0), // 1-bit input: B port register set/reset + .WEBWE(0), // 4-bit input: B port write enable/Write enable + // Port B Data: 16-bit (each) input: Port B data + .DIBDI(0), // 16-bit input: B port data/MSB data + .DIPBDIP(0) // 2-bit input: B port parity/MSB parity + ); + + + initial begin + bram_addr <= 0; + bram_line_index <= 0; + bitstream_index <= 0; + done <= 1'b0; + end + + always @(posedge prog_clk) begin + if (start && !done) begin + + bram_addr <= bram_addr + 1; + bitstream_index <= bitstream_index + 1; + end + if (bitstream_index == BITSTREAM_SIZE) begin + done <= 1'b1; + end + end + + +endmodule + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/benchmarks/config_loader/clock_divider.v b/openfpga_flow/benchmarks/config_loader/clock_divider.v new file mode 100644 index 000000000..4127cd9f3 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/clock_divider.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 03:25:29 PM +// Design Name: +// Module Name: clk_divider +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clock_divider ( + input clk_in, + output reg clk_out + ); + + parameter CLK_DIVIDER_SIZE=8; + + reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; + + initial begin + clkdiv_counter <= 0; + clk_out <= 0; + end + + // Divide pl_clk (50MHz) to 1MHz + always @(posedge clk_in) begin + if (clkdiv_counter == 1 << CLK_DIVIDER_SIZE - 1) begin + clk_out <= ~clk_out; + end + clkdiv_counter <= clkdiv_counter +1; + end + +endmodule diff --git a/openfpga_flow/benchmarks/config_loader/configuration_manager.v b/openfpga_flow/benchmarks/config_loader/configuration_manager.v new file mode 100644 index 000000000..e3c20c2c1 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/configuration_manager.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/05/2021 10:29:55 AM +// Design Name: +// Module Name: configuration_manager +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`include "clock_divider.v" +`include "pulse_generator.v" + +module configuration_manager( + input clk_in, + output prog_reset, + output prog_clk, + output ccff_head, + output configuration_done + ); + + parameter START_CYCLE=3; // Start configuration on cycle 3 of prog_clk + parameter CONFIGURATION_CLK_DIV_SIZE=12; // Divide clk_in (50MHz) by 4096 (2^12) times + + wire prog_clk_out; // prog_clk signal from clk_divider + wire ccff_head_out; + + assign ccff_head = ccff_head_out & ~prog_reset; + assign prog_clk = prog_clk_out & ~configuration_done; // prog_clk will stop when configuration done + + // PRESET + // Programming reset will be enabled until START_CYCLE + reset_generator #( + .INITIAL_VALUE(1), + .ACTIVE_CYCLES(START_CYCLE) + ) prog_reset_generator( + .clk(~prog_clk), + .pulse(prog_reset) + ); + + + // PROG_CLK + // Divide pl_clk (50MHz) by 4096 (2^12) times + clock_divider #( + .CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE) + ) prog_clk_divider ( + .clk_in(clk_in), + .clk_out(prog_clk_out) + ); + + + // Instantiate bitstream loader + bitstream_loader loader ( + .prog_clk(prog_clk), + .config_chain_head(ccff_head_out), + .start(~prog_reset), + .done(configuration_done) + ); + +endmodule diff --git a/openfpga_flow/benchmarks/config_loader/pulse_generator.v b/openfpga_flow/benchmarks/config_loader/pulse_generator.v new file mode 100644 index 000000000..a73fc37f6 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/pulse_generator.v @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 03:37:44 PM +// Design Name: +// Module Name: pulse_generator +// Project Name: +// Target Devices: +// Tool Versions: +// Description: A simple pulse generator with configurable initial values and waiting cycles +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module pulse_generator( + input clk_in, + input repeated, // Specify if the pulse should be generated repeatedly + output reg pulse + ); + + + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value + parameter WAIT_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied + parameter PULSE_WIDTH=1; // Define the length of the pulse width + parameter PULSE_COUNTER_SIZE=10; // Define the size of the pulse width counter + + reg [WAIT_CYCLES<=2 ? 2 : $clog2(WAIT_CYCLES) : 0] wait_cycle_counter; // Size of wait counter is determined by WAIT_CYCLES + reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter; + reg pulse_start; + reg pulse_end; + + initial begin + pulse <= INITIAL_VALUE; + pulse_start <= 1'b0; + pulse_end <= 1'b0; + wait_cycle_counter <= 0; + pulse_width_counter <= 0; + end + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk_in) begin + if (wait_cycle_counter == WAIT_CYCLES) begin + pulse_start <= 1'b1; + end + if (~pulse_start) begin + wait_cycle_counter <= wait_cycle_counter + 1; + end + end + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk_in) begin + pulse <= INITIAL_VALUE; + if (pulse_start && ~pulse_end) begin + // Reach the pulse width limit, stop counting + if (pulse_width_counter < PULSE_WIDTH) begin + pulse <= ~INITIAL_VALUE; + if (~repeated) begin + pulse_end = 1'b1; + end + end + // When pulse ends, flip to initial value + if (pulse_end) begin + pulse <= INITIAL_VALUE; + end + pulse_width_counter <= pulse_width_counter + 1; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/config_loader/reset_generator.v b/openfpga_flow/benchmarks/config_loader/reset_generator.v new file mode 100644 index 000000000..f949e722a --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/reset_generator.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 04:52:18 PM +// Design Name: +// Module Name: reset_generator +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module reset_generator( + input clk, + output reg pulse + ); + + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value + parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied + + reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; + + initial begin + pulse <= INITIAL_VALUE; + active_cycle_counter <= 0; + end + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk) begin + if (active_cycle_counter == ACTIVE_CYCLES) begin + pulse <= ~INITIAL_VALUE; + end else begin + active_cycle_counter <= active_cycle_counter + 1; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/config_loader/test_top.v b/openfpga_flow/benchmarks/config_loader/test_top.v new file mode 100644 index 000000000..e9a9c3783 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/test_top.v @@ -0,0 +1,176 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/11/2021 03:01:46 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`include "clock_divider.v" +`include "pulse_generator.v" + +module test_top ( + input sys_clk, + + + // Commented out i/o means it is floating and inaccessable to MPSoC + + // input LUT5_OUT_1_pad, + input GPIO3_pad, + input GPIO0_pad, + input CC_SPYPAD_1_pad, + // input PERF_SPYPAD_0_pad, + // input LUT5_OUT_0_pad, + output RESET_pad, + output CLK_pad, + // input GPIO4_pad, + // input GPIO5_pad, + input GPIO2_pad, + input GPIO1_pad, + input LUT6_OUT_0_pad, + input TEST_EN_pad, + input LUT4_OUT_0_pad, + // input LUT4_OUT_1_pad, + // input LUT4_OUT_2_pad, + // input LUT4_OUT_3_pad, + input SC_HEAD_pad, + input CCFF_TAIL_pad, + input GPIO23_pad, + input GPIO11_pad, + // input GPIO21_pad, + input GPIO22_pad, + input GPIO20_pad, + input GPIO10_pad, + input GPIO8_pad, + input GPIO9_pad, + input GPIO18_pad, + input GPIO19_pad, + input GPIO6_pad, + input GPIO7_pad, + input CC_SPYPAD_0_pad, + input CC_SPYPAD_2_pad, + input SC_TAIL_pad, + input COUT_SPYPAD_0_pad, + output CCFF_HEAD_pad, + // input SHIFTREG_SPY_pad, + // input SC_SPYPAD_0_pad, + output PRESET_pad, + input GPIO12_pad, + input GPIO16_pad, + // input GPIO15_pad, + // input GPIO14_pad, + input GPIO13_pad, + output PROG_CLK_pad, + input GPIO17_pad, + + + output t0_pad, + output t1_pad, + output t2_pad, + input t3_pad, + + output t0_is_output, + output t1_is_output, + output t2_is_output, + output t3_is_output + ); + + + parameter RESET_LENGTH=10; // Start off test with 10 cycle reset + parameter TEST_START_CYCLE=11; // Start the test on cycle 11 + + // Local signals + wire logic_reset; + wire prog_reset; + + wire logic_clk; + wire prog_clk; + + wire ccff_head; + wire configuration_done; + + // ****** GF12 Inputs / MPSoC Outputs ****** + assign RESET_pad = logic_reset; + assign SC_HEAD_pad = 0; + assign CCFF_HEAD_pad = ccff_head; + assign PRESET_pad = prog_reset; + assign PROG_CLK_pad = prog_clk; + assign CLK_pad = logic_clk; + assign TEST_EN_pad = 0; + // ************************* + + + // ******* MPSoC GPIO (4 inputs/outputs) ******* + assign t0_pad = 0; + assign t1_pad = 0; + assign t2_pad = 0; +// assign start_signal = t3_pad; + + assign t0_is_output = 1; + assign t1_is_output = 1; + assign t2_is_output = 1; + assign t3_is_output = 0; + // ******************************************** + + + // ########################### CLOCKS ########################### + + // CLK + // Divide pl_clk (50MHz) by 67108864 (2^26) times + clock_divider #( + .CLK_DIVIDER_SIZE(26) + ) logic_clk_divider ( + .clk_in(sys_clk), + .clk_out(logic_clk) + ); + + // ############################################################## + + + + + // ########################### RESETS ########################### + + // RESET + // Logic reset will be enabled in the first 2 clock cycles + reset_generator #( + .INITIAL_VALUE(1), + .ACTIVE_CYCLES(100) + ) logic_reset_generator( + .clk(sys_clk), + .pulse(logic_reset) + ); + + // ############################################################## + + + + + // ####################### CONFIGURATION ####################### + + // Configuration manager + configuration_manager config_manager ( + .clk_in(sys_clk), + .prog_reset(prog_reset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .configuration_done(configuration_done) + ); + + // ############################################################## + + +endmodule \ No newline at end of file From 3cfc42cdf933326c805bfdf840b1c9a0e371c6f5 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Tue, 15 Jun 2021 14:16:31 -0600 Subject: [PATCH 03/89] added testbench CI --- .../benchmarks/config_loader/test_top.v | 176 ------------------ .../config_loader/bitstream_loader.v | 0 .../config_loader/configuration_manager.v | 0 .../signal_gen}/clock_divider.v | 0 .../signal_gen}/pulse_generator.v | 0 .../signal_gen}/reset_generator.v | 0 .../benchmark_sweep_test.sh | 11 ++ .../signal_gen/config/task.conf | 38 ++++ 8 files changed, 49 insertions(+), 176 deletions(-) delete mode 100644 openfpga_flow/benchmarks/config_loader/test_top.v rename openfpga_flow/benchmarks/{ => micro_benchmark}/config_loader/bitstream_loader.v (100%) rename openfpga_flow/benchmarks/{ => micro_benchmark}/config_loader/configuration_manager.v (100%) rename openfpga_flow/benchmarks/{config_loader => micro_benchmark/signal_gen}/clock_divider.v (100%) rename openfpga_flow/benchmarks/{config_loader => micro_benchmark/signal_gen}/pulse_generator.v (100%) rename openfpga_flow/benchmarks/{config_loader => micro_benchmark/signal_gen}/reset_generator.v (100%) create mode 100755 openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh create mode 100644 openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf diff --git a/openfpga_flow/benchmarks/config_loader/test_top.v b/openfpga_flow/benchmarks/config_loader/test_top.v deleted file mode 100644 index e9a9c3783..000000000 --- a/openfpga_flow/benchmarks/config_loader/test_top.v +++ /dev/null @@ -1,176 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 03/11/2021 03:01:46 PM -// Design Name: -// Module Name: top -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - -`include "clock_divider.v" -`include "pulse_generator.v" - -module test_top ( - input sys_clk, - - - // Commented out i/o means it is floating and inaccessable to MPSoC - - // input LUT5_OUT_1_pad, - input GPIO3_pad, - input GPIO0_pad, - input CC_SPYPAD_1_pad, - // input PERF_SPYPAD_0_pad, - // input LUT5_OUT_0_pad, - output RESET_pad, - output CLK_pad, - // input GPIO4_pad, - // input GPIO5_pad, - input GPIO2_pad, - input GPIO1_pad, - input LUT6_OUT_0_pad, - input TEST_EN_pad, - input LUT4_OUT_0_pad, - // input LUT4_OUT_1_pad, - // input LUT4_OUT_2_pad, - // input LUT4_OUT_3_pad, - input SC_HEAD_pad, - input CCFF_TAIL_pad, - input GPIO23_pad, - input GPIO11_pad, - // input GPIO21_pad, - input GPIO22_pad, - input GPIO20_pad, - input GPIO10_pad, - input GPIO8_pad, - input GPIO9_pad, - input GPIO18_pad, - input GPIO19_pad, - input GPIO6_pad, - input GPIO7_pad, - input CC_SPYPAD_0_pad, - input CC_SPYPAD_2_pad, - input SC_TAIL_pad, - input COUT_SPYPAD_0_pad, - output CCFF_HEAD_pad, - // input SHIFTREG_SPY_pad, - // input SC_SPYPAD_0_pad, - output PRESET_pad, - input GPIO12_pad, - input GPIO16_pad, - // input GPIO15_pad, - // input GPIO14_pad, - input GPIO13_pad, - output PROG_CLK_pad, - input GPIO17_pad, - - - output t0_pad, - output t1_pad, - output t2_pad, - input t3_pad, - - output t0_is_output, - output t1_is_output, - output t2_is_output, - output t3_is_output - ); - - - parameter RESET_LENGTH=10; // Start off test with 10 cycle reset - parameter TEST_START_CYCLE=11; // Start the test on cycle 11 - - // Local signals - wire logic_reset; - wire prog_reset; - - wire logic_clk; - wire prog_clk; - - wire ccff_head; - wire configuration_done; - - // ****** GF12 Inputs / MPSoC Outputs ****** - assign RESET_pad = logic_reset; - assign SC_HEAD_pad = 0; - assign CCFF_HEAD_pad = ccff_head; - assign PRESET_pad = prog_reset; - assign PROG_CLK_pad = prog_clk; - assign CLK_pad = logic_clk; - assign TEST_EN_pad = 0; - // ************************* - - - // ******* MPSoC GPIO (4 inputs/outputs) ******* - assign t0_pad = 0; - assign t1_pad = 0; - assign t2_pad = 0; -// assign start_signal = t3_pad; - - assign t0_is_output = 1; - assign t1_is_output = 1; - assign t2_is_output = 1; - assign t3_is_output = 0; - // ******************************************** - - - // ########################### CLOCKS ########################### - - // CLK - // Divide pl_clk (50MHz) by 67108864 (2^26) times - clock_divider #( - .CLK_DIVIDER_SIZE(26) - ) logic_clk_divider ( - .clk_in(sys_clk), - .clk_out(logic_clk) - ); - - // ############################################################## - - - - - // ########################### RESETS ########################### - - // RESET - // Logic reset will be enabled in the first 2 clock cycles - reset_generator #( - .INITIAL_VALUE(1), - .ACTIVE_CYCLES(100) - ) logic_reset_generator( - .clk(sys_clk), - .pulse(logic_reset) - ); - - // ############################################################## - - - - - // ####################### CONFIGURATION ####################### - - // Configuration manager - configuration_manager config_manager ( - .clk_in(sys_clk), - .prog_reset(prog_reset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .configuration_done(configuration_done) - ); - - // ############################################################## - - -endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/config_loader/bitstream_loader.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/bitstream_loader.v rename to openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v diff --git a/openfpga_flow/benchmarks/config_loader/configuration_manager.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/configuration_manager.v rename to openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v diff --git a/openfpga_flow/benchmarks/config_loader/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/clock_divider.v rename to openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v diff --git a/openfpga_flow/benchmarks/config_loader/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/pulse_generator.v rename to openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v diff --git a/openfpga_flow/benchmarks/config_loader/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/reset_generator.v rename to openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v diff --git a/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh b/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh new file mode 100755 index 000000000..01f278fe9 --- /dev/null +++ b/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## + +echo -e "Benchmark sweep tests"; +run-task benchmark_sweep/signal_gen --debug --show_thread_logs \ No newline at end of file diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf new file mode 100644 index 000000000..b1f3d4e47 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v + +[SYNTHESIS_PARAM] +bench0_top = pulse_generator +# bench1_top = reset_generator +# bench2_top = clock_divider + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From 96cb3081abf1aa90abd1e977476da88d0d779cdb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Jun 2021 09:51:16 -0600 Subject: [PATCH 04/89] Update fix_device_route_chan_width_example_script.openfpga --- .../fix_device_route_chan_width_example_script.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index d31ffe36c..fe7679f65 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitsream.bit +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator From 0e01177cf08f015eb044cb9d28b772eca739ad14 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Jun 2021 11:01:45 -0600 Subject: [PATCH 05/89] [Script] Now openfpga flow script output detailed error message when task is not found --- openfpga_flow/scripts/run_fpga_task.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index e8543a402..29a584505 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -174,7 +174,7 @@ def generate_each_task_actions(taskname): elif os.path.isdir(repo_tasks): curr_task_dir = repo_tasks else: - clean_up_and_exit("Task directory [%s] not found" % curr_task_dir) + clean_up_and_exit("Task directory not found" % taskname + " locally at [%s]" % local_tasks + " or in OpenFPGA task directory [%s]" % repo_tasks) os.chdir(curr_task_dir) From fce84e564d25c442a48c1657ac48bd7c970c5711 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Jun 2021 11:20:35 -0600 Subject: [PATCH 06/89] [Script] Patch on missing string to show in error message --- openfpga_flow/scripts/run_fpga_task.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 29a584505..5663cc55c 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -174,7 +174,7 @@ def generate_each_task_actions(taskname): elif os.path.isdir(repo_tasks): curr_task_dir = repo_tasks else: - clean_up_and_exit("Task directory not found" % taskname + " locally at [%s]" % local_tasks + " or in OpenFPGA task directory [%s]" % repo_tasks) + clean_up_and_exit("Task directory [%s] not found" % taskname + " locally at [%s]" % local_tasks + " or in OpenFPGA task directory [%s]" % repo_tasks) os.chdir(curr_task_dir) From fed975c52a782c604c443e3b2e21a295481a2c27 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Jun 2021 16:13:50 -0600 Subject: [PATCH 07/89] [Tool] Add postfix removal support in write_io_mapping command --- .../src/openfpga_reserved_words.h | 3 +++ openfpga/src/base/openfpga_bitstream.cpp | 9 ++++++++- .../src/fpga_bitstream/build_io_mapping_info.cpp | 16 ++++++++++++++-- .../src/fpga_bitstream/build_io_mapping_info.h | 3 ++- .../verilog_formal_random_top_testbench.cpp | 1 + .../src/fpga_verilog/verilog_testbench_utils.h | 3 --- 6 files changed, 28 insertions(+), 7 deletions(-) diff --git a/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h b/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h index 2f9bae817..732247178 100644 --- a/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h +++ b/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h @@ -59,6 +59,9 @@ constexpr char* DEFAULT_LB_DIR_NAME = "lb/"; constexpr char* DEFAULT_RR_DIR_NAME = "routing/"; constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/"; +constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:"; +constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_"; + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index 78e0cbddd..b978b200d 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -10,6 +10,7 @@ /* Headers from openfpgautil library */ #include "openfpga_digest.h" +#include "openfpga_reserved_words.h" /* Headers from fpgabitstream library */ #include "read_xml_arch_bitstream.h" @@ -153,6 +154,11 @@ int write_io_mapping(const OpenfpgaContext& openfpga_ctx, ModuleId top_module = openfpga_ctx.module_graph().find_module(top_module_name); VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module)); + /* VPR added a prefix to the output ports, remove them here */ + std::vector prefix_to_remove; + prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX)); + prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX)); + IoMap io_map = build_fpga_io_mapping_info(openfpga_ctx.module_graph(), top_module, g_vpr_ctx.atom(), @@ -160,7 +166,8 @@ int write_io_mapping(const OpenfpgaContext& openfpga_ctx, openfpga_ctx.io_location_map(), openfpga_ctx.vpr_netlist_annotation(), std::string(), - std::string()); + std::string(), + prefix_to_remove); status = write_io_mapping_to_xml_file(io_map, cmd_context.option_value(cmd, opt_file), diff --git a/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp b/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp index 76fbda9a2..3eb10fe37 100644 --- a/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp +++ b/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp @@ -37,7 +37,8 @@ IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager, const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& io_input_port_name_postfix, - const std::string& io_output_port_name_postfix) { + const std::string& io_output_port_name_postfix, + const std::vector& output_port_prefix_to_remove) { IoMap io_map; /* Only mappable i/o ports can be considered */ @@ -129,7 +130,18 @@ IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager, benchmark_io_port.set_width(1); } else { VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)); - benchmark_io_port.set_name(std::string(block_name + io_output_port_name_postfix)); + /* VPR may have added a prefix to the output ports, remove them here */ + std::string output_block_name = block_name; + for (const std::string& prefix_to_remove : output_port_prefix_to_remove) { + if (!prefix_to_remove.empty()) { + if (0 == output_block_name.find(prefix_to_remove)) { + output_block_name.erase(0, prefix_to_remove.length()); + break; + } + } + } + + benchmark_io_port.set_name(std::string(output_block_name + io_output_port_name_postfix)); benchmark_io_port.set_width(1); } diff --git a/openfpga/src/fpga_bitstream/build_io_mapping_info.h b/openfpga/src/fpga_bitstream/build_io_mapping_info.h index 615fafdd8..01f4b1d61 100644 --- a/openfpga/src/fpga_bitstream/build_io_mapping_info.h +++ b/openfpga/src/fpga_bitstream/build_io_mapping_info.h @@ -26,7 +26,8 @@ IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager, const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& io_input_port_name_postfix, - const std::string& io_output_port_name_postfix); + const std::string& io_output_port_name_postfix, + const std::vector& output_port_prefix_to_remove); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 710a0312d..ffc15437b 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -16,6 +16,7 @@ /* Headers from openfpgautil library */ #include "openfpga_port.h" #include "openfpga_digest.h" +#include "openfpga_reserved_words.h" #include "openfpga_atom_netlist_utils.h" #include "simulation_utils.h" diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 807d25ae5..1f9567481 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -23,9 +23,6 @@ /* begin namespace openfpga */ namespace openfpga { -constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:"; -constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_"; - void print_verilog_testbench_fpga_instance(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, From cbbf601edc88a49fbfeae12ac04c69ccc89bec38 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Jun 2021 16:20:13 -0600 Subject: [PATCH 08/89] [Tool] Fix a compiler warning due to uninitialized data structure --- openfpga/src/fabric/build_top_module_connection.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 3fde3ee9c..03b04cd03 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -747,6 +747,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana /* Find the port of the grid module according to the tile annotation */ int grid_pin_start_index = physical_tile->num_pins; t_physical_tile_port physical_tile_port; + physical_tile_port.num_pins = 0; for (const t_physical_tile_port& tile_port : physical_tile->ports) { if (std::string(tile_port.name) == tile_port_to_connect.get_name()) { BasicPort ref_tile_port(tile_port.name, tile_port.num_pins); From f9e66e1bae4e3b16c452e5bea20d1c793e9b94b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Jun 2021 15:27:12 -0600 Subject: [PATCH 09/89] [Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name; --- openfpga_flow/scripts/run_fpga_task.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 5663cc55c..7855a54fd 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -309,7 +309,7 @@ def generate_each_task_actions(taskname): for indx, arch in enumerate(archfile_list): for bench in benchmark_list: for lbl, param in bench["script_params"].items(): - flow_run_dir = get_flow_rundir(arch, bench["top_module"], lbl) + flow_run_dir = get_flow_rundir(arch, benchmark_list.index(bench), bench["top_module"], lbl) command = create_run_command( curr_job_dir=flow_run_dir, archfile=arch, @@ -330,11 +330,12 @@ def generate_each_task_actions(taskname): logger.info('Created total %d jobs' % len(flow_run_cmd_list)) return flow_run_cmd_list - -def get_flow_rundir(arch, top_module, flow_params=None): +# Make the directory name unique by including the benchmark index in the list. +# This is because benchmarks may share the same top module names +def get_flow_rundir(arch, bench_index, top_module, flow_params=None): path = [ os.path.basename(arch).replace(".xml", ""), - top_module, + "bench" + str(bench_index) + "_" + top_module, flow_params if flow_params else "common" ] return os.path.abspath(os.path.join(*path)) From 07dcf3ad27bd7de8b8303f693fb37dd394439548 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Jun 2021 16:48:35 -0600 Subject: [PATCH 10/89] [HDL] Add more micro benchmarks for counter, and-gate and mac unit --- .../benchmarks/micro_benchmark/and4/and4.v | 22 ++++++++++++++++ .../counter_128bit_async_reset/counter.v | 25 +++++++++++++++++++ .../counter_128bit_async_reset/counter_tb.v | 25 +++++++++++++++++++ .../counter_128bit_async_resetb/counter.v | 25 +++++++++++++++++++ .../counter_128bit_async_resetb/counter_tb.v | 25 +++++++++++++++++++ .../micro_benchmark/mac/mac_18/mac_18.v | 22 ++++++++++++++++ .../micro_benchmark/mac/mac_20/mac_20.v | 22 ++++++++++++++++ .../micro_benchmark/mac/mac_36/mac_36.v | 22 ++++++++++++++++ .../micro_benchmark/mac/mac_8_9/mac_8_9.v | 25 +++++++++++++++++++ .../micro_benchmark/mac/mac_9/mac_9.v | 22 ++++++++++++++++ 10 files changed, 235 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and4/and4.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/and4/and4.v b/openfpga_flow/benchmarks/micro_benchmark/and4/and4.v new file mode 100644 index 000000000..4b71607f6 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and4/and4.v @@ -0,0 +1,22 @@ +///////////////////////////////////////// +// Functionality: 4-input AND +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module and4( + a, + b, + c, + d, + e); + +input wire a; +input wire b; +input wire c; +input wire d; +output wire e; + +assign e = a & b & c & d; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v new file mode 100644 index 000000000..4a3542eec --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + reset, + result +); + + input clk; + input reset; + output [127:0] result; + + reg [127:0] result; + + always @(posedge clk or posedge reset) + begin + if (reset) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v new file mode 100644 index 000000000..4d11e9e0b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, reset; + wire [127:0] result; + + counter DUT( + .clk(clk), + .reset(reset), + .result(result) + ); + + initial begin + #0 reset = 1'b1; clk = 1'b0; + #100 reset = 1'b0; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v new file mode 100644 index 000000000..d5e8ce2a8 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + resetb, + result +); + + input clk; + input reset; + output [127:0] result; + + reg [127:0] result; + + always @(posedge clk or negedge resetb) + begin + if (~resetb) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v new file mode 100644 index 000000000..c96557b4e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, resetb; + wire [127:0] result; + + counter DUT( + .clk(clk), + .resetb(resetb), + .result(result) + ); + + initial begin + #0 reset = 1'b0; clk = 1'b0; + #100 reset = 1'b1; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v new file mode 100644 index 000000000..74a935e8d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 18-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_18(a, b, c, out); +parameter DATA_WIDTH = 18; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v new file mode 100644 index 000000000..f7be3eff9 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 20-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_20(a, b, c, out); +parameter DATA_WIDTH = 20; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v new file mode 100644 index 000000000..669bc4747 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 36-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_36(a, b, c, out); +parameter DATA_WIDTH = 4; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v new file mode 100644 index 000000000..05df02fac --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v @@ -0,0 +1,25 @@ +//------------------------------------------------------- +// Functionality: +// - A 8-bit multiply-acculumate circuit +// - A 9-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_8_9(a, b, c, out); +parameter DATA_WIDTH = 18; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out[8:0] = a[8:0] * b[8:0] + c[8:0]; +assign out[17:9] = a[17:9] * b[17:9] + c[17:9]; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v new file mode 100644 index 000000000..664df33f4 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 9-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_9(a, b, c, out); +parameter DATA_WIDTH = 9; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + From 9c24a739bebafa73a6decd967bfc8fc3d8af127e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Jun 2021 17:40:53 -0600 Subject: [PATCH 11/89] [Test] Added a MAC benchmark sweeping test --- .../mac_units/config/task.conf | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 openfpga_flow/tasks/benchmark_sweep/mac_units/config/task.conf diff --git a/openfpga_flow/tasks/benchmark_sweep/mac_units/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/mac_units/config/task.conf new file mode 100644 index 000000000..0fddaa91a --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/mac_units/config/task.conf @@ -0,0 +1,67 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 +# VPR parameters +# Use a fixed routing channel width to save runtime +vpr_route_chan_width=300 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v +bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v +bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v +bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_12/mac_12.v +bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v +bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v +bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v +bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_32/mac_32.v +bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +bench0_top = mac_2 +bench1_top = mac_4 +bench2_top = mac_6 +bench3_top = mac_8 +bench4_top = mac_8_9 +bench5_top = mac_9 +bench6_top = mac_12 +bench7_top = mac_16 +bench8_top = mac_18 +bench9_top = mac_20 +bench10_top = mac_32 +bench11_top = mac_36 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From 760570d8835fad8457966419398343db56fb9fca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Jun 2021 18:13:18 -0600 Subject: [PATCH 12/89] [Test] Update counter test case for cover most counter HDL design --- .../benchmark_sweep/counter/config/task.conf | 32 ++++++++++++------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index 9d5a92747..7cedf7d27 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -12,26 +12,36 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif +timeout_each_job = 5*60 +fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/benchmark_sweep/counter/config/pin_constraints.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v [SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + bench0_top = counter -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v -bench0_chan_width = 300 +bench1_top = counter +bench2_top = counter +bench3_top = counter [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= +#end_flow_with_test= #vpr_fpga_verilog_formal_verification_top_netlist= From 0b2d6eb14787cda9a92a2426ddec709ab6f8558f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Jun 2021 18:35:41 -0600 Subject: [PATCH 13/89] [Test] Add micro benchmark to a dedicated regression test --- .../micro_benchmark_reg_test.sh | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100755 openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh new file mode 100755 index 000000000..dc8e9ddc2 --- /dev/null +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -0,0 +1,12 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "Micro benchmark regression tests"; +# TODO: enable this when flow-run script support same top module name in one task configuration file +#run-task benchmark_sweep/counter --debug --show_thread_logs +run-task benchmark_sweep/mac_units --debug --show_thread_logs From 260b14c3d4bcbcb50b60fa0f4b925d9a4586b527 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Jun 2021 18:37:42 -0600 Subject: [PATCH 14/89] [CI] Add the micro benchmark regression test to CI --- .github/workflows/build.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 753b4c77f..77ccb1527 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -210,6 +210,7 @@ jobs: - name: fpga_bitstream_reg_test - name: fpga_sdc_reg_test - name: fpga_spice_reg_test + - name: micro_benchmark_reg_test - name: quicklogic_reg_test - name: vtr_benchmark_reg_test - name: iwls_benchmark_reg_test @@ -257,6 +258,7 @@ jobs: - name: fpga_bitstream_reg_test - name: fpga_sdc_reg_test - name: fpga_spice_reg_test + - name: micro_benchmark_reg_test - name: quicklogic_reg_test - name: vtr_benchmark_reg_test - name: iwls_benchmark_reg_test From fd580bb36f8b7ad5d326a86f269b14f5560d9c92 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Jun 2021 11:45:23 -0600 Subject: [PATCH 15/89] [Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name --- openfpga_flow/scripts/run_fpga_task.py | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 7855a54fd..0cb6612e1 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -302,6 +302,13 @@ def generate_each_task_actions(taskname): benchmark_list.append(CurrBenchPara) + # Count the number of duplicated top module name among benchmark + # This is required as flow run directory names for these benchmarks are different than others + # which are uniquified + benchmark_top_module_count = [] + for bench in benchmark_list: + benchmark_top_module_count.append(bench["top_module"]) + # Create OpenFPGA flow run commnad for each combination of # architecture, benchmark and parameters # Create run_job object [arch, bench, run_dir, commnad] @@ -309,7 +316,11 @@ def generate_each_task_actions(taskname): for indx, arch in enumerate(archfile_list): for bench in benchmark_list: for lbl, param in bench["script_params"].items(): - flow_run_dir = get_flow_rundir(arch, benchmark_list.index(bench), bench["top_module"], lbl) + if (benchmark_top_module_count.count(bench["top_module"]) > 1): + flow_run_dir = get_flow_rundir(arch, "bench" + str(benchmark_list.index(bench)) + "_" + bench["top_module"], lbl) + else: + flow_run_dir = get_flow_rundir(arch, bench["top_module"], lbl) + command = create_run_command( curr_job_dir=flow_run_dir, archfile=arch, @@ -332,10 +343,10 @@ def generate_each_task_actions(taskname): # Make the directory name unique by including the benchmark index in the list. # This is because benchmarks may share the same top module names -def get_flow_rundir(arch, bench_index, top_module, flow_params=None): +def get_flow_rundir(arch, top_module, flow_params=None): path = [ os.path.basename(arch).replace(".xml", ""), - "bench" + str(bench_index) + "_" + top_module, + top_module, flow_params if flow_params else "common" ] return os.path.abspath(os.path.join(*path)) From 0a0d10b36d220a977051ad9ee243b61f721ee4a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Jun 2021 16:18:46 -0600 Subject: [PATCH 16/89] [HDL] Bug fix in Verilog syntax --- .../micro_benchmark/counter_128bit_async_resetb/counter.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v index d5e8ce2a8..628ec4c08 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v @@ -10,7 +10,7 @@ module counter ( ); input clk; - input reset; + input resetb; output [127:0] result; reg [127:0] result; From f06017581c2e7d72b210327c4da9b22cf627417e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Jun 2021 16:33:50 -0600 Subject: [PATCH 17/89] [Test] Bug fix in counter micro benchmark tests --- .../benchmark_sweep/counter/config/task.conf | 24 ++++++++++++------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index 7cedf7d27..eb0079516 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -9,23 +9,29 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 5*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/benchmark_sweep/counter/config/pin_constraints.xml # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v -yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 +# VPR parameters +# # Use a fixed routing channel width to save runtime +vpr_route_chan_width=50 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v @@ -34,8 +40,8 @@ bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_12 bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v [SYNTHESIS_PARAM] -bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys -bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +#bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter bench1_top = counter From e34fbf8ecf8f7769fd650ab48e2200997a1a60e5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Jun 2021 16:36:04 -0600 Subject: [PATCH 18/89] [Test] Deploy MCNC big20 to the micro benchmark regression test --- .../regression_test_scripts/fpga_verilog_reg_test.sh | 6 ------ .../regression_test_scripts/micro_benchmark_reg_test.sh | 9 +++++++-- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 70137dd77..9c51ef6ea 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -136,9 +136,3 @@ run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs echo -e "Testing through channels in tileable routing"; run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs - -# Verify MCNC big20 benchmark suite with ModelSim -# Please make sure you have ModelSim installed in the environment -# Otherwise, it will fail -#run-task fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20 -#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index dc8e9ddc2..28b24aef3 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,6 +7,11 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -# TODO: enable this when flow-run script support same top module name in one task configuration file -#run-task benchmark_sweep/counter --debug --show_thread_logs +run-task benchmark_sweep/counter --debug --show_thread_logs run-task benchmark_sweep/mac_units --debug --show_thread_logs + +# Verify MCNC big20 benchmark suite with ModelSim +# Please make sure you have ModelSim installed in the environment +# Otherwise, it will fail +run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim From b2c30e3103a695749eb56fdce37f9d227ae2cf6c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Jun 2021 16:40:24 -0600 Subject: [PATCH 19/89] [Test] Bug fix in mcnc openfpga shell script --- .../mcnc_example_script.openfpga | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga index 56b5c9caf..7f2984f96 100644 --- a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose # Build fabric-dependent bitstream build_fabric_bitstream --verbose @@ -46,9 +46,7 @@ build_fabric_bitstream --verbose # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC \ --explicit_port_mapping \ - --include_timing \ - --include_signal_init -# --support_icarus_simulator + --include_timing # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -59,16 +57,6 @@ write_fabric_verilog --file ./SRC \ write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis - # Finish and exit OpenFPGA exit From 21d1519658cee4406f5a7a0cf208dfa51a7bb4e8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 16:56:28 -0600 Subject: [PATCH 20/89] [Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option --- .../fpga_verilog/verilog_auxiliary_netlists.cpp | 6 ------ openfpga/src/fpga_verilog/verilog_constants.h | 1 - .../verilog_preconfig_top_module.cpp | 16 ++++++++++------ .../src/fpga_verilog/verilog_testbench_utils.cpp | 3 --- 4 files changed, 10 insertions(+), 16 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index b0bacad37..85b403290 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -206,12 +206,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, /* Print the title */ print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); - /* To enable signal initialization */ - if (true == verilog_testbench_opts.include_signal_init()) { - print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1); - fp << std::endl; - } - /* To enable functional verfication with Icarus */ if (true == verilog_testbench_opts.support_icarus_simulator()) { print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1); diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index 0275a40a7..e9f2f5cd8 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -7,7 +7,6 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v"; constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation -constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 5b7264044..2e330fc93 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -507,12 +507,16 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, circuit_lib, sram_model, bitstream_manager); - /* Add signal initialization */ - print_verilog_testbench_signal_initialization(fp, - std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), - circuit_lib, - module_manager, - top_module); + /* Add signal initialization: + * Bypass writing codes to files due to the autogenerated codes are very large. + */ + if (true == options.include_signal_init()) { + print_verilog_testbench_signal_initialization(fp, + std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), + circuit_lib, + module_manager, + top_module); + } /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 994d6f280..dfb1b2468 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -911,7 +911,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, /* Add signal initialization Verilog codes */ fp << std::endl; - fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl; for (const CircuitModelId& signal_init_circuit_model : signal_init_circuit_models) { /* Find the module id corresponding to the circuit model from module graph */ ModuleId primitive_module = module_manager.find_module(circuit_lib.model_name(signal_init_circuit_model)); @@ -924,8 +923,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, module_manager, top_module, primitive_module); } - - fp << "`endif" << std::endl; } } /* end namespace openfpga */ From 779437cd37f5de7111e554c5f9e9d41d825fa10e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 17:07:15 -0600 Subject: [PATCH 21/89] [Doc] Update documentation to remove out-of-date options related to signal_init --- .../openfpga_commands/fpga_verilog_commands.rst | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 2a9af3b96..c41887484 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -24,14 +24,6 @@ write_fabric_verilog Output timing information to Verilog netlists for primitive modules - .. option:: --include_signal_init - - Output signal initialization to Verilog netlists for primitive modules - - .. option:: --support_icarus_simulator - - Output Verilog netlists with syntax that iVerilog simulatorcan accept - .. option:: --print_user_defined_template Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists @@ -118,6 +110,10 @@ write_preconfigured_fabric_wrapper Output Verilog netlists with syntax that iVerilog simulator can accept + .. option:: --include_signal_init + + Output signal initialization to Verilog testbench to smooth convergence in HDL simulation + .. option:: --verbose Show verbose log @@ -152,7 +148,6 @@ write_preconfigured_testbench Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. - .. option:: --support_icarus_simulator Output Verilog netlists with syntax that iVerilog simulator can accept From 5364d8104fb60d056062247da27dfb381976dbab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 17:07:41 -0600 Subject: [PATCH 22/89] [Tool] Add signal_init option to preconfigured fabric wrapper writer --- openfpga/src/base/openfpga_verilog.cpp | 2 ++ openfpga/src/base/openfpga_verilog_command.cpp | 3 +++ 2 files changed, 5 insertions(+) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 081466c06..3d853c18c 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -128,6 +128,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator"); + CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -139,6 +140,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator)); + options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); options.set_print_formal_verification_top_netlist(true); if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index a890d6971..d2410bff3 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -149,6 +149,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga: /* Add an option '--support_icarus_simulator' */ shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator"); + /* add an option '--include_signal_init' */ + shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches"); + /* add an option '--verbose' */ shell_cmd.add_option("verbose", false, "enable verbose output"); From 549657e1fbbaf3dcf07e338df92c5a9fc9b9a864 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 17:13:36 -0600 Subject: [PATCH 23/89] [Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base --- openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp | 6 ------ openfpga/src/fpga_verilog/verilog_constants.h | 1 - 2 files changed, 7 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index 85b403290..9701a9ace 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -212,12 +212,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, fp << std::endl; } - /* To enable manualy checked simulation */ - if (true == verilog_testbench_opts.print_top_testbench()) { - print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1); - fp << std::endl; - } - /* To enable auto-checked simulation */ if ( (true == verilog_testbench_opts.print_preconfig_top_testbench()) || (true == verilog_testbench_opts.print_top_testbench()) ) { diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index e9f2f5cd8..4a0ec4908 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -8,7 +8,6 @@ constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale ( constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation -constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification From 67dec810eb62dbd7374208fdb75770cb1d617e58 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Jun 2021 17:27:32 -0600 Subject: [PATCH 24/89] [Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes --- .../verilog_auxiliary_netlists.cpp | 6 ---- openfpga/src/fpga_verilog/verilog_constants.h | 4 --- .../verilog_preconfig_top_module.cpp | 30 +++++++++---------- 3 files changed, 14 insertions(+), 26 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index 9701a9ace..a3ac9c580 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -206,12 +206,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, /* Print the title */ print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); - /* To enable functional verfication with Icarus */ - if (true == verilog_testbench_opts.support_icarus_simulator()) { - print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1); - fp << std::endl; - } - /* To enable auto-checked simulation */ if ( (true == verilog_testbench_opts.print_preconfig_top_testbench()) || (true == verilog_testbench_opts.print_top_testbench()) ) { diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index 4a0ec4908..18e23b721 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -13,10 +13,6 @@ constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to ena constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms"; -// Icarus variables and flag -constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches -// End of Icarus variables and flag - constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v"; constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v"; constexpr char* VERILOG_TOP_POSTFIX = "_top.v"; diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 2e330fc93..e3675428d 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -364,7 +364,8 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, const ModuleId &top_module, const CircuitLibrary& circuit_lib, const CircuitModelId& mem_model, - const BitstreamManager &bitstream_manager) { + const BitstreamManager &bitstream_manager, + const bool& support_icarus_simulator) { /* Skip the datab port if there is only 1 output port in memory model * Currently, it assumes that the data output port is always defined while datab is optional @@ -379,21 +380,17 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); - print_verilog_preprocessing_flag(fp, std::string(ICARUS_SIMULATOR_FLAG)); - /* Use assign syntax for Icarus simulator */ - print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, - bitstream_manager, - output_datab_bits); - - fp << "`else" << std::endl; - - /* Use assign syntax for Icarus simulator */ - print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, - bitstream_manager, - output_datab_bits); - - print_verilog_endif(fp); + if (support_icarus_simulator) { + print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, + bitstream_manager, + output_datab_bits); + } else { + /* Use deposit syntax for other simulators */ + print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, + bitstream_manager, + output_datab_bits); + } print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); } @@ -505,7 +502,8 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, /* Assign FPGA internal SRAM/Memory ports to bitstream values */ print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, circuit_lib, sram_model, - bitstream_manager); + bitstream_manager, + options.support_icarus_simulator()); /* Add signal initialization: * Bypass writing codes to files due to the autogenerated codes are very large. From bcc16d732c9ff3ab17f89f838a372324971dd49e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 10:10:16 -0600 Subject: [PATCH 25/89] [Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches --- openfpga/src/base/openfpga_verilog.cpp | 23 +++++++++++ .../src/base/openfpga_verilog_command.cpp | 4 ++ openfpga/src/fpga_verilog/verilog_api.cpp | 1 + .../verilog_simulation_info_writer.cpp | 38 +++++++++++++++---- .../verilog_simulation_info_writer.h | 2 + 5 files changed, 60 insertions(+), 8 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 3d853c18c..c9ef08765 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -219,6 +219,7 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_file = cmd.option("file"); CommandOptionId opt_hdl_dir = cmd.option("hdl_dir"); CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); + CommandOptionId opt_tb_type = cmd.option("testbench_type"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -230,6 +231,28 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file)); + /* Identify testbench type */ + std::string full_tb_tag("full_testbench"); + std::string preconfig_tb_tag("preconfigured_testbench"); + if (true == cmd_context.option_enable(cmd, opt_tb_type)) { + if (std::string("preconfigured_testbench") == cmd_context.option_value(cmd, opt_tb_type)) { + options.set_print_preconfig_top_testbench(true); + } else if (std::string("full_testbench") == cmd_context.option_value(cmd, opt_tb_type)) { + options.set_print_preconfig_top_testbench(false); + options.set_print_top_testbench(true); + } else { + /* Invalid option, error out */ + VTR_LOG_ERROR("Invalid option value for testbench type: '%s'! Should be either '%s' or '%s'\n", + cmd_context.option_value(cmd, opt_tb_type).c_str(), + full_tb_tag.c_str(), + preconfig_tb_tag.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } else { + /* Deposit default type which is the preconfigured testbench */ + options.set_print_preconfig_top_testbench(true); + } + return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(), g_vpr_ctx.atom(), diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index d2410bff3..2d8846e35 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -243,6 +243,10 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell Date: Fri, 25 Jun 2021 10:16:48 -0600 Subject: [PATCH 26/89] [Doc] update documentation on the new option '--testbench_type' --- .../openfpga_commands/fpga_verilog_commands.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index c41887484..a1303941d 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -173,6 +173,10 @@ write_simulation_task_info Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + .. option:: --testbench_type + + Specify the type of testbenches [``preconfigured_testbench``|``full_testbench``]. By default, it is the ``preconfigured_testbench``. + .. option:: --verbose Show verbose log From 2bb514c51a9da0239ffe4e9f4fcb9b9eed016e0e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 10:33:29 -0600 Subject: [PATCH 27/89] [Tool] Support time unit in writing simulation information file --- openfpga/src/base/openfpga_verilog.cpp | 8 ++++++++ openfpga/src/base/openfpga_verilog_command.cpp | 4 ++++ .../verilog_simulation_info_writer.cpp | 14 +++++--------- .../src/fpga_verilog/verilog_testbench_options.cpp | 9 +++++++++ .../src/fpga_verilog/verilog_testbench_options.h | 3 +++ 5 files changed, 29 insertions(+), 9 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index c9ef08765..3821c407f 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -8,6 +8,9 @@ /* Headers from openfpgashell library */ #include "command_exit_codes.h" +/* Headers from openfpgautil library */ +#include "openfpga_scale.h" + #include "verilog_api.h" #include "openfpga_verilog.h" @@ -220,6 +223,7 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_hdl_dir = cmd.option("hdl_dir"); CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); CommandOptionId opt_tb_type = cmd.option("testbench_type"); + CommandOptionId opt_time_unit = cmd.option("time_unit"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -231,6 +235,10 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file)); + if (true == cmd_context.option_enable(cmd, opt_time_unit)) { + options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit))); + } + /* Identify testbench type */ std::string full_tb_tag("full_testbench"); std::string preconfig_tb_tag("preconfigured_testbench"); diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 2d8846e35..c78d69595 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -247,6 +247,10 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell units_map; - // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; - // units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15; /* Compute simulation time period: full testbench and pre-configured testbench has different length * Currently, we only support the two types. And one of them must be enabled when outputting this file */ float simulation_time_period = 0.; if (options.print_top_testbench()) { - simulation_time_period = find_simulation_time_period(1E-3, + simulation_time_period = find_simulation_time_period(options.time_unit(), num_program_clock_cycles, 1. / prog_clock_freq, num_operating_clock_cycles, 1. / op_clock_freq); } else { VTR_ASSERT(options.print_preconfig_top_testbench()); - /* Added 2 additional clock cycles due to reset/set cycles */ simulation_time_period = find_operating_phase_simulation_time(1., - num_operating_clock_cycles + 2, + num_operating_clock_cycles, 1. / op_clock_freq, - 1E-3); - + options.time_unit()); } /* Identify the testbench file name depending on the type */ @@ -96,7 +92,7 @@ void print_verilog_simulation_info(const std::string& ini_fname, ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name; ini["SIMULATION_DECK"]["TOP_TB"] = top_tb_name; ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period); - ini["SIMULATION_DECK"]["UNIT "] = "ms"; + ini["SIMULATION_DECK"]["UNIT "] = unit_to_string(options.time_unit()); ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX)); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp index cce9338cf..49d14dee6 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp @@ -24,6 +24,7 @@ VerilogTestbenchOption::VerilogTestbenchOption() { support_icarus_simulator_ = false; include_signal_init_ = false; default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; + time_unit_ = 1E-3; verbose_output_ = false; } @@ -82,6 +83,10 @@ e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const { return default_net_type_; } +float VerilogTestbenchOption::time_unit() const { + return time_unit_; +} + bool VerilogTestbenchOption::verbose_output() const { return verbose_output_; } @@ -160,6 +165,10 @@ void VerilogTestbenchOption::set_default_net_type(const std::string& default_net } } +void VerilogTestbenchOption::set_time_unit(const float& time_unit) { + time_unit_ = time_unit; +} + void VerilogTestbenchOption::set_verbose_output(const bool& enabled) { verbose_output_ = enabled; } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h index 6b46d8316..a68a44bd2 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h @@ -36,6 +36,7 @@ class VerilogTestbenchOption { bool include_signal_init() const; bool support_icarus_simulator() const; e_verilog_default_net_type default_net_type() const; + float time_unit() const; bool verbose_output() const; public: /* Public validator */ bool validate() const; @@ -61,6 +62,7 @@ class VerilogTestbenchOption { void set_include_signal_init(const bool& enabled); void set_support_icarus_simulator(const bool& enabled); void set_default_net_type(const std::string& default_net_type); + void set_time_unit(const float& time_unit); void set_verbose_output(const bool& enabled); private: /* Internal Data */ std::string output_directory_; @@ -76,6 +78,7 @@ class VerilogTestbenchOption { bool support_icarus_simulator_; bool include_signal_init_; e_verilog_default_net_type default_net_type_; + float time_unit_; bool verbose_output_; }; From 507f5ee54cf9a07212be60830164d3af296b4ffc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 10:34:43 -0600 Subject: [PATCH 28/89] [Doc] Update documentation about time unit support in writing simulation file --- .../openfpga_commands/fpga_verilog_commands.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index a1303941d..88cf33bc6 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -177,6 +177,10 @@ write_simulation_task_info Specify the type of testbenches [``preconfigured_testbench``|``full_testbench``]. By default, it is the ``preconfigured_testbench``. + .. option:: --time_unit + + Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``ms``). + .. option:: --verbose Show verbose log From 90163fab6c15d44638113fdfc08b16c2a34fb268 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 15:06:07 -0600 Subject: [PATCH 29/89] [Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream ' --- openfpga/src/base/openfpga_verilog.cpp | 9 +++--- .../src/base/openfpga_verilog_command.cpp | 8 ++--- .../verilog_preconfig_top_module.cpp | 9 +++--- .../verilog_testbench_options.cpp | 31 +++++++++++++------ .../fpga_verilog/verilog_testbench_options.h | 15 +++++++-- 5 files changed, 47 insertions(+), 25 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 3821c407f..fd21d47c3 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -79,6 +79,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); + CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -97,6 +98,10 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); } + if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) { + options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream)); + } + /* If pin constraints are enabled by command options, read the file */ PinConstraints pin_constraints; if (true == cmd_context.option_enable(cmd, opt_pcf)) { @@ -130,7 +135,6 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); - CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator"); CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); CommandOptionId opt_verbose = cmd.option("verbose"); @@ -142,7 +146,6 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist)); options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); - options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator)); options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); options.set_print_formal_verification_top_netlist(true); if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { @@ -178,7 +181,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); - CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_verbose = cmd.option("verbose"); @@ -190,7 +192,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist)); options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark)); - options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator)); options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_print_preconfig_top_testbench(true); diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index c78d69595..95c146e03 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -146,8 +146,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga: CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'"); shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING); - /* Add an option '--support_icarus_simulator' */ - shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator"); + /* Add an option '--embed_bitstream' */ + CommandOptionId embed_bitstream_opt = shell_cmd.add_option("embed_bitstream", false, "Embed bitstream to the Verilog wrapper netlist; This may cause a large netlist file size"); + shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING); /* add an option '--include_signal_init' */ shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches"); @@ -195,9 +196,6 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist"); shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); - /* Add an option '--support_icarus_simulator' */ - shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator"); - /* Add an option '--explicit_port_mapping' */ shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists"); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index e3675428d..02fbaa166 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -365,7 +365,7 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, const CircuitLibrary& circuit_lib, const CircuitModelId& mem_model, const BitstreamManager &bitstream_manager, - const bool& support_icarus_simulator) { + const e_embedded_bitstream_hdl_type& embedded_bitstream_hdl_type) { /* Skip the datab port if there is only 1 output port in memory model * Currently, it assumes that the data output port is always defined while datab is optional @@ -381,12 +381,13 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); /* Use assign syntax for Icarus simulator */ - if (support_icarus_simulator) { + if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) { print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, bitstream_manager, output_datab_bits); } else { /* Use deposit syntax for other simulators */ + VTR_ASSERT(EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type); print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, bitstream_manager, output_datab_bits); @@ -499,11 +500,11 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, CircuitModelId sram_model = config_protocol.memory_model(); VTR_ASSERT(true == circuit_lib.valid_model_id(sram_model)); - /* Assign FPGA internal SRAM/Memory ports to bitstream values */ + /* Assign FPGA internal SRAM/Memory ports to bitstream values, only output when needed */ print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, circuit_lib, sram_model, bitstream_manager, - options.support_icarus_simulator()); + options.embedded_bitstream_hdl_type()); /* Add signal initialization: * Bypass writing codes to files due to the autogenerated codes are very large. diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp index 49d14dee6..ca936bea7 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp @@ -21,9 +21,9 @@ VerilogTestbenchOption::VerilogTestbenchOption() { print_top_testbench_ = false; simulation_ini_path_.clear(); explicit_port_mapping_ = false; - support_icarus_simulator_ = false; include_signal_init_ = false; default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; + embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM; time_unit_ = 1E-3; verbose_output_ = false; } @@ -75,10 +75,6 @@ bool VerilogTestbenchOption::include_signal_init() const { return include_signal_init_; } -bool VerilogTestbenchOption::support_icarus_simulator() const { - return support_icarus_simulator_; -} - e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const { return default_net_type_; } @@ -87,6 +83,10 @@ float VerilogTestbenchOption::time_unit() const { return time_unit_; } +e_embedded_bitstream_hdl_type VerilogTestbenchOption::embedded_bitstream_hdl_type() const { + return embedded_bitstream_hdl_type_; +} + bool VerilogTestbenchOption::verbose_output() const { return verbose_output_; } @@ -147,10 +147,6 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) { include_signal_init_ = enabled; } -void VerilogTestbenchOption::set_support_icarus_simulator(const bool& enabled) { - support_icarus_simulator_ = enabled; -} - void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) { /* Decode from net type string */; if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) { @@ -165,6 +161,23 @@ void VerilogTestbenchOption::set_default_net_type(const std::string& default_net } } +void VerilogTestbenchOption::set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type) { + /* Decode from HDL type string */; + if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES])) { + embedded_bitstream_hdl_type_ = NUM_EMBEDDED_BITSTREAM_HDL_TYPES; + } else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG])) { + embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_IVERILOG; + } else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM])) { + embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM; + } else { + VTR_LOG_WARN("Invalid embedded bitstream type: '%s'! Expect ['%s'|'%s'|'%s']\n", + embedded_bitstream_hdl_type.c_str(), + EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES], + EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG], + EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM]); + } +} + void VerilogTestbenchOption::set_time_unit(const float& time_unit) { time_unit_ = time_unit; } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h index a68a44bd2..ad671386d 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h @@ -10,6 +10,15 @@ /* Begin namespace openfpga */ namespace openfpga { +/* Embedded bitstream code style */ +enum e_embedded_bitstream_hdl_type { + EMBEDDED_BITSTREAM_HDL_IVERILOG, + EMBEDDED_BITSTREAM_HDL_MODELSIM, + NUM_EMBEDDED_BITSTREAM_HDL_TYPES +}; + +constexpr std::array EMBEDDED_BITSTREAM_HDL_TYPE_STRING = {{"iverilog", "modelsim", "none"}}; //String versions of default net types + /******************************************************************** * Options for Verilog Testbench generator * Typicall usage: @@ -34,8 +43,8 @@ class VerilogTestbenchOption { std::string simulation_ini_path() const; bool explicit_port_mapping() const; bool include_signal_init() const; - bool support_icarus_simulator() const; e_verilog_default_net_type default_net_type() const; + e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const; float time_unit() const; bool verbose_output() const; public: /* Public validator */ @@ -60,9 +69,9 @@ class VerilogTestbenchOption { void set_print_simulation_ini(const std::string& simulation_ini_path); void set_explicit_port_mapping(const bool& enabled); void set_include_signal_init(const bool& enabled); - void set_support_icarus_simulator(const bool& enabled); void set_default_net_type(const std::string& default_net_type); void set_time_unit(const float& time_unit); + void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type); void set_verbose_output(const bool& enabled); private: /* Internal Data */ std::string output_directory_; @@ -75,9 +84,9 @@ class VerilogTestbenchOption { /* Print simulation ini is enabled only when the path is not empty */ std::string simulation_ini_path_; bool explicit_port_mapping_; - bool support_icarus_simulator_; bool include_signal_init_; e_verilog_default_net_type default_net_type_; + e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_; float time_unit_; bool verbose_output_; }; From 11d0283771c1889b17a478d781e868cb2a6eb11c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 15:11:12 -0600 Subject: [PATCH 30/89] [Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream' --- .../openfpga_commands/fpga_verilog_commands.rst | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 88cf33bc6..957eb6e63 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -106,9 +106,11 @@ write_preconfigured_fabric_wrapper Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. - .. option:: --support_icarus_simulator + .. option:: --embed_bitstream - Output Verilog netlists with syntax that iVerilog simulator can accept + Specify if the bitstream should be embedded to the Verilog netlists in HDL codes. Available options are ``none``, ``iverilog`` and ``modelsim``. Default value: ``modelsim``. + + .. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong! .. option:: --include_signal_init @@ -148,10 +150,6 @@ write_preconfigured_testbench Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. - .. option:: --support_icarus_simulator - - Output Verilog netlists with syntax that iVerilog simulator can accept - .. option:: --verbose Show verbose log From fae5e1dfdfb106d1e0d97112684fdd6de6eeb738 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 15:16:37 -0600 Subject: [PATCH 31/89] [Script] Upgrade openfpga shell script with the new option '--embed_bitstream' --- .../behavioral_verilog_example_script.openfpga | 4 ++-- .../bitstream_setting_example_script.openfpga | 4 ++-- .../configuration_chain_example_script.openfpga | 4 ++-- .../duplicated_grid_pin_example_script.openfpga | 4 ++-- .../openfpga_shell_scripts/example_script.openfpga | 4 ++-- .../example_without_ace_script.openfpga | 4 ++-- .../fix_device_example_script.openfpga | 4 ++-- ...e_clock_bitstream_setting_example_script.openfpga | 4 ++-- ..._device_global_tile_clock_example_script.openfpga | 4 ++-- ...x_device_route_chan_width_example_script.openfpga | 4 ++-- .../fix_heterogeneous_device_example_script.openfpga | 4 ++-- .../flatten_routing_example_script.openfpga | 4 ++-- .../generate_secure_fabric_example_script.openfpga | 4 ++-- ...te_secure_fabric_from_key_example_script.openfpga | 4 ++-- .../generate_testbench_example_script.openfpga | 4 ++-- .../global_tile_clock_example_script.openfpga | 4 ++-- .../global_tile_multiclock_example_script.openfpga | 4 ++-- .../implicit_verilog_example_script.openfpga | 4 ++-- .../iverilog_example_script.openfpga | 4 ++-- .../mcnc_example_script.openfpga | 4 ++-- .../openfpga_shell_scripts/rename_scripts.sh | 12 ++++++++++-- .../skywater_tapeout_example_script.openfpga | 4 ++-- .../verilog_default_net_type_example_script.openfpga | 4 ++-- 23 files changed, 54 insertions(+), 46 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga index cf614678e..be124317b 100644 --- a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga @@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga index 2d4820510..d0e0d69e2 100644 --- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga index 34e56c3b9..00944653e 100644 --- a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga @@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga index cf9cbd8b5..55c54adb7 100644 --- a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga @@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga index 71e6fd224..a31f81948 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga index 61c5ea8af..e614455cf 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga index 94a9a41c5..594d2e21b 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga index ea4f9912e..4a826bffe 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga @@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga index c40e79c79..1e1db546d 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga @@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index fe7679f65..7ca431e92 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga index 79430e976..9f2742315 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga index 4511ba34d..2fc56e4c7 100644 --- a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga index 571ceee8f..6efc2baa5 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga @@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga index 857b20981..4dd7f21c3 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga @@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index 19487e48b..b0322f105 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -52,8 +52,8 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga index bc56dc8ee..db51ffe15 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga @@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga index 5fe8cd4b5..ff0ba8d81 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga @@ -62,8 +62,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga index 9a32a86eb..31296021f 100644 --- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga index d44e57a24..1741f3011 100644 --- a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga index 7f2984f96..78daebb4b 100644 --- a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga @@ -54,8 +54,8 @@ write_fabric_verilog --file ./SRC \ # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh index 6b568e5d8..c222fa6d5 100644 --- a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh +++ b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh @@ -1,4 +1,12 @@ foreach i (*.openfpga) - sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i - sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i +# sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i +# sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i +end + +foreach i (*.openfpga) + sed -i 's/--support_icarus_simulator//g' $i +end + +foreach i (*.openfpga) + sed -i 's/write_preconfigured_fabric_wrapper/write_preconfigured_fabric_wrapper --embed_bitstream iverilog/g' $i end diff --git a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga index 7cfe311f3..7dd793dbe 100644 --- a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga index fab25be5a..3dc4da3da 100644 --- a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} # Write the SDC files for PnR backend # - Turn on every options here From 991062e9bfe35bcacc458709101465e735ff8dac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 15:22:42 -0600 Subject: [PATCH 32/89] [Tool] Bug fix --- openfpga/src/base/openfpga_verilog.cpp | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index fd21d47c3..b912c518c 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -79,7 +79,6 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); - CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -98,10 +97,6 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); } - if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) { - options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream)); - } - /* If pin constraints are enabled by command options, read the file */ PinConstraints pin_constraints; if (true == cmd_context.option_enable(cmd, opt_pcf)) { @@ -136,6 +131,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); + CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -148,10 +144,15 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); options.set_print_formal_verification_top_netlist(true); + if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); } + if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) { + options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream)); + } + /* If pin constraints are enabled by command options, read the file */ PinConstraints pin_constraints; if (true == cmd_context.option_enable(cmd, opt_pcf)) { From 30027b8c15dbd6e2af027ea87194442522fad725 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 15:27:15 -0600 Subject: [PATCH 33/89] [Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init' --- docs/source/manual/fpga_verilog/testbench.rst | 16 ---------------- .../openfpga_commands/fpga_verilog_commands.rst | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index 3f41f1a1d..addf4496f 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -87,23 +87,7 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n - ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command. .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled! - - - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command. - - .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. - - .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable. - - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command. - - .. warning:: Please disable this flag if you are not using icarus iVerilog simulator. - -__ iverilog_website_ - -.. _iverilog_website: http://iverilog.icarus.com/ - - - .. option:: _autocheck_top_tb.v This is the netlist for full testbench. diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 957eb6e63..d8e254a3e 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -76,6 +76,11 @@ write_full_testbench Output signal initialization to Verilog testbench to smooth convergence in HDL simulation + .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. + + .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable. + + .. option:: --verbose Show verbose log @@ -112,10 +117,20 @@ write_preconfigured_fabric_wrapper .. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong! + .. warning:: Please specify ``iverilog`` if you are using icarus iVerilog simulator. + +__ iverilog_website_ + +.. _iverilog_website: http://iverilog.icarus.com/ + .. option:: --include_signal_init Output signal initialization to Verilog testbench to smooth convergence in HDL simulation + .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. + + .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable. + .. option:: --verbose Show verbose log From 87446a14c365cbb62abf368873b867b2de6d06be Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Jun 2021 19:45:06 -0600 Subject: [PATCH 34/89] [Tool] Bug fix for the option ``--embed_bitstream none`` --- openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 02fbaa166..44f863cb8 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -385,9 +385,8 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, bitstream_manager, output_datab_bits); - } else { - /* Use deposit syntax for other simulators */ - VTR_ASSERT(EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type); + /* Use deposit syntax for other simulators */ + } else if (EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type) { print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, bitstream_manager, output_datab_bits); From 4a623bec79415da736fe2cad231ba1587a1b04bc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Jun 2021 19:55:40 -0600 Subject: [PATCH 35/89] [Script] Add example openfpga shell script to generate preconfigured fabric wrapper --- .../preconfig_fabric_example_script.openfpga | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga new file mode 100644 index 000000000..f07f5e2a5 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga @@ -0,0 +1,57 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream ${OPENFPGA_EMBEDDED_BITSTREAM_HDL_TYPE} --file ./SRC --explicit_port_mapping + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 6f0600e17f4358c3d798bb8d9d078db4b98e42d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Jun 2021 19:56:01 -0600 Subject: [PATCH 36/89] [Test] Added two test cases for generating preconfigured fabric wrapper in different styles --- .../embed_bitstream_modelsim/config/task.conf | 35 +++++++++++++++++++ .../embed_bitstream_none/config/task.conf | 35 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim/config/task.conf create mode 100644 openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_none/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim/config/task.conf new file mode 100644 index 000000000..9b755a5c7 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_embedded_bitstream_hdl_type=modelsim + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_none/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_none/config/task.conf new file mode 100644 index 000000000..c93d2fed8 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_none/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_embedded_bitstream_hdl_type=none + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From b4c587f10b083b4f430abb63b6624ae7c6d8e221 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Jun 2021 19:58:15 -0600 Subject: [PATCH 37/89] [Test] Added the new test cases to regression tests --- .../regression_test_scripts/fpga_verilog_reg_test.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 9c51ef6ea..044821b3e 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -136,3 +136,7 @@ run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs echo -e "Testing through channels in tileable routing"; run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs + +echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators"; +run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs From dfe1db996a7c1d48017a17539fbc093ca4034d8a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 09:56:04 -0600 Subject: [PATCH 38/89] [Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 4 +--- openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp | 3 +-- openfpga/src/utils/simulation_utils.cpp | 5 ++--- openfpga/src/utils/simulation_utils.h | 3 +-- 4 files changed, 5 insertions(+), 10 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index ffc15437b..b4b9045fb 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -41,7 +41,6 @@ constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT"; constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT"; constexpr char* ERROR_COUNTER = "nb_error"; constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start"; -constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; /******************************************************************** * Print the module ports for the Verilog testbench @@ -354,8 +353,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, clock_port_names, std::string(DEFAULT_CLOCK_NAME)); - float simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME, - simulation_parameters.num_clock_cycles(), + float simulation_time = find_operating_phase_simulation_time(simulation_parameters.num_clock_cycles(), 1./simulation_parameters.default_operating_clock_frequency(), VERILOG_SIM_TIMESCALE); diff --git a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp index 05477f30c..f80cce0a8 100644 --- a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp @@ -72,8 +72,7 @@ void print_verilog_simulation_info(const std::string& ini_fname, 1. / op_clock_freq); } else { VTR_ASSERT(options.print_preconfig_top_testbench()); - simulation_time_period = find_operating_phase_simulation_time(1., - num_operating_clock_cycles, + simulation_time_period = find_operating_phase_simulation_time(num_operating_clock_cycles, 1. / op_clock_freq, options.time_unit()); } diff --git a/openfpga/src/utils/simulation_utils.cpp b/openfpga/src/utils/simulation_utils.cpp index 87a04976d..df56bf91b 100644 --- a/openfpga/src/utils/simulation_utils.cpp +++ b/openfpga/src/utils/simulation_utils.cpp @@ -14,14 +14,13 @@ namespace openfpga { /******************************************************************** * Compute the time period for the simulation *******************************************************************/ -float find_operating_phase_simulation_time(const int& factor, - const int& num_op_clock_cycles, +float find_operating_phase_simulation_time(const int& num_op_clock_cycles, const float& op_clock_period, const float& timescale) { /* Take into account the prog_reset and reset cycles * 1e9 is to change the unit to ns rather than second */ - return ((float)factor * (float)num_op_clock_cycles * op_clock_period) / timescale; + return ((float)num_op_clock_cycles * op_clock_period) / timescale; } /******************************************************************** diff --git a/openfpga/src/utils/simulation_utils.h b/openfpga/src/utils/simulation_utils.h index c82999bc9..3d5e6bba2 100644 --- a/openfpga/src/utils/simulation_utils.h +++ b/openfpga/src/utils/simulation_utils.h @@ -12,8 +12,7 @@ /* begin namespace openfpga */ namespace openfpga { -float find_operating_phase_simulation_time(const int& factor, - const int& num_op_clock_cycles, +float find_operating_phase_simulation_time(const int& num_op_clock_cycles, const float& op_clock_period, const float& timescale); From 75a12e55de609550b47274e0434c1f8e4e2d7234 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 11:40:22 -0600 Subject: [PATCH 39/89] [HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes --- .../openfpga_cell_library/verilog/dff.v | 94 ++++--------------- 1 file changed, 18 insertions(+), 76 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index a1d3e2407..c3a5e538e 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -20,12 +20,7 @@ always @ (posedge CK) begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; -`else - assign Q = 1'bZ; -`endif +assign Q = q_reg; endmodule //End Of Module @@ -46,14 +41,8 @@ always @ (posedge CK) begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -79,12 +68,7 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; -`else - assign Q = 1'bZ; -`endif +assign Q = q_reg; endmodule //End Of Module @@ -111,14 +95,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -144,14 +122,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -178,14 +150,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -211,14 +177,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -249,14 +209,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -349,14 +303,8 @@ end else begin q_reg <= D; end -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q - assign Q = q_reg; - assign QN = !Q; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = !Q; endmodule //End Of Module @@ -462,13 +410,7 @@ end assign CFGQ = CFGE ? Q : 1'b0; assign CFGQN = CFGE ? QN : 1'b1; -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q - assign Q = q_reg; - assign QN = !Q; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = !Q; endmodule //End Of Module From a3208b332b30a28f68815b09e0e215c2af6ac1c4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 11:50:53 -0600 Subject: [PATCH 40/89] [Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL --- .../verilog_preconfig_top_module.cpp | 48 ++++++------------- 1 file changed, 14 insertions(+), 34 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 44f863cb8..4c7a8d2bf 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -204,16 +204,18 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, * while uses 'force' syntax to impost the bitstream at mem_inv port *******************************************************************/ static -void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp, - const ModuleManager &module_manager, - const ModuleId &top_module, - const BitstreamManager &bitstream_manager, - const bool& output_datab_bits) { +void print_verilog_preconfig_top_module_force_bitstream(std::fstream &fp, + const ModuleManager &module_manager, + const ModuleId &top_module, + const BitstreamManager &bitstream_manager, + const bool& output_datab_bits) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----")); + fp << "initial begin" << std::endl; + for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) { /* We only cares blocks with configuration bits */ if (0 == bitstream_manager.block_bits(config_block_id).size()) { @@ -242,31 +244,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp, for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { config_data_values.push_back(bitstream_manager.bit_value(config_bit)); } - print_verilog_wire_constant_values(fp, config_data_port, config_data_values); - } - - if (true == output_datab_bits) { - fp << "initial begin" << std::endl; - - for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) { - /* We only cares blocks with configuration bits */ - if (0 == bitstream_manager.block_bits(config_block_id).size()) { - continue; - } - /* Build the hierarchical path of the configuration bit in modules */ - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); - /* Drop the first block, which is the top module, it should be replaced by the instance name here */ - /* Ensure that this is the module we want to drop! */ - VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); - block_hierarchy.erase(block_hierarchy.begin()); - /* Build the full hierarchy path */ - std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME); - for (const ConfigBlockId &temp_block : block_hierarchy) { - bit_hierarchy_path += std::string("."); - bit_hierarchy_path += bitstream_manager.block_name(temp_block); - } - bit_hierarchy_path += std::string("."); + print_verilog_force_wire_constant_values(fp, config_data_port, config_data_values); + if (true == output_datab_bits) { /* Find the bit index in the parent block */ BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(), bitstream_manager.block_bits(config_block_id).size()); @@ -277,10 +257,10 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp, } print_verilog_force_wire_constant_values(fp, config_datab_port, config_datab_values); } - - fp << "end" << std::endl; } + fp << "end" << std::endl; + print_verilog_comment(fp, std::string("----- End assign bitstream to configuration memories -----")); } @@ -382,9 +362,9 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, /* Use assign syntax for Icarus simulator */ if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) { - print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, - bitstream_manager, - output_datab_bits); + print_verilog_preconfig_top_module_force_bitstream(fp, module_manager, top_module, + bitstream_manager, + output_datab_bits); /* Use deposit syntax for other simulators */ } else if (EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type) { print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, From 77dddaeb398ad67397e166a85d9e15b69035cf52 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 14:26:33 -0600 Subject: [PATCH 41/89] [Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions --- openfpga/src/fpga_verilog/verilog_api.cpp | 16 ++-- .../verilog_auxiliary_netlists.cpp | 92 ++++++++++++------- .../fpga_verilog/verilog_auxiliary_netlists.h | 13 ++- openfpga/src/fpga_verilog/verilog_constants.h | 2 - .../verilog_preconfig_top_module.cpp | 3 +- .../fpga_verilog/verilog_testbench_utils.cpp | 34 ++++--- .../fpga_verilog/verilog_testbench_utils.h | 3 +- .../fpga_verilog/verilog_top_testbench.cpp | 3 +- 8 files changed, 96 insertions(+), 70 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index df9cf46fc..a63132e36 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -192,10 +192,10 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager, options); /* Generate a Verilog file including all the netlists that have been generated */ - print_verilog_testbench_include_netlists(src_dir_path, - netlist_name, - options.fabric_netlist_file_path(), - options.reference_benchmark_file_path()); + print_verilog_full_testbench_include_netlists(src_dir_path, + netlist_name, + options.fabric_netlist_file_path(), + options.reference_benchmark_file_path()); return status; } @@ -286,10 +286,10 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager, options); /* Generate a Verilog file including all the netlists that have been generated */ - print_verilog_testbench_include_netlists(src_dir_path, - netlist_name, - options.fabric_netlist_file_path(), - options.reference_benchmark_file_path()); + print_verilog_preconfigured_testbench_include_netlists(src_dir_path, + netlist_name, + options.fabric_netlist_file_path(), + options.reference_benchmark_file_path()); return status; } diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index a3ac9c580..bd0d55114 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -90,14 +90,14 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager, /******************************************************************** * Print a file that includes all the netlists - * including the fabric netlists and testbenches + * including the fabric netlists and full testbenches * that have been generated and user-defined. * Some netlists are open to compile under specific preprocessing flags *******************************************************************/ -void print_verilog_testbench_include_netlists(const std::string& src_dir, - const std::string& circuit_name, - const std::string& fabric_netlist_file, - const std::string& reference_benchmark_file) { +void print_verilog_full_testbench_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& fabric_netlist_file, + const std::string& reference_benchmark_file) { std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX); /* Create the file stream */ @@ -132,28 +132,62 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir, print_verilog_endif(fp); fp << std::endl; - /* Include formal verification netlists only when formal verification flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG)); + /* Include top-level testbench only when auto-check flag is enabled */ + print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX)); + + /* Close the file stream */ + fp.close(); +} + +/******************************************************************** + * Print a file that includes all the netlists + * including the fabric netlists and preconfigured testbenches + * that have been generated and user-defined. + * Some netlists are open to compile under specific preprocessing flags + *******************************************************************/ +void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& fabric_netlist_file, + const std::string& reference_benchmark_file) { + std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_stream(verilog_fname.c_str(), fp); + + /* Print the title */ + print_verilog_file_header(fp, std::string("Netlist Summary")); + + /* Print preprocessing flags */ + print_verilog_comment(fp, std::string("------ Include simulation defines -----")); + print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)); + fp << std::endl; + + /* Include FPGA top module */ + print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----")); + if (true == fabric_netlist_file.empty()) { + print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME)); + } else { + VTR_ASSERT_SAFE(false == fabric_netlist_file.empty()); + print_verilog_include_netlist(fp, fabric_netlist_file); + } + fp << std::endl; + + /* Include reference benchmark netlist only when auto-check flag is enabled */ + print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); fp << "\t"; - print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX)); - - /* Include formal verification testbench only when formal simulation flag is enabled */ - fp << "\t"; - print_verilog_preprocessing_flag(fp, std::string(FORMAL_SIMULATION_FLAG)); - fp << "\t\t"; - print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX)); - fp << "\t"; - print_verilog_endif(fp); - + print_verilog_include_netlist(fp, std::string(reference_benchmark_file)); print_verilog_endif(fp); fp << std::endl; - /* Include top-level testbench only when auto-check flag is enabled */ - print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); - fp << "\t"; - print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX)); - print_verilog_endif(fp); - fp << std::endl; + /* Include formal verification netlists */ + print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX)); + + /* Include formal verification testbench */ + print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX)); /* Close the file stream */ fp.close(); @@ -213,18 +247,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, fp << std::endl; } - /* To enable pre-configured FPGA simulation */ - if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) { - print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1); - fp << std::endl; - } - - /* To enable pre-configured FPGA simulation */ - if (true == verilog_testbench_opts.print_preconfig_top_testbench()) { - print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1); - fp << std::endl; - } - /* Close the file stream */ fp.close(); } diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h index 0fdf2338b..e206a478b 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h @@ -21,10 +21,15 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager, const std::string& src_dir, const CircuitLibrary& circuit_lib); -void print_verilog_testbench_include_netlists(const std::string& src_dir, - const std::string& circuit_name, - const std::string& fabric_netlist_file, - const std::string& reference_benchmark_file); +void print_verilog_full_testbench_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& fabric_netlist_file, + const std::string& reference_benchmark_file); + +void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& fabric_netlist_file, + const std::string& reference_benchmark_file); void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, const FabricVerilogOption& fabric_verilog_opts); diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index 18e23b721..aea360206 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -7,9 +7,7 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v"; constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation -constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification -constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms"; diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 4c7a8d2bf..e797151a8 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -493,7 +493,8 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), circuit_lib, module_manager, - top_module); + top_module, + false); } /* Testbench ends*/ diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index dfb1b2468..cbebc5545 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -791,7 +791,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst const std::vector& circuit_input_ports, const ModuleManager& module_manager, const ModuleId& parent_module, - const ModuleId& primitive_module) { + const ModuleId& primitive_module, + const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -819,7 +820,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst child_hie_path, circuit_lib, circuit_model, circuit_input_ports, module_manager, child_module, - primitive_module); + primitive_module, + deposit_random_values); } else { /* If the child module is the primitive module, * we output the signal initialization codes for the input ports @@ -828,7 +830,6 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----")); fp << "\tinitial begin" << std::endl; - fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl; for (const auto& input_port : circuit_input_ports) { /* Only for formal verification: deposite a zero signal values */ @@ -838,22 +839,17 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst fp << "\t\t$deposit("; fp << child_hie_path << "."; fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false); - fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0'); - fp << ");" << std::endl; - } - fp << "\t`else" << std::endl; + + if (!deposit_random_values) { - /* Regular case: deposite initial signal values: a random value */ - for (const auto& input_port : circuit_input_ports) { - BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - input_port_info.set_origin_port_width(input_port_info.get_width()); - fp << "\t\t$deposit("; - fp << child_hie_path << "."; - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false); - fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl; + fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0'); + fp << ");" << std::endl; + } else { + VTR_ASSERT_SAFE(deposit_random_values); + fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl; + } } - fp << "\t`endif\n" << std::endl; fp << "\tend" << std::endl; print_verilog_comment(fp, std::string("------ END driver initialization -----")); } @@ -871,7 +867,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, const std::string& top_instance_name, const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, - const ModuleId& top_module) { + const ModuleId& top_module, + const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -921,7 +918,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, top_instance_name, circuit_lib, signal_init_circuit_model, signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, top_module, - primitive_module); + primitive_module, + deposit_random_values); } } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 1f9567481..91ade1856 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -101,7 +101,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, const std::string& top_instance_name, const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, - const ModuleId& top_module); + const ModuleId& top_module, + const bool& deposit_random_values); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index aecf72d6f..e5bdbcf01 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -2029,7 +2029,8 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME), circuit_lib, module_manager, - top_module); + top_module, + true); } From 7ac7de789e9b31d9e91784aa37210fa7bfc70671 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 15:26:40 -0600 Subject: [PATCH 42/89] [Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes --- openfpga/src/base/openfpga_verilog.cpp | 4 + .../src/base/openfpga_verilog_command.cpp | 6 ++ openfpga/src/fpga_verilog/verilog_api.cpp | 14 +--- .../verilog_auxiliary_netlists.cpp | 67 ++++------------ .../fpga_verilog/verilog_auxiliary_netlists.h | 9 +-- openfpga/src/fpga_verilog/verilog_constants.h | 3 - .../verilog_formal_random_top_testbench.cpp | 60 +++++++-------- .../verilog_simulation_info_writer.cpp | 2 +- .../verilog_testbench_options.cpp | 8 ++ .../fpga_verilog/verilog_testbench_options.h | 3 + .../fpga_verilog/verilog_testbench_utils.cpp | 24 ++---- .../fpga_verilog/verilog_testbench_utils.h | 3 +- .../fpga_verilog/verilog_top_testbench.cpp | 77 ++++++++----------- 13 files changed, 113 insertions(+), 167 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index b912c518c..16016a913 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -78,6 +78,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_fast_configuration = cmd.option("fast_configuration"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); + CommandOptionId opt_no_self_checking = cmd.option("no_self_checking"); CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); CommandOptionId opt_verbose = cmd.option("verbose"); @@ -93,6 +94,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_print_top_testbench(true); options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); + options.set_no_self_checking(cmd_context.option_enable(cmd, opt_no_self_checking)); if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); } @@ -184,6 +186,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); + CommandOptionId opt_no_self_checking = cmd.option("no_self_checking"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -196,6 +199,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_print_preconfig_top_testbench(true); + options.set_no_self_checking(cmd_context.option_enable(cmd, opt_no_self_checking)); if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); } diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 95c146e03..3b0c94138 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -97,6 +97,9 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell& clock_port_names, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const e_verilog_default_net_type& default_net_type) { + const VerilogTestbenchOption& options) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_default_net_type_declaration(fp, - default_net_type); + options.default_net_type()); /* Print the declaration for the module */ fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl; @@ -84,16 +84,17 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp, std::string(BENCHMARK_PORT_POSTFIX), std::string(FPGA_PORT_POSTFIX), std::string(CHECKFLAG_PORT_POSTFIX), - std::string(AUTOCHECKED_SIMULATION_FLAG)); + options.no_self_checking()); /* Instantiate an integer to count the number of error * and determine if the simulation succeed or failed */ - print_verilog_comment(fp, std::string("----- Error counter -------")); - fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; + if (!options.no_self_checking()) { + print_verilog_comment(fp, std::string("----- Error counter -------")); + fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl; + /* Add an empty line as splitter */ + fp << std::endl; + } } /******************************************************************** @@ -108,9 +109,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, /* Validate the file stream */ valid_file_stream(fp); - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); - + /* Instanciate benchmark */ print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); /* Do NOT use explicit port mapping here: @@ -132,12 +131,6 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, /* Add an empty line as splitter */ fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; } /******************************************************************** @@ -300,7 +293,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); /* Start of testbench */ - print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options.default_net_type()); + print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options); /* Call defined top-level module */ print_verilog_random_testbench_fpga_instance(fp, circuit_name, @@ -308,9 +301,11 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, options.explicit_port_mapping()); /* Call defined benchmark */ - print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, - atom_ctx, netlist_annotation, - options.explicit_port_mapping()); + if (!options.no_self_checking()) { + print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, + atom_ctx, netlist_annotation, + options.explicit_port_mapping()); + } /* Find clock port to be used */ std::vector clock_ports = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); @@ -341,17 +336,18 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, std::string(CHECKFLAG_PORT_POSTFIX), clock_ports); - print_verilog_testbench_check(fp, - std::string(AUTOCHECKED_SIMULATION_FLAG), - std::string(FORMAL_TB_SIM_START_PORT_NAME), - std::string(BENCHMARK_PORT_POSTFIX), - std::string(FPGA_PORT_POSTFIX), - std::string(CHECKFLAG_PORT_POSTFIX), - std::string(ERROR_COUNTER), - atom_ctx, - netlist_annotation, - clock_port_names, - std::string(DEFAULT_CLOCK_NAME)); + if (!options.no_self_checking()) { + print_verilog_testbench_check(fp, + std::string(FORMAL_TB_SIM_START_PORT_NAME), + std::string(BENCHMARK_PORT_POSTFIX), + std::string(FPGA_PORT_POSTFIX), + std::string(CHECKFLAG_PORT_POSTFIX), + std::string(ERROR_COUNTER), + atom_ctx, + netlist_annotation, + clock_port_names, + std::string(DEFAULT_CLOCK_NAME)); + } float simulation_time = find_operating_phase_simulation_time(simulation_parameters.num_clock_cycles(), 1./simulation_parameters.default_operating_clock_frequency(), diff --git a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp index f80cce0a8..9ed82a131 100644 --- a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp @@ -93,7 +93,7 @@ void print_verilog_simulation_info(const std::string& ini_fname, ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period); ini["SIMULATION_DECK"]["UNIT "] = unit_to_string(options.time_unit()); ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); - ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME); + ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX)); ini["SIMULATION_DECK"]["CONFIG_PROTOCOL"] = std::string(CONFIG_PROTOCOL_TYPE_STRING[config_protocol_type]); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp index ca936bea7..616081ad2 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp @@ -75,6 +75,10 @@ bool VerilogTestbenchOption::include_signal_init() const { return include_signal_init_; } +bool VerilogTestbenchOption::no_self_checking() const { + return no_self_checking_; +} + e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const { return default_net_type_; } @@ -147,6 +151,10 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) { include_signal_init_ = enabled; } +void VerilogTestbenchOption::set_no_self_checking(const bool& enabled) { + no_self_checking_ = enabled; +} + void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) { /* Decode from net type string */; if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) { diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h index ad671386d..1cee764c3 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h @@ -43,6 +43,7 @@ class VerilogTestbenchOption { std::string simulation_ini_path() const; bool explicit_port_mapping() const; bool include_signal_init() const; + bool no_self_checking() const; e_verilog_default_net_type default_net_type() const; e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const; float time_unit() const; @@ -69,6 +70,7 @@ class VerilogTestbenchOption { void set_print_simulation_ini(const std::string& simulation_ini_path); void set_explicit_port_mapping(const bool& enabled); void set_include_signal_init(const bool& enabled); + void set_no_self_checking(const bool& enabled); void set_default_net_type(const std::string& default_net_type); void set_time_unit(const float& time_unit); void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type); @@ -85,6 +87,7 @@ class VerilogTestbenchOption { std::string simulation_ini_path_; bool explicit_port_mapping_; bool include_signal_init_; + bool no_self_checking_; e_verilog_default_net_type default_net_type_; e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_; float time_unit_; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index cbebc5545..4422c836c 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -366,7 +366,6 @@ std::vector generate_verilog_testbench_clock_port(const std::vector clock_ports = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); @@ -460,9 +457,6 @@ void print_verilog_testbench_check(std::fstream& fp, fp << std::endl; } - /* Condition ends */ - print_verilog_endif(fp); - /* Add an empty line as splitter */ fp << std::endl; } @@ -664,7 +658,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, const std::string& benchmark_output_port_postfix, const std::string& fpga_output_port_postfix, const std::string& check_flag_port_postfix, - const std::string& autocheck_preprocessing_flag) { + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); @@ -718,11 +712,9 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, /* Add an empty line as splitter */ fp << std::endl; - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(autocheck_preprocessing_flag)); - - /* Add an empty line as splitter */ - fp << std::endl; + if (no_self_checking) { + return; + } /* Instantiate wire for benchmark output */ print_verilog_comment(fp, std::string("----- Benchmark outputs -------")); @@ -767,12 +759,6 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, /* Add an empty line as splitter */ fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; } /******************************************************************** diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 91ade1856..7b6858ce5 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -62,7 +62,6 @@ std::vector generate_verilog_testbench_clock_port(const std::vector(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1))); - /* Add output autocheck */ - print_verilog_testbench_check(fp, - std::string(AUTOCHECKED_SIMULATION_FLAG), - std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), - std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), - std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), - std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - std::string(TOP_TESTBENCH_ERROR_COUNTER), - atom_ctx, - netlist_annotation, - clock_port_names, - std::string(TOP_TB_OP_CLOCK_PORT_NAME)); + if (!options.no_self_checking()) { + /* Add output autocheck */ + print_verilog_testbench_check(fp, + std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), + std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), + std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), + std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), + std::string(TOP_TESTBENCH_ERROR_COUNTER), + atom_ctx, + netlist_annotation, + clock_port_names, + std::string(TOP_TB_OP_CLOCK_PORT_NAME)); - /* Add autocheck for configuration phase */ - print_verilog_top_testbench_check(fp, - std::string(AUTOCHECKED_SIMULATION_FLAG), - std::string(TOP_TB_CONFIG_DONE_PORT_NAME), - std::string(TOP_TESTBENCH_ERROR_COUNTER)); + /* Add autocheck for configuration phase */ + print_verilog_top_testbench_check(fp, + std::string(TOP_TB_CONFIG_DONE_PORT_NAME), + std::string(TOP_TESTBENCH_ERROR_COUNTER)); + } /* Find simulation time */ float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE, From ac9046b7d20c560c9a8b9ab5e47f06f7e360497e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 15:38:35 -0600 Subject: [PATCH 43/89] [Doc] Remove ``define_simulation.v`` since it is no longer needed. --- .../figures/verilog_testbench_hierarchy.png | Bin 32203 -> 0 bytes .../figures/verilog_testbench_hierarchy.svg | 79 ++++++++++++++++++ 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The FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag. - - .. note:: OpenFPGA always enable the self-testing feature. Users can disable it by commenting out the associated line in the ``define_simulation.v``. - - - ```define ENABLE_FORMAL_VERFICATION`` When enabled, the ``_include_netlist.v`` will include the pre-configured FPGA netlist for formal verification usage. This flag is added when ``--print_formal_verification_top_netlist`` option is enabled when calling the ``write_verilog_testbench`` command. - - - ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command. - - .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled! - .. option:: _autocheck_top_tb.v This is the netlist for full testbench. diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index d8e254a3e..e927d7b2c 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -51,7 +51,9 @@ write_full_testbench .. option:: --reference_benchmark_file_path - Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + + .. note:: If not specified, the testbench will not include any self-checking feature! .. option:: --pin_constraints_file or -pcf @@ -150,7 +152,9 @@ write_preconfigured_testbench .. option:: --reference_benchmark_file_path - Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + + .. note:: If not specified, the testbench will not include any self-checking feature! .. option:: --pin_constraints_file or -pcf From 6a260cadbfafe21f42caa06d4de61cb31f1e3223 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 15:42:23 -0600 Subject: [PATCH 44/89] [Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose --- openfpga/src/base/openfpga_verilog.cpp | 4 ---- openfpga/src/base/openfpga_verilog_command.cpp | 7 ++----- openfpga/src/fpga_verilog/verilog_testbench_options.cpp | 6 +----- openfpga/src/fpga_verilog/verilog_testbench_options.h | 2 -- 4 files changed, 3 insertions(+), 16 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 16016a913..b912c518c 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -78,7 +78,6 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_fast_configuration = cmd.option("fast_configuration"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); - CommandOptionId opt_no_self_checking = cmd.option("no_self_checking"); CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); CommandOptionId opt_verbose = cmd.option("verbose"); @@ -94,7 +93,6 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_print_top_testbench(true); options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); - options.set_no_self_checking(cmd_context.option_enable(cmd, opt_no_self_checking)); if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); } @@ -186,7 +184,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); - CommandOptionId opt_no_self_checking = cmd.option("no_self_checking"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -199,7 +196,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_print_preconfig_top_testbench(true); - options.set_no_self_checking(cmd_context.option_enable(cmd, opt_no_self_checking)); if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); } diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 3b0c94138..bbee67815 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -196,7 +196,7 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); /* Add an option '--reference_benchmark_file_path'*/ - CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist"); + CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes"); shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); /* Add an option '--explicit_port_mapping' */ @@ -206,9 +206,6 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'"); shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING); - /* Add an option '--no_self_checking' */ - shell_cmd.add_option("no_self_checking", false, "Do not generate self-checking codes for Verilog testbenches."); - /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Enable verbose output"); @@ -244,7 +241,7 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell Date: Tue, 29 Jun 2021 15:52:42 -0600 Subject: [PATCH 45/89] [Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated --- openfpga_flow/scripts/run_fpga_flow.py | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 1593d3f85..a333ebb8f 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -741,11 +741,6 @@ def run_netlists_verification(exit_if_fail=True): command = [cad_tools["iverilog_path"]] command += ["-o", compiled_file] - fpga_define_file = "./SRC/define_simulation.v" - fpga_define_file_bk = "./SRC/define_simulation.v.bak" - shutil.copy(fpga_define_file, fpga_define_file_bk) - with open(fpga_define_file, "r") as fp: - fpga_defines = fp.readlines() command += ["./SRC/%s_include_netlists.v" % args.top_module] command += ["-s"] @@ -753,11 +748,6 @@ def run_netlists_verification(exit_if_fail=True): command += [tb_top_formal] else: command += [tb_top_autochecked] - with open(fpga_define_file, "w") as fp: - for eachLine in fpga_defines: - if not (("ENABLE_FORMAL_VERIFICATION" in eachLine) or - "FORMAL_SIMULATION" in eachLine): - fp.write(eachLine) run_command("iverilog_verification", "iverilog_output.txt", command) vvp_command = ["vvp", compiled_file] From 01391fd81e460b80c81707253a499d592acd96b3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 15:56:33 -0600 Subject: [PATCH 46/89] [Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features --- ...hout_self_checking_example_script.openfpga | 74 ++++++++++++++++++ ...hout_self_checking_example_script.openfpga | 75 +++++++++++++++++++ 2 files changed, 149 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga create mode 100644 openfpga_flow/openfpga_shell_scripts/preconfigure_testbench_without_self_checking_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga new file mode 100644 index 000000000..31717063b --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/preconfigure_testbench_without_self_checking_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfigure_testbench_without_self_checking_example_script.openfpga new file mode 100644 index 000000000..7fd7053f8 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/preconfigure_testbench_without_self_checking_example_script.openfpga @@ -0,0 +1,75 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 20faf82e64cac216004bab385df9226b9351ae92 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 16:02:35 -0600 Subject: [PATCH 47/89] [Script] Rename example script --- ...gured_testbench_without_self_checking_example_script.openfpga} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename openfpga_flow/openfpga_shell_scripts/{preconfigure_testbench_without_self_checking_example_script.openfpga => preconfigured_testbench_without_self_checking_example_script.openfpga} (100%) diff --git a/openfpga_flow/openfpga_shell_scripts/preconfigure_testbench_without_self_checking_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga similarity index 100% rename from openfpga_flow/openfpga_shell_scripts/preconfigure_testbench_without_self_checking_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga From 30c2f597f2c01683d7f2036879981a6b10bdc76a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 16:06:15 -0600 Subject: [PATCH 48/89] [Test] Added two cases to validate testbench generation without self checking --- .../config/task.conf | 36 +++++++++++++++++++ .../config/task.conf | 35 ++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf new file mode 100644 index 000000000..2fe7d3e62 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2_latch +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf new file mode 100644 index 000000000..d511bdbb9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2_latch +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From cbea4a3cb6ca20050f2c861bdc05a2cdf6b3d45e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 16:08:22 -0600 Subject: [PATCH 49/89] [Test] Add the test cases to regression test --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index b9d4039d0..0a11ed4e0 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -53,6 +53,10 @@ run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs +echo -e "Testing testbenches without self checking features"; +run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking --debug --show_thread_logs + echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs From b83eef47b48db73f873968a37e5f8851504ba076 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 16:27:29 -0600 Subject: [PATCH 50/89] [Tool] Bug fix for testbench generation without self checking codes --- .../src/base/openfpga_verilog_command.cpp | 2 +- .../verilog_formal_random_top_testbench.cpp | 6 +- .../fpga_verilog/verilog_testbench_utils.cpp | 65 ++++++++++++------- .../fpga_verilog/verilog_testbench_utils.h | 6 +- .../fpga_verilog/verilog_top_testbench.cpp | 6 +- 5 files changed, 53 insertions(+), 32 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index bbee67815..165a0eb38 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -84,7 +84,7 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell& clock_port_names, const std::string& check_flag_port_postfix, - const std::vector& clock_ports) { + const std::vector& clock_ports, + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); @@ -569,25 +582,27 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, } } - /* Add an empty line as splitter */ - fp << std::endl; - /* Set 0 to registers for checking flags */ - for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { - /* Bypass non-I/O atom blocks ! */ - if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) { - continue; + if (!no_self_checking) { + /* Add an empty line as splitter */ + fp << std::endl; + + for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { + /* Bypass non-I/O atom blocks ! */ + if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) { + continue; + } + + /* The block may be renamed as it contains special characters which violate Verilog syntax */ + std::string block_name = atom_ctx.nlist.block_name(atom_blk); + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + block_name = netlist_annotation.block_name(atom_blk); + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1); + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl; } - - /* The block may be renamed as it contains special characters which violate Verilog syntax */ - std::string block_name = atom_ctx.nlist.block_name(atom_blk); - if (true == netlist_annotation.is_block_renamed(atom_blk)) { - block_name = netlist_annotation.block_name(atom_blk); - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1); - fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl; } fp << "\tend" << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 7b6858ce5..f45452c6d 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -56,7 +56,8 @@ void print_verilog_timeout_and_vcd(std::fstream& fp, const std::string& vcd_fname, const std::string& simulation_start_counter_name, const std::string& error_counter_name, - const float& simulation_time); + const float& simulation_time, + const bool& no_self_checking); std::vector generate_verilog_testbench_clock_port(const std::vector& clock_port_names, const std::string& default_clock_name); @@ -85,7 +86,8 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, const PinConstraints& pin_constraints, const std::vector& clock_port_names, const std::string& check_flag_port_postfix, - const std::vector& clock_ports); + const std::vector& clock_ports, + const bool& no_self_checking); void print_verilog_testbench_shared_ports(std::fstream& fp, const AtomContext& atom_ctx, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 49fe46889..47300ce1e 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -2038,7 +2038,8 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, pin_constraints, clock_port_names, std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - std::vector(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1))); + std::vector(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)), + options.no_self_checking()); if (!options.no_self_checking()) { /* Add output autocheck */ @@ -2075,7 +2076,8 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, std::string(circuit_name + std::string("_formal.vcd")), std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), std::string(TOP_TESTBENCH_ERROR_COUNTER), - std::ceil(simulation_time)); + std::ceil(simulation_time), + options.no_self_checking()); /* Testbench ends*/ From b5df1f9aeb3f92ea3d385aaba4d1ab69d7ac93bb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 17:02:16 -0600 Subject: [PATCH 51/89] [Tool] Bug fix for redundant endif in netlists --- openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index b36501102..09974ca12 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -123,9 +123,7 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir, /* Include reference benchmark netlist only when auto-check flag is enabled */ if (!no_self_checking) { - fp << "\t"; print_verilog_include_netlist(fp, std::string(reference_benchmark_file)); - print_verilog_endif(fp); fp << std::endl; } @@ -171,9 +169,7 @@ void print_verilog_preconfigured_testbench_include_netlists(const std::string& s /* Include reference benchmark netlist only when auto-check flag is enabled */ if (!no_self_checking) { - fp << "\t"; print_verilog_include_netlist(fp, std::string(reference_benchmark_file)); - print_verilog_endif(fp); fp << std::endl; } From 9655bc35cb2b5829abdaac50ca2889a5b40ed7be Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 17:04:19 -0600 Subject: [PATCH 52/89] [Script] Bug fix due to the full testbench generation changes --- .../generate_testbench_example_script.openfpga | 2 -- 1 file changed, 2 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index b0322f105..0b5cfa232 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -52,8 +52,6 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis From 4fb34642cafb207cccb9d0cd91be223c1afa0b46 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 17:53:56 -0600 Subject: [PATCH 53/89] [Script] Add a new example script for global tile clock running full testbench --- ...ock_full_testbench_example_script.openfpga | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga new file mode 100644 index 000000000..d15fb05e5 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 2c1692e6dce72e66b2b32fc5017adb3e2a4194b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 17:54:25 -0600 Subject: [PATCH 54/89] [Test] Bug fix --- .../basic_tests/fixed_simulation_settings/config/task.conf | 5 +++-- .../tasks/fpga_verilog/io/registerable_io/config/task.conf | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf index 78daaf0c9..cb41e9959 100644 --- a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -34,4 +36,3 @@ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf index 700f8e3c7..9f7cd13a3 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 From 5f5a03f17fb12b7832723767ca7c42965d6c1acb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 18:28:38 -0600 Subject: [PATCH 55/89] [Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches --- .../generate_secure_fabric_example_script.openfpga | 2 -- .../basic_tests/fabric_key/generate_random_key/config/task.conf | 1 - 2 files changed, 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga index 6efc2baa5..c2107e0cb 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga @@ -59,8 +59,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf index 069541110..14110892b 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf @@ -34,4 +34,3 @@ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= From c6089385b095ffb3e607e3d00ee6aefe5308ad7e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 18:34:41 -0600 Subject: [PATCH 56/89] [Misc] Bug fix --- .../generate_secure_fabric_from_key_example_script.openfpga | 2 -- .../basic_tests/fabric_key/load_external_key/config/task.conf | 1 - 2 files changed, 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga index 4dd7f21c3..0431c5f75 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga @@ -59,8 +59,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf index 787e469d0..474f802dc 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf @@ -36,4 +36,3 @@ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= From 56b0428eba12713ef4ead2b619a0141296ca702b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 18:48:19 -0600 Subject: [PATCH 57/89] [Misc] Bug fix --- .../global_tile_clock_example_script.openfpga | 2 -- 1 file changed, 2 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga index db51ffe15..fe4a4abdb 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga @@ -58,8 +58,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here From f32ffb6d6197a5e487f9540df53856f7c98637c9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 18:51:28 -0600 Subject: [PATCH 58/89] [Test] Bug fix --- .../global_tile_clock_example_script.openfpga | 3 ++- .../global_tile_multiclock_example_script.openfpga | 1 - .../global_tile_ports/global_tile_clock/config/task.conf | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga index fe4a4abdb..086dc9eb0 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga @@ -57,7 +57,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga index ff0ba8d81..1b1daae4d 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga @@ -61,7 +61,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf index abc1be003..99b9d3f47 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml From 9eeec05a1f313c31466fd17cb33b406cab93458b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 19:55:07 -0600 Subject: [PATCH 59/89] [Test] Bug fix --- .../global_tile_ports/global_tile_clock/config/task.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf index 99b9d3f47..ab945d768 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=auto [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml From 4d4577bb835779a90578d65b902ac1aa9f058d6a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Jun 2021 15:13:47 -0600 Subject: [PATCH 60/89] [Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders --- .../micro_benchmark/adder/adder_16/adder_16.v | 21 ++++++ .../micro_benchmark/adder/adder_4/adder_4.v | 21 ++++++ .../micro_benchmark/adder/adder_6/adder_6.v | 21 ++++++ .../{ => adder}/adder_8/adder_8.act | 0 .../{ => adder}/adder_8/adder_8.eblif | 0 .../{ => adder}/adder_8/adder_8.v | 0 .../{ => adder}/adder_8/adder_8_out.v | 0 .../adder/adder_8/adder_8_post_synthesis.v | 65 +++++++++++++++++++ 8 files changed, 128 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.act (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.eblif (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8_out.v (100%) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v new file mode 100644 index 000000000..2e7d31076 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_16(cout, sum, a, b, cin); +parameter size = 6; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v new file mode 100644 index 000000000..b444bfa3a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_4(cout, sum, a, b, cin); +parameter size = 4; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v new file mode 100644 index 000000000..74a09005d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_6(cout, sum, a, b, cin); +parameter size = 6; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v new file mode 100644 index 000000000..1e7069e8c --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v @@ -0,0 +1,65 @@ +/* Generated by Yosys 0.9+2406 (git sha1 3a9968de, gcc 8.4.0 -fPIC -Os) */ + +module adder_8(\a[0] , \a[1] , \a[2] , \a[3] , \a[4] , \a[5] , \a[6] , \a[7] , \b[0] , \b[1] , \b[2] , \b[3] , \b[4] , \b[5] , \b[6] , \b[7] , cin, cout, \sum[0] , \sum[1] , \sum[2] , \sum[3] , \sum[4] , \sum[5] , \sum[6] , \sum[7] ); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire _10_; + wire _11_; + wire _12_; + input \a[0] ; + input \a[1] ; + input \a[2] ; + input \a[3] ; + input \a[4] ; + input \a[5] ; + input \a[6] ; + input \a[7] ; + input \b[0] ; + input \b[1] ; + input \b[2] ; + input \b[3] ; + input \b[4] ; + input \b[5] ; + input \b[6] ; + input \b[7] ; + input cin; + output cout; + output \sum[0] ; + output \sum[1] ; + output \sum[2] ; + output \sum[3] ; + output \sum[4] ; + output \sum[5] ; + output \sum[6] ; + output \sum[7] ; + assign cout = 8'h8e >> { _00_, \a[7] , \b[7] }; + assign _08_ = 4'h8 >> { \a[5] , \b[5] }; + assign \sum[0] = 8'h96 >> { \a[0] , \b[0] , cin }; + assign \sum[1] = 8'h69 >> { _05_, \a[1] , \b[1] }; + assign \sum[2] = 16'h6a56 >> { _05_, \a[1] , \b[1] , _04_ }; + assign \sum[3] = 16'h9996 >> { _03_, _06_, \a[3] , \b[3] }; + assign \sum[4] = 8'h69 >> { _02_, \a[4] , \b[4] }; + assign \sum[5] = 8'h69 >> { _09_, \a[5] , \b[5] }; + assign _09_ = 8'h71 >> { _02_, \a[4] , \b[4] }; + assign \sum[6] = 16'h9996 >> { _01_, _08_, \a[6] , \b[6] }; + assign \sum[7] = 8'h69 >> { _00_, \a[7] , \b[7] }; + assign _00_ = 16'h011f >> { \a[6] , \b[6] , _01_, _08_ }; + assign _01_ = 16'h4054 >> { _02_, \a[4] , \b[4] , _07_ }; + assign _02_ = 16'h011f >> { \a[3] , \b[3] , _03_, _06_ }; + assign _03_ = 16'h80a8 >> { _05_, \a[1] , \b[1] , _04_ }; + assign _04_ = 4'h6 >> { \a[2] , \b[2] }; + assign _05_ = 8'h17 >> { \a[0] , \b[0] , cin }; + assign _06_ = 4'h8 >> { \a[2] , \b[2] }; + assign _07_ = 4'h1 >> { \a[5] , \b[5] }; + assign _10_ = 1'h0; + assign _11_ = 1'h1; + assign _12_ = 1'hx; +endmodule From 83d177b13b11a9a2d77a00612f570667bdcdb38c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Jun 2021 15:14:24 -0600 Subject: [PATCH 61/89] [Test] Deploy the newly added adder benchmarks to tests --- .../lut_adder_test/config/task.conf | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 4f501a1c3..12f1bebe1 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -27,18 +27,20 @@ yosys_args = -family qlf_k4n8 -no_ff_map arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys -bench1_top = adder_8 +bench0_top = adder_4 +bench1_top = adder_6 +bench2_top = adder_8 +bench3_top = adder_16 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -########################## -# The output verilog of yosys is not synthesizable!!! -# Turn off verification for now -# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow end_flow_with_test= vpr_fpga_verilog_formal_verification_top_netlist= From a89853747404ea63eb9378763771d9d295069a4b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Jun 2021 15:29:13 -0600 Subject: [PATCH 62/89] [Benchmark] Remove redundant post-synthesis netlist for ``adder_8`` --- .../adder/adder_8/adder_8_post_synthesis.v | 65 ------------------- 1 file changed, 65 deletions(-) delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v deleted file mode 100644 index 1e7069e8c..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v +++ /dev/null @@ -1,65 +0,0 @@ -/* Generated by Yosys 0.9+2406 (git sha1 3a9968de, gcc 8.4.0 -fPIC -Os) */ - -module adder_8(\a[0] , \a[1] , \a[2] , \a[3] , \a[4] , \a[5] , \a[6] , \a[7] , \b[0] , \b[1] , \b[2] , \b[3] , \b[4] , \b[5] , \b[6] , \b[7] , cin, cout, \sum[0] , \sum[1] , \sum[2] , \sum[3] , \sum[4] , \sum[5] , \sum[6] , \sum[7] ); - wire _00_; - wire _01_; - wire _02_; - wire _03_; - wire _04_; - wire _05_; - wire _06_; - wire _07_; - wire _08_; - wire _09_; - wire _10_; - wire _11_; - wire _12_; - input \a[0] ; - input \a[1] ; - input \a[2] ; - input \a[3] ; - input \a[4] ; - input \a[5] ; - input \a[6] ; - input \a[7] ; - input \b[0] ; - input \b[1] ; - input \b[2] ; - input \b[3] ; - input \b[4] ; - input \b[5] ; - input \b[6] ; - input \b[7] ; - input cin; - output cout; - output \sum[0] ; - output \sum[1] ; - output \sum[2] ; - output \sum[3] ; - output \sum[4] ; - output \sum[5] ; - output \sum[6] ; - output \sum[7] ; - assign cout = 8'h8e >> { _00_, \a[7] , \b[7] }; - assign _08_ = 4'h8 >> { \a[5] , \b[5] }; - assign \sum[0] = 8'h96 >> { \a[0] , \b[0] , cin }; - assign \sum[1] = 8'h69 >> { _05_, \a[1] , \b[1] }; - assign \sum[2] = 16'h6a56 >> { _05_, \a[1] , \b[1] , _04_ }; - assign \sum[3] = 16'h9996 >> { _03_, _06_, \a[3] , \b[3] }; - assign \sum[4] = 8'h69 >> { _02_, \a[4] , \b[4] }; - assign \sum[5] = 8'h69 >> { _09_, \a[5] , \b[5] }; - assign _09_ = 8'h71 >> { _02_, \a[4] , \b[4] }; - assign \sum[6] = 16'h9996 >> { _01_, _08_, \a[6] , \b[6] }; - assign \sum[7] = 8'h69 >> { _00_, \a[7] , \b[7] }; - assign _00_ = 16'h011f >> { \a[6] , \b[6] , _01_, _08_ }; - assign _01_ = 16'h4054 >> { _02_, \a[4] , \b[4] , _07_ }; - assign _02_ = 16'h011f >> { \a[3] , \b[3] , _03_, _06_ }; - assign _03_ = 16'h80a8 >> { _05_, \a[1] , \b[1] , _04_ }; - assign _04_ = 4'h6 >> { \a[2] , \b[2] }; - assign _05_ = 8'h17 >> { \a[0] , \b[0] , cin }; - assign _06_ = 4'h8 >> { \a[2] , \b[2] }; - assign _07_ = 4'h1 >> { \a[5] , \b[5] }; - assign _10_ = 1'h0; - assign _11_ = 1'h1; - assign _12_ = 1'hx; -endmodule From fab2b069f0bb83dc27530c70e8f79fd2612024e9 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Wed, 30 Jun 2021 16:18:09 -0600 Subject: [PATCH 63/89] added signal gen regression test to shell script --- .../config_loader/bitstream_loader.v | 143 ++++-------------- .../micro_benchmark_reg_test.sh | 3 + 2 files changed, 34 insertions(+), 112 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v index 68b04aee1..69a92ff92 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v +++ b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v @@ -38,35 +38,26 @@ module bitstream_loader( wire bram_output; assign config_chain_head = bram_output; - RAMB18E1 #( - // Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE" - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - // Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") - .SIM_COLLISION_CHECK("ALL"), - // RAM Mode: "SDP" or "TDP" - .RAM_MODE("TDP"), - // READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port - .READ_WIDTH_A(1), // 0-72 - .READ_WIDTH_B(0), // 0-18 - .WRITE_WIDTH_A(0), // 0-18 - .WRITE_WIDTH_B(0), // 0-72 + EFX_RAM_5K #( + .READ_WIDTH(1), + .WRITE_WIDTH(0), - .INIT_00(256'h00000000000000000000000000000000000000000000007f00000000000000ff), - .INIT_01(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), - .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_04(256'h00000003f8000000000000000000000000000000000000000000000000000000), - .INIT_05(256'h0000000000000000078000000000000000000000000000000000000000000000), - .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0(256'h00000000000000000000000000000000000000000000007f00000000000000ff), + .INIT_1(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), + .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4(256'h00000003f8000000000000000000000000000000000000000000000000000000), + .INIT_5(256'h0000000000000000078000000000000000000000000000000000000000000000), + .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), @@ -75,92 +66,20 @@ module bitstream_loader( .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000), - .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), - - - - // RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE") - .RSTREG_PRIORITY_A("RSTREG"), - .RSTREG_PRIORITY_B("RSTREG"), - // SRVAL_A, SRVAL_B: Set/reset value for output - .SRVAL_A(18'hFFFFF), - .SRVAL_B(18'h00000), - // Simulation Device: Must be set to "7SERIES" for simulation behavior - .SIM_DEVICE("7SERIES"), - // WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE") - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST") ) - RAMB18E1_inst ( + EFX_RAM_5K_inst ( // Port A Data: 16-bit (each) output: Port A data - .DOADO(bram_output), // 16-bit output: A port data/LSB data - .DOPADOP(), // 2-bit output: A port parity/LSB parity - // Port B Data: 16-bit (each) output: Port B data - .DOBDO(), // 16-bit output: B port data/MSB data - .DOPBDOP(), // 2-bit output: B port parity/MSB parity - // Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port - // when RAM_MODE="SDP") - .ADDRARDADDR(bram_addr), // 14-bit input: A port address/Read address - .CLKARDCLK(~prog_clk), // 1-bit input: A port clock/Read clock - .ENARDEN(1'b1), // 1-bit input: A port enable/Read enable - .REGCEAREGCE(1'b1), // 1-bit input: A port register enable/Register enable - .RSTRAMARSTRAM(0), // 1-bit input: A port set/reset - .RSTREGARSTREG(0), // 1-bit input: A port register set/reset - .WEA(2'b00), // 2-bit input: A port write enable - // Port A Data: 16-bit (each) input: Port A data - .DIADI(0), // 16-bit input: A port data/LSB data - .DIPADIP(0), // 2-bit input: A port parity/LSB parity - // Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port - // when RAM_MODE="SDP") - .ADDRBWRADDR(0), // 14-bit input: B port address/Write address - .CLKBWRCLK(0), // 1-bit input: B port clock/Write clock - .ENBWREN(0), // 1-bit input: B port enable/Write enable - .REGCEB(0), // 1-bit input: B port register enable - .RSTRAMB(0), // 1-bit input: B port set/reset - .RSTREGB(0), // 1-bit input: B port register set/reset - .WEBWE(0), // 4-bit input: B port write enable/Write enable - // Port B Data: 16-bit (each) input: Port B data - .DIBDI(0), // 16-bit input: B port data/MSB data - .DIPBDIP(0) // 2-bit input: B port parity/MSB parity + .WDATA(0), // Write data + .WADDR(0), // Write address + .WE(0), // Write enable + + .WCLK(0), + .WCLKE(0), + + .RDATA(bram_output), + .RADDR(bram_addr), + .RE(1'b1), + .RCLK(prog_clk) ); diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 28b24aef3..0790421bb 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -15,3 +15,6 @@ run-task benchmark_sweep/mac_units --debug --show_thread_logs # Otherwise, it will fail run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim + + +run-task benchmark_sweep/signal_gen --debug --show_thread_logs From db9231c2251a6be9e20f0c75181b596d54a6a783 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 13:52:28 -0600 Subject: [PATCH 64/89] tests failing with initial blocks --- .../signal_gen/clock_divider.v | 8 +++---- .../signal_gen/pulse_generator.v | 14 ++++++------ .../benchmark_sweep_test.sh | 11 ---------- .../micro_benchmark_reg_test.sh | 7 +++--- .../signal_gen/config/task.conf | 22 ++++++++++++------- 5 files changed, 29 insertions(+), 33 deletions(-) delete mode 100755 openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v index 4127cd9f3..8172b7c6d 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v @@ -29,10 +29,10 @@ module clock_divider ( reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; - initial begin - clkdiv_counter <= 0; - clk_out <= 0; - end + // initial begin + // clkdiv_counter <= 0; + // clk_out <= 0; + // end // Divide pl_clk (50MHz) to 1MHz always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v index a73fc37f6..ff3391d55 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v @@ -36,13 +36,13 @@ module pulse_generator( reg pulse_start; reg pulse_end; - initial begin - pulse <= INITIAL_VALUE; - pulse_start <= 1'b0; - pulse_end <= 1'b0; - wait_cycle_counter <= 0; - pulse_width_counter <= 0; - end + // initial begin + // pulse <= INITIAL_VALUE; + // pulse_start <= 1'b0; + // pulse_end <= 1'b0; + // wait_cycle_counter <= 0; + // pulse_width_counter <= 0; + // end // Wait a number of clock cycles, hold the initial value always @(posedge clk_in) begin diff --git a/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh b/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh deleted file mode 100755 index 01f278fe9..000000000 --- a/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -set -e -source openfpga.sh -PYTHON_EXEC=python3.8 -############################################### -# OpenFPGA Shell with VPR8 -############################################## - -echo -e "Benchmark sweep tests"; -run-task benchmark_sweep/signal_gen --debug --show_thread_logs \ No newline at end of file diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 0790421bb..44ecacd30 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,14 +7,15 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -run-task benchmark_sweep/counter --debug --show_thread_logs -run-task benchmark_sweep/mac_units --debug --show_thread_logs +# run-task benchmark_sweep/counter --debug --show_thread_logs +# run-task benchmark_sweep/mac_units --debug --show_thread_logs # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail -run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim +# run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index b1f3d4e47..6158af998 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -16,23 +16,29 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v -# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v -# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] -bench0_top = pulse_generator -# bench1_top = reset_generator -# bench2_top = clock_divider +bench0_top = clock_divider +bench0_chan_width = 300 + +bench1_top = pulse_generator +bench1_chan_width = 300 + +# bench2_top = reset_generator +# bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= From 2567fbee05ac26d2b6c1a015464f03267945c586 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 15:28:59 -0600 Subject: [PATCH 65/89] ready to merge --- .../signal_gen/clock_divider.v | 13 +++++++---- .../signal_gen/pulse_generator.v | 22 ++++++++++++------- .../signal_gen/reset_generator.v | 5 +++++ .../micro_benchmark_reg_test.sh | 8 +++---- .../signal_gen/config/task.conf | 6 ++--- 5 files changed, 34 insertions(+), 20 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v index 8172b7c6d..3cb3f9899 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v @@ -19,6 +19,9 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS module clock_divider ( input clk_in, @@ -29,10 +32,12 @@ module clock_divider ( reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; - // initial begin - // clkdiv_counter <= 0; - // clk_out <= 0; - // end +`ifdef VIVADO_SYNTHESIS + initial begin + clkdiv_counter <= 0; + clk_out <= 0; + end +`endif // Divide pl_clk (50MHz) to 1MHz always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v index ff3391d55..1f092e6a0 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v @@ -19,6 +19,10 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS + module pulse_generator( input clk_in, input repeated, // Specify if the pulse should be generated repeatedly @@ -35,14 +39,16 @@ module pulse_generator( reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter; reg pulse_start; reg pulse_end; - - // initial begin - // pulse <= INITIAL_VALUE; - // pulse_start <= 1'b0; - // pulse_end <= 1'b0; - // wait_cycle_counter <= 0; - // pulse_width_counter <= 0; - // end + +`ifdef VIVADO_SYNTHESIS + initial begin + pulse <= INITIAL_VALUE; + pulse_start <= 1'b0; + pulse_end <= 1'b0; + wait_cycle_counter <= 0; + pulse_width_counter <= 0; + end +`endif // Wait a number of clock cycles, hold the initial value always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v index f949e722a..6de4b6980 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v @@ -19,6 +19,9 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS module reset_generator( input clk, @@ -30,10 +33,12 @@ module reset_generator( reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; +`ifdef VIVADO_SYNTHESIS initial begin pulse <= INITIAL_VALUE; active_cycle_counter <= 0; end +`endif // Wait a number of clock cycles, hold the initial value always @(posedge clk) begin diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 44ecacd30..5f958e261 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,15 +7,13 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -# run-task benchmark_sweep/counter --debug --show_thread_logs -# run-task benchmark_sweep/mac_units --debug --show_thread_logs +run-task benchmark_sweep/counter --debug --show_thread_logs +run-task benchmark_sweep/mac_units --debug --show_thread_logs # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail -# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim - -# run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 6158af998..c6306d7da 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -27,15 +27,15 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v # bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] bench0_top = clock_divider bench0_chan_width = 300 -bench1_top = pulse_generator -bench1_chan_width = 300 +# bench1_top = pulse_generator +# bench1_chan_width = 300 # bench2_top = reset_generator # bench2_chan_width = 300 From 006b54c4bcc42dd09de78f2b45c83a3091df2b81 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 15:35:39 -0600 Subject: [PATCH 66/89] ready for merge --- .../benchmark_sweep/signal_gen/config/task.conf | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index c6306d7da..9ada9e960 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -27,18 +27,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v -# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v -# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] bench0_top = clock_divider bench0_chan_width = 300 -# bench1_top = pulse_generator -# bench1_chan_width = 300 +bench1_top = pulse_generator +bench1_chan_width = 300 -# bench2_top = reset_generator -# bench2_chan_width = 300 +bench2_top = reset_generator +bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From 808821bb8c6fcd89cf2e53d5fb42e46d87ca95fd Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 16:40:03 -0600 Subject: [PATCH 67/89] fixed errors --- .../signal_gen/reset_generator.v | 41 ++++++++++--------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v index 6de4b6980..84e957cb1 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v @@ -24,29 +24,30 @@ // `define VIVADO_SYNTHESIS module reset_generator( - input clk, - output reg pulse + input clk, + output reg pulse ); + + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value + parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied - parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value - parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied - - reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; - + reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; + `ifdef VIVADO_SYNTHESIS - initial begin - pulse <= INITIAL_VALUE; - active_cycle_counter <= 0; - end -`endif - - // Wait a number of clock cycles, hold the initial value - always @(posedge clk) begin - if (active_cycle_counter == ACTIVE_CYCLES) begin - pulse <= ~INITIAL_VALUE; - end else begin - active_cycle_counter <= active_cycle_counter + 1; + initial begin + clkdiv_counter <= 0; + active_cycle_counter <= 0; + pulse <= INITIAL_VALUE; end - end +`endif + // Wait a number of clock cycles, hold the initial value + always @(posedge clk) begin + if (active_cycle_counter == ACTIVE_CYCLES) begin + pulse <= ~pulse; + end else begin + active_cycle_counter <= active_cycle_counter + 1; + end + end + endmodule From 1d281765ea6d520b96a27f3c4e50fa3d25110ad6 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 16:42:04 -0600 Subject: [PATCH 68/89] fixed tab spacing --- .../signal_gen/reset_generator.v | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v index 84e957cb1..bbb73e440 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v @@ -24,21 +24,21 @@ // `define VIVADO_SYNTHESIS module reset_generator( - input clk, - output reg pulse - ); - + input clk, + output reg pulse + ); + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; - + `ifdef VIVADO_SYNTHESIS - initial begin - clkdiv_counter <= 0; - active_cycle_counter <= 0; - pulse <= INITIAL_VALUE; - end + initial begin + clkdiv_counter <= 0; + active_cycle_counter <= 0; + pulse <= INITIAL_VALUE; + end `endif // Wait a number of clock cycles, hold the initial value @@ -49,5 +49,5 @@ module reset_generator( active_cycle_counter <= active_cycle_counter + 1; end end - + endmodule From d0e4f8521f89e804c6bd9e139a3bff946876728f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 19:58:54 -0600 Subject: [PATCH 69/89] [Tool] Bug fix on the reset stimuli --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 7b54ceb44..7194f208f 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -230,7 +230,7 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, */ fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; - print_verilog_wire_connection(fp, reset_port, reset_port, true); + print_verilog_register_connection(fp, reset_port, reset_port, true); fp << "\tend" << std::endl; } From 81f9dff9ff413ab6c27d2a96cb4ce28eb2c372dd Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 1 Jul 2021 22:19:53 -0600 Subject: [PATCH 70/89] [Flow] Allows benchmark specific var declaraton --- openfpga_flow/scripts/run_fpga_task.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 0cb6612e1..1a373df9b 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -271,6 +271,9 @@ def generate_each_task_actions(taskname): fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) + for eachKey, eachValue in SynthSection.items(): + eachKey = eachKey.replace(bech_name+"_","") + CurrBenchPara[eachKey] = eachValue if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -320,7 +323,7 @@ def generate_each_task_actions(taskname): flow_run_dir = get_flow_rundir(arch, "bench" + str(benchmark_list.index(bench)) + "_" + bench["top_module"], lbl) else: flow_run_dir = get_flow_rundir(arch, bench["top_module"], lbl) - + command = create_run_command( curr_job_dir=flow_run_dir, archfile=arch, From 1de1f2f2e23f5caa14f859a77a427b48590a0ba8 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 1 Jul 2021 22:26:00 -0600 Subject: [PATCH 71/89] [FLOW] Variable in capital case --- openfpga_flow/scripts/run_fpga_task.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 1a373df9b..66ac0f838 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -272,7 +272,7 @@ def generate_each_task_actions(taskname): CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) for eachKey, eachValue in SynthSection.items(): - eachKey = eachKey.replace(bech_name+"_","") + eachKey = eachKey.replace(bech_name+"_","").upper() CurrBenchPara[eachKey] = eachValue if GeneralSection.get("fpga_flow") == "vpr_blif": From 9074bffa68f8bcb3c142855bc15ecc08bf49c434 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 23:43:19 -0600 Subject: [PATCH 72/89] [Tool] Support customized default value in pin constraint file --- libopenfpga/libpcf/src/pin_constraints.cpp | 51 +++++++++++++++++++ libopenfpga/libpcf/src/pin_constraints.h | 38 ++++++++++++++ .../libpcf/src/read_xml_pin_constraints.cpp | 8 +++ .../libpcf/src/write_xml_pin_constraints.cpp | 1 + .../verilog_formal_random_top_testbench.cpp | 4 ++ .../fpga_verilog/verilog_top_testbench.cpp | 8 ++- 6 files changed, 109 insertions(+), 1 deletion(-) diff --git a/libopenfpga/libpcf/src/pin_constraints.cpp b/libopenfpga/libpcf/src/pin_constraints.cpp index 25cd1048d..bc68b3bd8 100644 --- a/libopenfpga/libpcf/src/pin_constraints.cpp +++ b/libopenfpga/libpcf/src/pin_constraints.cpp @@ -60,6 +60,36 @@ openfpga::BasicPort PinConstraints::net_pin(const std::string& net) const { return constrained_pin; } +PinConstraints::e_logic_level PinConstraints::net_default_value(const std::string& net) const { + PinConstraints::e_logic_level logic_level = PinConstraints::NUM_LOGIC_LEVELS; + for (const PinConstraintId& pin_constraint : pin_constraints()) { + if (net == pin_constraint_nets_[pin_constraint]) { + logic_level = pin_constraint_net_default_values_[pin_constraint]; + break; + } + } + return logic_level; +} + +std::string PinConstraints::net_default_value_to_string(const PinConstraintId& pin_constraint) const { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + if (PinConstraints::LOGIC_HIGH == pin_constraint_net_default_values_[pin_constraint]) { + return std::string("1"); + } else if (PinConstraints::LOGIC_LOW == pin_constraint_net_default_values_[pin_constraint]) { + return std::string("0"); + } + return std::string(); +} + +size_t PinConstraints::net_default_value_to_int(const std::string& net) const { + if (PinConstraints::LOGIC_HIGH == net_default_value(net)) { + return 1; + } else if (PinConstraints::LOGIC_LOW == net_default_value(net)) { + return 0; + } + return -1; +} + bool PinConstraints::empty() const { return 0 == pin_constraint_ids_.size(); } @@ -71,6 +101,7 @@ void PinConstraints::reserve_pin_constraints(const size_t& num_pin_constraints) pin_constraint_ids_.reserve(num_pin_constraints); pin_constraint_pins_.reserve(num_pin_constraints); pin_constraint_nets_.reserve(num_pin_constraints); + pin_constraint_net_default_values_.reserve(num_pin_constraints); } PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& pin, @@ -81,10 +112,21 @@ PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& pin_constraint_ids_.push_back(pin_constraint_id); pin_constraint_pins_.push_back(pin); pin_constraint_nets_.push_back(net); + pin_constraint_net_default_values_.push_back(PinConstraints::NUM_LOGIC_LEVELS); return pin_constraint_id; } +void PinConstraints::set_net_default_value(const PinConstraintId& pin_constraint, + const std::string& default_value) { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + if (default_value == std::string("1")) { + pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_HIGH; + } else if (default_value == std::string("0")) { + pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_LOW; + } +} + /************************************************************************ * Internal invalidators/validators ***********************************************************************/ @@ -100,3 +142,12 @@ bool PinConstraints::unconstrained_net(const std::string& net) const { bool PinConstraints::unmapped_net(const std::string& net) const { return std::string(PIN_CONSTRAINT_OPEN_NET) == net; } + +bool PinConstraints::valid_net_default_value(const PinConstraintId& pin_constraint) const { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + return PinConstraints::NUM_LOGIC_LEVELS != pin_constraint_net_default_values_[pin_constraint]; +} + +bool PinConstraints::valid_net_default_value(const std::string& net) const { + return PinConstraints::NUM_LOGIC_LEVELS != net_default_value(net); +} diff --git a/libopenfpga/libpcf/src/pin_constraints.h b/libopenfpga/libpcf/src/pin_constraints.h index 3ea3aad2f..a60f0aae4 100644 --- a/libopenfpga/libpcf/src/pin_constraints.h +++ b/libopenfpga/libpcf/src/pin_constraints.h @@ -41,6 +41,12 @@ class PinConstraints { typedef vtr::vector::const_iterator pin_constraint_iterator; /* Create range */ typedef vtr::Range pin_constraint_range; + /* Logic value */ + enum e_logic_level { + LOGIC_HIGH, + LOGIC_LOW, + NUM_LOGIC_LEVELS + }; public: /* Constructors */ PinConstraints(); public: /* Accessors: aggregates */ @@ -63,6 +69,21 @@ class PinConstraints { */ openfpga::BasicPort net_pin(const std::string& net) const; + /* Find the default value that a net is constrained to + * If not found, return an invalid value + */ + e_logic_level net_default_value(const std::string& net) const; + + /* Generate the string of the default value + * If not found, return an empty string + */ + std::string net_default_value_to_string(const PinConstraintId& pin_constraint) const; + + /* Generate the integer representation of the default value + * If not found, return -1 + */ + size_t net_default_value_to_int(const std::string& net) const; + /* Check if there are any pin constraints */ bool empty() const; @@ -74,6 +95,10 @@ class PinConstraints { PinConstraintId create_pin_constraint(const openfpga::BasicPort& pin, const std::string& net); + /* Set the default value for the net under a given pin constraint */ + void set_net_default_value(const PinConstraintId& pin_constraint, + const std::string& default_value); + public: /* Public invalidators/validators */ /* Show if the pin constraint id is a valid for data queries */ bool valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const; @@ -91,6 +116,16 @@ class PinConstraints { * - net() */ bool unmapped_net(const std::string& net) const; + + /* Check if default value is a valid one or not + * This is to check if the default value is constrained or not + */ + bool valid_net_default_value(const PinConstraintId& pin_constraint) const; + + /* Check if default value is a valid one or not + * This is to check if the default value is constrained or not + */ + bool valid_net_default_value(const std::string& net) const; private: /* Internal data */ /* Unique ids for each design constraint */ vtr::vector pin_constraint_ids_; @@ -100,6 +135,9 @@ class PinConstraints { /* Nets to constraint */ vtr::vector pin_constraint_nets_; + + /* Default value of the nets to constraint */ + vtr::vector pin_constraint_net_default_values_; }; #endif diff --git a/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp b/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp index b0c662da5..98527cb32 100644 --- a/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp +++ b/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp @@ -41,6 +41,14 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint, archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), "Fail to create pin constraint!\n"); } + + /* Set default value if defined */ + std::string default_value = get_attribute(xml_pin_constraint, "default_value", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(); + pin_constraints.set_net_default_value(pin_constraint_id, default_value); + if (!default_value.empty() && !pin_constraints.valid_net_default_value(pin_constraint_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), + "Invalid default value for pin constraints. Expect [0|1]!\n"); + } } /******************************************************************** diff --git a/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp b/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp index 80a664f3f..ef728be95 100644 --- a/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp +++ b/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp @@ -44,6 +44,7 @@ int write_xml_pin_constraint(std::fstream& fp, write_xml_attribute(fp, "pin", generate_xml_port_name(pin_constraints.pin(pin_constraint)).c_str()); write_xml_attribute(fp, "net", pin_constraints.net(pin_constraint).c_str()); + write_xml_attribute(fp, "default_value", pin_constraints.net_default_value_to_string(pin_constraint).c_str()); fp << "/>" << "\n"; diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 7194f208f..6be38f425 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -213,6 +213,10 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, if (1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))) { initial_value = 0; } + /* Pin constraints has the final decision on the default value */ + if (pin_constraints.valid_net_default_value(block_name)) { + initial_value = pin_constraints.net_default_value_to_int(block_name); + } fp << "initial" << std::endl; fp << "\tbegin" << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 47300ce1e..1e82b7e81 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1789,11 +1789,17 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp, continue; } + /* Pin constraints has the final decision on the default value */ + size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name))); + if (pin_constraints.valid_net_default_value(block_name)) { + initial_value = pin_constraints.net_default_value_to_int(block_name); + } + /* Connect stimuli to greset with an optional inversion, depending on the default value */ BasicPort reset_port(block_name, 1); print_verilog_wire_connection(fp, reset_port, BasicPort(TOP_TB_RESET_PORT_NAME, 1), - 1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))); + 1 == initial_value); } } From 0851075bc96fe9bd4116bf7e65f89aeeb90ff372 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 23:47:36 -0600 Subject: [PATCH 73/89] [Doc] Update documentation about the new feature in pin constraint file --- docs/source/manual/file_formats/pin_constraints_file.rst | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/file_formats/pin_constraints_file.rst b/docs/source/manual/file_formats/pin_constraints_file.rst index c2a71c596..a172396f1 100644 --- a/docs/source/manual/file_formats/pin_constraints_file.rst +++ b/docs/source/manual/file_formats/pin_constraints_file.rst @@ -10,7 +10,7 @@ An example of design constraints is shown as follows. .. code-block:: xml - + @@ -23,3 +23,9 @@ An example of design constraints is shown as follows. .. option:: net="" The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file. + +.. option:: default_value="" + + The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli. + + .. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration. From 43afaca17c0b406d3b58a347dd37677fd4b90ed0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 23:51:54 -0600 Subject: [PATCH 74/89] [Doc] Add more details about the new syntax --- docs/source/manual/file_formats/pin_constraints_file.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/manual/file_formats/pin_constraints_file.rst b/docs/source/manual/file_formats/pin_constraints_file.rst index a172396f1..063b27542 100644 --- a/docs/source/manual/file_formats/pin_constraints_file.rst +++ b/docs/source/manual/file_formats/pin_constraints_file.rst @@ -29,3 +29,5 @@ An example of design constraints is shown as follows. The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli. .. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration. + + .. note:: The default value in pin constraint file has a higher priority than the ``default_value`` syntax in the :ref:`circuit_library`. From 0b6a9b06f593b6eb5f29726a23147baad7b0c9ec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 10:39:07 -0600 Subject: [PATCH 75/89] [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality --- .../counter_128bit_async_reset/counter.v | 0 .../counter_128bit_async_reset/counter_tb.v | 0 .../counter_128bit_async_resetb/counter.v | 0 .../counter_128bit_async_resetb/counter_tb.v | 0 .../counter4bit_2clock.act | 0 .../counter4bit_2clock.blif | 0 .../counter_4bit_2clock}/counter4bit_2clock.v | 0 .../counter4bit_2clock_post_yosys.v | 0 .../counter4bit_2clock_tb.v | 0 .../counter_8bit_async_reset}/counter.v | 0 .../counter_8bit_async_reset}/counter_tb.v | 0 .../counter_8bit_async_resetb/counter.v | 25 +++++++++++++++++++ .../counter_8bit_async_resetb/counter_tb.v | 25 +++++++++++++++++++ .../counter_8bit_sync_reset}/counter.v | 0 .../counter_8bit_sync_reset}/counter_tb.v | 0 15 files changed, 50 insertions(+) rename openfpga_flow/benchmarks/micro_benchmark/{ => counters}/counter_128bit_async_reset/counter.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => counters}/counter_128bit_async_reset/counter_tb.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => counters}/counter_128bit_async_resetb/counter.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => counters}/counter_128bit_async_resetb/counter_tb.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock.act (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock.blif (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock_post_yosys.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock_tb.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter_async_reset => counters/counter_8bit_async_reset}/counter.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter_async_reset => counters/counter_8bit_async_reset}/counter_tb.v (100%) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v rename openfpga_flow/benchmarks/micro_benchmark/{counter => counters/counter_8bit_sync_reset}/counter.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter => counters/counter_8bit_sync_reset}/counter_tb.v (100%) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v new file mode 100644 index 000000000..3d929091d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + resetb, + result +); + + input clk; + input resetb; + output [7:0] result; + + reg [7:0] result; + + always @(posedge clk or negedge resetb) + begin + if (!resetb) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v new file mode 100644 index 000000000..8813aa0c4 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, resetb; + wire [7:0] result; + + counter DUT( + .clk(clk), + .resetb(resetb), + .result(result) + ); + + initial begin + #0 resetb = 1'b0; clk = 1'b0; + #100 resetb = 1'b1; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v From fd85f956c9d8ea46dd7b5d13c522ff6a4d5806ec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:08:39 -0600 Subject: [PATCH 76/89] [Arch] Update k4n4 arch with true multi-mode flip-flop --- .../k4_frac_N4_fracff_40nm_cc_openfpga.xml | 24 ++- .../k4_frac_N4_tileable_fracff_40nm.xml | 171 +++++++++++++++--- 2 files changed, 167 insertions(+), 28 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml index 5aca72a87..bc4e0de63 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - + @@ -220,20 +220,34 @@ - + - + + + + + + + + - + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index af701b3c9..ebd712620 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -7,11 +7,7 @@ with optionally registered outputs - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1 - Details on Modelling: - - Based on flagship k4_frac_N4_mem32K_40nm.xml architecture. - - Authors: Jason Luu, Jeff Goeders, Vaughn Betz + Authors: Xifan Tang --> + + + + + + + + + + - - + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -417,16 +483,75 @@ 261e-12 - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 477e5353447987281dda10144c8fcb5242203e2d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:13:03 -0600 Subject: [PATCH 77/89] [HDL] Added a multi-mode FF design with configurable asynchronous reset --- .../openfpga_cell_library/verilog/dff.v | 33 ++++++++++++++++--- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index c3a5e538e..2eb5765c9 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -246,9 +246,9 @@ endmodule //End Of Module //----------------------------------------------------- // Function : A multi-functional D-type flip-flop with // - asynchronous reset -// which can be switched between active-low and active hight -// - asynchronous set which can be switched -// which can be switched between active-low and active hight +// which can be switched between active-low and active high +// - asynchronous set +// which can be switched between active-low and active high //----------------------------------------------------- module MULTI_MODE_DFFSRQ ( input SET, // Set input @@ -259,8 +259,8 @@ module MULTI_MODE_DFFSRQ ( input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity ); -wire post_set = mode ? ~SET : SET; -wire post_reset = mode ? ~RST : RST; +wire post_set = mode[1] ? ~SET : SET; +wire post_reset = mode[0] ? ~RST : RST; DFFSRQ FF_CORE (.SET(post_set), .RST(post_rst), @@ -271,6 +271,29 @@ DFFSRQ FF_CORE (.SET(post_set), endmodule //End Of Module +//----------------------------------------------------- +// Function : A multi-functional D-type flip-flop with +// - asynchronous reset +// which can be switched between active-low and active high +//----------------------------------------------------- +module MULTI_MODE_DFFRQ ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity +); + +wire post_reset = mode ? ~RST : RST; + +DFFRQ FF_CORE (.RST(post_rst), + .CK(CK), + .D(D), + .Q(Q) + ); + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset From 02fd2a69b313fb7c84a248e4503e4a0b64459b07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:17:43 -0600 Subject: [PATCH 78/89] [Script] Add dff with active-low async reset to default yosys tech lib --- .../openfpga_yosys_techlib/openfpga_dff_map.v | 10 ++++++ .../openfpga_yosys_techlib/openfpga_dff_sim.v | 31 +++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v index 707d9c0e6..8c6c149c4 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -17,6 +17,16 @@ module \$_DFF_PP0_ (D, C, R, Q); dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); endmodule +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + // Async reset, enable module \$_DFFE_PP0P_ (D, C, E, R, Q); input D; diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v index d4798a906..12b9e8ec3 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v @@ -76,6 +76,37 @@ module dffre( endcase endmodule +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + (* abc9_flop, lib_whitebox *) module latchre ( output reg Q, From 5286f9ba255edce8343c4a448b7565fae817b5d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:39:00 -0600 Subject: [PATCH 79/89] [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking --- .../{pin_constraints.xml => pin_constraints_reset.xml} | 0 .../k4n4_fracff/config/pin_constraints_resetb.xml | 7 +++++++ .../basic_tests/k4_series/k4n4_fracff/config/task.conf | 7 ++++++- 3 files changed, 13 insertions(+), 1 deletion(-) rename openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/{pin_constraints.xml => pin_constraints_reset.xml} (100%) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml similarity index 100% rename from openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml rename to openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..cdef2ad86 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf index 07e326a1e..364f94ef5 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf @@ -28,13 +28,18 @@ yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter +bench0_pin_conf_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml + +bench1_top = counter +bench1_pin_conf_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From dcb89cb16b7d85efef01e7420faebfb791ab7bf0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:41:29 -0600 Subject: [PATCH 80/89] [Arch] Patch architecture due to missing mode bit definition --- .../k4_frac_N4_fracff_40nm_cc_openfpga.xml | 2 +- .../vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml index bc4e0de63..cd12856c5 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml @@ -220,7 +220,7 @@ - + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index ebd712620..5351486bc 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -40,6 +40,16 @@ + + + + + + + + + + From edd5be2cae572f45ff036b644d2ac184adc4bf6b Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 2 Jul 2021 12:51:34 -0600 Subject: [PATCH 81/89] [CI] Added testcase for benchmark variable --- openfpga_flow/scripts/run_fpga_task.py | 10 +++++++--- .../global_tile_4clock/config/task.conf | 3 ++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 66ac0f838..2fedb5cf6 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -271,9 +271,11 @@ def generate_each_task_actions(taskname): fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) + benchVariable = [] for eachKey, eachValue in SynthSection.items(): - eachKey = eachKey.replace(bech_name+"_","").upper() - CurrBenchPara[eachKey] = eachValue + if bech_name in eachKey: + eachKey = eachKey.replace(bech_name+"_", "").upper() + benchVariable = benchVariable+[f"--{eachKey}"] + [eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -335,7 +337,7 @@ def generate_each_task_actions(taskname): "bench": bench, "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, - "commands": command, + "commands": command + benchVariable, "finished": False, "status": False}) @@ -346,6 +348,8 @@ def generate_each_task_actions(taskname): # Make the directory name unique by including the benchmark index in the list. # This is because benchmarks may share the same top module names + + def get_flow_rundir(arch, top_module, flow_params=None): path = [ os.path.basename(arch).replace(".xml", ""), diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index e7cbcb5ab..679b8e6ac 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -20,7 +20,6 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml @@ -31,7 +30,9 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch [SYNTHESIS_PARAM] bench0_top = counter4bit_2clock +bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml bench1_top = and2_latch_2clock +bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From 6e6c3e9fa4269f023ff8e8571e50207ccd651b31 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:26:21 -0600 Subject: [PATCH 82/89] [Tool] Patch the critical bug in the use of signal polarity in pin constraints --- .../verilog_formal_random_top_testbench.cpp | 7 +++---- openfpga/src/fpga_verilog/verilog_testbench_utils.cpp | 10 ++++++++++ openfpga/src/fpga_verilog/verilog_testbench_utils.h | 1 + openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 7 +++---- 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 6be38f425..d27baccbd 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -105,6 +105,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, const std::string& reference_verilog_top_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); @@ -125,6 +126,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, prefix_to_remove, std::string(BENCHMARK_PORT_POSTFIX), atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -213,10 +215,6 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, if (1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))) { initial_value = 0; } - /* Pin constraints has the final decision on the default value */ - if (pin_constraints.valid_net_default_value(block_name)) { - initial_value = pin_constraints.net_default_value_to_int(block_name); - } fp << "initial" << std::endl; fp << "\tbegin" << std::endl; @@ -308,6 +306,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, if (!options.no_self_checking()) { print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx, netlist_annotation, + pin_constraints, options.explicit_port_mapping()); } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index bd530cc3e..01cdb0a22 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -69,6 +69,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, const std::string& output_port_postfix, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& use_explicit_port_map) { /* Validate the file stream */ valid_file_stream(fp); @@ -99,6 +100,15 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, if (true == use_explicit_port_map) { fp << "." << block_name << module_input_port_postfix << "("; } + + /* Polarity of some input may have to be inverted, as defined in pin constraints + * For example, the reset signal of the benchmark is active low + * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted) + * However, to ensure correct stimuli to the benchmark, we have to invert the signal + */ + if (LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { + fp << "~"; + } fp << block_name; if (true == use_explicit_port_map) { fp << ")"; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index f45452c6d..d06f267c9 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -38,6 +38,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, const std::string& output_port_postfix, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& use_explicit_port_map); void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 1e82b7e81..e4778c292 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -912,6 +912,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, const std::string& reference_verilog_top_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); @@ -932,6 +933,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, prefix_to_remove, std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -1789,11 +1791,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp, continue; } - /* Pin constraints has the final decision on the default value */ size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name))); - if (pin_constraints.valid_net_default_value(block_name)) { - initial_value = pin_constraints.net_default_value_to_int(block_name); - } /* Connect stimuli to greset with an optional inversion, depending on the default value */ BasicPort reset_port(block_name, 1); @@ -2004,6 +2002,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, circuit_name, atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); } From c67807868c76b988c876b0733c6d492f52472390 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 2 Jul 2021 15:26:39 -0600 Subject: [PATCH 83/89] [bugFix] Benchamrk variable declaration --- openfpga_flow/scripts/run_fpga_task.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 2fedb5cf6..9ae4d87c7 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -271,11 +271,11 @@ def generate_each_task_actions(taskname): fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) - benchVariable = [] + CurrBenchPara["benchVariable"] = [] for eachKey, eachValue in SynthSection.items(): if bech_name in eachKey: eachKey = eachKey.replace(bech_name+"_", "").upper() - benchVariable = benchVariable+[f"--{eachKey}"] + [eachValue] + CurrBenchPara["benchVariable"] += [eachKey,eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -337,7 +337,7 @@ def generate_each_task_actions(taskname): "bench": bench, "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, - "commands": command + benchVariable, + "commands": command + bench["benchVariable"], "finished": False, "status": False}) From 3cbe266c4412b319a08b309befbf8b065d3b09e3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:27:27 -0600 Subject: [PATCH 84/89] [Test] Bug fix on the test case for multi-mode FF and pin constraints --- .../tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf index 364f94ef5..2408323ed 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf @@ -19,7 +19,6 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml # Yosys script parameters yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -36,10 +35,10 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter -bench0_pin_conf_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml bench1_top = counter -bench1_pin_conf_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From e9d29e27e50d49269f515c2298312093d987092c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:32:30 -0600 Subject: [PATCH 85/89] [Tool] Bug fix --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 1 + openfpga/src/fpga_verilog/verilog_testbench_utils.cpp | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index d27baccbd..47fc6a13d 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -157,6 +157,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, std::vector(), std::string(FPGA_PORT_POSTFIX), atom_ctx, netlist_annotation, + PinConstraints(), explicit_port_mapping); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 01cdb0a22..3542cdcfc 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -106,7 +106,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted) * However, to ensure correct stimuli to the benchmark, we have to invert the signal */ - if (LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { + if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { fp << "~"; } fp << block_name; From 8baf60603a5aeeffe638b1de48b67653d703e3d8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:59:29 -0600 Subject: [PATCH 86/89] [Script] Patching the run_fpga_task.py on pin constraint files --- openfpga_flow/scripts/run_fpga_task.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 9ae4d87c7..7665cfb1b 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -275,7 +275,7 @@ def generate_each_task_actions(taskname): for eachKey, eachValue in SynthSection.items(): if bech_name in eachKey: eachKey = eachKey.replace(bech_name+"_", "").upper() - CurrBenchPara["benchVariable"] += [eachKey,eachValue] + CurrBenchPara["benchVariable"] += [f"--{eachKey}", eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist From 5a6874e9f173f613c237d525f63e0eebf8025e70 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 17:28:17 -0600 Subject: [PATCH 87/89] [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks --- .../counter4bit_2clock.act | 22 ------- .../counter4bit_2clock.blif | 48 --------------- .../counter4bit_2clock_post_yosys.v | 60 ------------------- ...ter4bit_2clock.v => counter_4bit_2clock.v} | 2 +- ...t_2clock_tb.v => counter_4bit_2clock_tb.v} | 6 +- 5 files changed, 4 insertions(+), 134 deletions(-) delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v rename openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/{counter4bit_2clock.v => counter_4bit_2clock.v} (85%) rename openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/{counter4bit_2clock_tb.v => counter_4bit_2clock_tb.v} (75%) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act deleted file mode 100644 index e0e56d449..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act +++ /dev/null @@ -1,22 +0,0 @@ -clk0 0.505000 0.204400 -rst0 0.491000 0.206000 -clk1 0.472000 0.204400 -rst1 0.501400 0.204600 -q1[0] 0.278800 0.557400 -q1[1] 0.240600 0.268800 -q1[2] 0.178200 0.120000 -q1[3] 0.098400 0.041600 -q0[0] 0.283400 0.566600 -q0[1] 0.246800 0.272000 -q0[2] 0.181000 0.122200 -q0[3] 0.093200 0.048800 -n34 0.178200 0.068356 -n38 0.098400 0.002698 -$abc$226$new_n22_ 0.880800 0.004943 -n42 0.283400 0.129291 -n46 0.246800 0.084119 -n50 0.181000 0.067113 -n54 0.093200 0.002644 -$abc$226$new_n27_ 0.883200 0.005398 -n26 0.278800 0.038636 -n30 0.240600 0.082416 diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif deleted file mode 100644 index 0ae3c95a7..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif +++ /dev/null @@ -1,48 +0,0 @@ -# Benchmark "counter4bit_2clock" written by ABC on Wed Jan 13 13:27:00 2021 -.model counter4bit_2clock -.inputs clk0 rst0 clk1 rst1 -.outputs q0[0] q0[1] q0[2] q0[3] q1[0] q1[1] \ -q1[2] q1[3] - -.latch n26 q1[0] re clk1 2 -.latch n30 q1[1] re clk1 2 -.latch n34 q1[2] re clk1 2 -.latch n38 q1[3] re clk1 2 -.latch n42 q0[0] re clk0 2 -.latch n46 q0[1] re clk0 2 -.latch n50 q0[2] re clk0 2 -.latch n54 q0[3] re clk0 2 - -.names q1[0] q1[1] rst1 q1[2] n34 --001 1 -0-01 1 -1100 1 -.names rst1 $abc$226$new_n22_ n38 -00 1 -.names q1[2] q1[0] q1[1] q1[3] $abc$226$new_n22_ ---00 1 --0-0 1 -0--0 1 -1111 1 -.names rst0 q0[0] n42 -00 1 -.names rst0 q0[1] q0[0] n46 -001 1 -010 1 -.names q0[1] q0[0] rst0 q0[2] n50 --001 1 -0-01 1 -1100 1 -.names rst0 $abc$226$new_n27_ n54 -00 1 -.names q0[2] q0[1] q0[0] q0[3] $abc$226$new_n27_ ---00 1 --0-0 1 -0--0 1 -1111 1 -.names q1[0] rst1 n26 -00 1 -.names rst1 q1[0] q1[1] n30 -001 1 -010 1 -.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v deleted file mode 100644 index 2b14fc540..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v +++ /dev/null @@ -1,60 +0,0 @@ -/* Generated by Yosys 0.9+2406 (git sha1 a0606e09, gcc 8.4.0 -fPIC -Os) */ - -module counter4bit_2clock(clk0, rst0, clk1, rst1, \q0[0] , \q0[1] , \q0[2] , \q0[3] , \q1[0] , \q1[1] , \q1[2] , \q1[3] ); - wire _00_; - wire _01_; - input clk0; - input clk1; - wire n26; - wire n30; - wire n34; - wire n38; - wire n42; - wire n46; - wire n50; - wire n54; - output \q0[0] ; - reg \q0[0] ; - output \q0[1] ; - reg \q0[1] ; - output \q0[2] ; - reg \q0[2] ; - output \q0[3] ; - reg \q0[3] ; - output \q1[0] ; - reg \q1[0] ; - output \q1[1] ; - reg \q1[1] ; - output \q1[2] ; - reg \q1[2] ; - output \q1[3] ; - reg \q1[3] ; - input rst0; - input rst1; - always @(posedge clk1) - \q1[0] <= n26; - always @(posedge clk1) - \q1[1] <= n30; - always @(posedge clk1) - \q1[2] <= n34; - always @(posedge clk1) - \q1[3] <= n38; - always @(posedge clk1) - \q0[0] <= n42; - always @(posedge clk1) - \q0[1] <= n46; - always @(posedge clk1) - \q0[2] <= n50; - always @(posedge clk1) - \q0[3] <= n54; - assign n38 = 4'h1 >> { _00_, rst1 }; - assign _00_ = 16'h807f >> { \q1[3] , \q1[1] , \q1[0] , \q1[2] }; - assign n42 = 4'h1 >> { \q0[0] , rst0 }; - assign n46 = 8'h14 >> { \q0[0] , \q0[1] , rst0 }; - assign n50 = 16'h0708 >> { \q0[2] , rst0, \q0[0] , \q0[1] }; - assign n54 = 4'h1 >> { _01_, rst0 }; - assign _01_ = 16'h807f >> { \q0[3] , \q0[0] , \q0[1] , \q0[2] }; - assign n26 = 4'h1 >> { rst1, \q1[0] }; - assign n30 = 8'h14 >> { \q1[1] , \q1[0] , rst1 }; - assign n34 = 16'h0708 >> { \q1[2] , rst1, \q1[1] , \q1[0] }; -endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v similarity index 85% rename from openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v index 93f7dc07b..c1b5f2ee6 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v @@ -1,4 +1,4 @@ -module counter4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); +module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); input clk0; input rst0; diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v similarity index 75% rename from openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v index 880b99088..9150f55b9 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v @@ -1,4 +1,4 @@ -module counter4bit_2clock_tb; +module counter_4bit_2clock_tb; reg clk0, rst0; wire [3:0] q0; @@ -6,12 +6,12 @@ module counter4bit_2clock_tb; reg clk1, rst1; wire [3:0] q1; - counter_2clock C_1( + counter_4bit_2clock C_1( clk0, q0, rst0); - counter_2clock C_1( + counter_4bit_2clock C_1( clk1, q1, rst1); From 64dcdaec6111fe5c68007e234ac16eeccaf0e5f5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 17:29:13 -0600 Subject: [PATCH 88/89] [Test] Update all the tasks that use counter benchmark --- .../global_tile_ports/global_tile_4clock/config/task.conf | 4 ++-- .../tasks/benchmark_sweep/counter/config/task.conf | 8 ++++---- .../implicit_verilog/config/task.conf | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index 679b8e6ac..feb6dfbaa 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -25,11 +25,11 @@ openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/task arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v [SYNTHESIS_PARAM] -bench0_top = counter4bit_2clock +bench0_top = counter_4bit_2clock bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml bench1_top = and2_latch_2clock bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index eb0079516..6fefdb16d 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -34,10 +34,10 @@ vpr_route_chan_width=50 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v -bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf index f7f2a8b06..df4d8b854 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf @@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=none arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v [SYNTHESIS_PARAM] bench0_top = counter From 9f03ecb160354fa8251e8502ea6041653570e556 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 17:57:39 -0600 Subject: [PATCH 89/89] [Test] Patch test case due to the changes in counter benchmarks --- .../implicit_verilog_default_nettype_wire/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf index 898412cd2..568ded5e4 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf @@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=wire arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v [SYNTHESIS_PARAM] bench0_top = counter