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Code Issues Projects Releases Wiki Activity

comment out desings that utilize local async reset/preset

This commit is contained in:
Tarachand Pagarani 2021-03-09 10:37:06 -08:00
parent c4b83aeaa9
commit 7f4c20ff33
1 changed files with 6 additions and 3 deletions
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9
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
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@ -33,7 +33,8 @@ bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/c
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v #cavlc_top requires async reset/preset
#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v
# counter120bitx5 requires 5 clocks # counter120bitx5 requires 5 clocks
#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v #bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v
@ -41,8 +42,10 @@ bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_
bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v
bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v #i2c_master_top requires async reset/preset
bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v #bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v
#iir requires async reset/preset
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v
bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
# sdc_controller requires 4 clocks # sdc_controller requires 4 clocks