From 7f4c20ff33a3b201b2d8386bf07e25981235381e Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Tue, 9 Mar 2021 10:37:06 -0800 Subject: [PATCH] comment out desings that utilize local async reset/preset --- .../tasks/quicklogic_tests/flow_test/config/task.conf | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index d58a27fbd..43e7649b8 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -33,7 +33,8 @@ bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/c bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v -bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v +#cavlc_top requires async reset/preset +#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v # counter120bitx5 requires 5 clocks #bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v @@ -41,8 +42,10 @@ bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_ bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v -bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v -bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v +#i2c_master_top requires async reset/preset +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v +#iir requires async reset/preset +#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v # sdc_controller requires 4 clocks