Merge pull request #873 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-4834fd0
Bump vtr-verilog-to-routing from `ff83963` to `4834fd0`
This commit is contained in:
tangxifan
GitHub
commit
7e60890c9c
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@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
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initial begin
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clk[0] <= 1'b0;
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while(1) begin
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#0.5744515657
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#0.7626540661
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clk[0] <= !clk[0];
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end
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end
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@ -109,7 +109,7 @@ initial begin
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$timeformat(-9, 2, "ns", 20);
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$display("Simulation start");
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// ----- Can be changed by the user for his/her need -------
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#8.042322159
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#10.6771574
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if(nb_error == 0) begin
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$display("Simulation Succeed");
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end else begin
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@ -9,14 +9,14 @@
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##################################################
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# Create clock
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##################################################
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create_clock clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10}
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create_clock clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10}
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##################################################
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# Create input and output delays for used I/Os
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##################################################
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set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[26]
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set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[25]
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set_output_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[11]
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set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[27]
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set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[15]
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set_output_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[12]
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##################################################
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# Disable timing for unused I/Os
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@ -32,10 +32,9 @@ set_disable_timing gfpga_pad_GPIO_PAD[7]
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set_disable_timing gfpga_pad_GPIO_PAD[8]
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set_disable_timing gfpga_pad_GPIO_PAD[9]
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set_disable_timing gfpga_pad_GPIO_PAD[10]
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set_disable_timing gfpga_pad_GPIO_PAD[12]
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set_disable_timing gfpga_pad_GPIO_PAD[11]
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set_disable_timing gfpga_pad_GPIO_PAD[13]
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set_disable_timing gfpga_pad_GPIO_PAD[14]
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set_disable_timing gfpga_pad_GPIO_PAD[15]
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set_disable_timing gfpga_pad_GPIO_PAD[16]
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set_disable_timing gfpga_pad_GPIO_PAD[17]
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set_disable_timing gfpga_pad_GPIO_PAD[18]
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@ -45,7 +44,8 @@ set_disable_timing gfpga_pad_GPIO_PAD[21]
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set_disable_timing gfpga_pad_GPIO_PAD[22]
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set_disable_timing gfpga_pad_GPIO_PAD[23]
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set_disable_timing gfpga_pad_GPIO_PAD[24]
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set_disable_timing gfpga_pad_GPIO_PAD[27]
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set_disable_timing gfpga_pad_GPIO_PAD[25]
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set_disable_timing gfpga_pad_GPIO_PAD[26]
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set_disable_timing gfpga_pad_GPIO_PAD[28]
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set_disable_timing gfpga_pad_GPIO_PAD[29]
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set_disable_timing gfpga_pad_GPIO_PAD[30]
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@ -156,7 +156,6 @@ set_disable_timing cbx_1__0_/chanx_left_in[7]
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set_disable_timing cbx_1__0_/chanx_right_in[7]
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set_disable_timing cbx_1__0_/chanx_left_in[8]
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set_disable_timing cbx_1__0_/chanx_right_in[8]
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set_disable_timing cbx_1__0_/chanx_left_in[9]
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set_disable_timing cbx_1__0_/chanx_right_in[9]
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set_disable_timing cbx_1__0_/chanx_left_in[10]
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set_disable_timing cbx_1__0_/chanx_right_in[10]
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@ -181,7 +180,6 @@ set_disable_timing cbx_1__0_/chanx_left_out[7]
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set_disable_timing cbx_1__0_/chanx_right_out[7]
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set_disable_timing cbx_1__0_/chanx_left_out[8]
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set_disable_timing cbx_1__0_/chanx_right_out[8]
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set_disable_timing cbx_1__0_/chanx_left_out[9]
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set_disable_timing cbx_1__0_/chanx_right_out[9]
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set_disable_timing cbx_1__0_/chanx_left_out[10]
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set_disable_timing cbx_1__0_/chanx_right_out[10]
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@ -274,7 +272,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[1]
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set_disable_timing cbx_1__1_/chanx_left_in[2]
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set_disable_timing cbx_1__1_/chanx_right_in[2]
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set_disable_timing cbx_1__1_/chanx_left_in[3]
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set_disable_timing cbx_1__1_/chanx_right_in[3]
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set_disable_timing cbx_1__1_/chanx_left_in[4]
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set_disable_timing cbx_1__1_/chanx_right_in[4]
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set_disable_timing cbx_1__1_/chanx_left_in[5]
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@ -283,7 +280,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[6]
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set_disable_timing cbx_1__1_/chanx_right_in[6]
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set_disable_timing cbx_1__1_/chanx_left_in[7]
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set_disable_timing cbx_1__1_/chanx_right_in[7]
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set_disable_timing cbx_1__1_/chanx_left_in[8]
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set_disable_timing cbx_1__1_/chanx_right_in[8]
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set_disable_timing cbx_1__1_/chanx_left_in[9]
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set_disable_timing cbx_1__1_/chanx_right_in[9]
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@ -299,7 +295,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[1]
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set_disable_timing cbx_1__1_/chanx_left_out[2]
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set_disable_timing cbx_1__1_/chanx_right_out[2]
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set_disable_timing cbx_1__1_/chanx_left_out[3]
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set_disable_timing cbx_1__1_/chanx_right_out[3]
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set_disable_timing cbx_1__1_/chanx_left_out[4]
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set_disable_timing cbx_1__1_/chanx_right_out[4]
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set_disable_timing cbx_1__1_/chanx_left_out[5]
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@ -308,7 +303,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[6]
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set_disable_timing cbx_1__1_/chanx_right_out[6]
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set_disable_timing cbx_1__1_/chanx_left_out[7]
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set_disable_timing cbx_1__1_/chanx_right_out[7]
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set_disable_timing cbx_1__1_/chanx_left_out[8]
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set_disable_timing cbx_1__1_/chanx_right_out[8]
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set_disable_timing cbx_1__1_/chanx_left_out[9]
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set_disable_timing cbx_1__1_/chanx_right_out[9]
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@ -326,7 +320,6 @@ set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_out
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0]
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0]
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set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0]
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set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0]
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set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0]
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set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1]
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@ -374,7 +367,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[4]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[4]
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set_disable_timing cbx_1__1_/mux_top_ipin_0/in[2]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[5]
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set_disable_timing cbx_1__1_/mux_top_ipin_0/in[5]
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set_disable_timing cbx_1__1_/mux_top_ipin_1/in[3]
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set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[4]
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set_disable_timing cbx_1__1_/mux_top_ipin_0/in[4]
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@ -398,11 +390,12 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[4]
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##################################################
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# Disable timing for Connection block cby_0__1_
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##################################################
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set_disable_timing cby_0__1_/chany_bottom_in[0]
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set_disable_timing cby_0__1_/chany_top_in[0]
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set_disable_timing cby_0__1_/chany_bottom_in[1]
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set_disable_timing cby_0__1_/chany_top_in[1]
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set_disable_timing cby_0__1_/chany_bottom_in[2]
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set_disable_timing cby_0__1_/chany_top_in[2]
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set_disable_timing cby_0__1_/chany_bottom_in[3]
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set_disable_timing cby_0__1_/chany_top_in[3]
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set_disable_timing cby_0__1_/chany_bottom_in[4]
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set_disable_timing cby_0__1_/chany_top_in[4]
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@ -413,7 +406,6 @@ set_disable_timing cby_0__1_/chany_top_in[6]
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set_disable_timing cby_0__1_/chany_bottom_in[7]
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set_disable_timing cby_0__1_/chany_top_in[7]
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set_disable_timing cby_0__1_/chany_bottom_in[8]
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set_disable_timing cby_0__1_/chany_top_in[8]
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set_disable_timing cby_0__1_/chany_bottom_in[9]
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set_disable_timing cby_0__1_/chany_top_in[9]
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set_disable_timing cby_0__1_/chany_bottom_in[10]
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@ -421,11 +413,12 @@ set_disable_timing cby_0__1_/chany_bottom_in[11]
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set_disable_timing cby_0__1_/chany_top_in[11]
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set_disable_timing cby_0__1_/chany_bottom_in[12]
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set_disable_timing cby_0__1_/chany_top_in[12]
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set_disable_timing cby_0__1_/chany_bottom_out[0]
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set_disable_timing cby_0__1_/chany_top_out[0]
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set_disable_timing cby_0__1_/chany_bottom_out[1]
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set_disable_timing cby_0__1_/chany_top_out[1]
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set_disable_timing cby_0__1_/chany_bottom_out[2]
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set_disable_timing cby_0__1_/chany_top_out[2]
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set_disable_timing cby_0__1_/chany_bottom_out[3]
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set_disable_timing cby_0__1_/chany_top_out[3]
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set_disable_timing cby_0__1_/chany_bottom_out[4]
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set_disable_timing cby_0__1_/chany_top_out[4]
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@ -436,7 +429,6 @@ set_disable_timing cby_0__1_/chany_top_out[6]
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set_disable_timing cby_0__1_/chany_bottom_out[7]
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set_disable_timing cby_0__1_/chany_top_out[7]
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set_disable_timing cby_0__1_/chany_bottom_out[8]
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set_disable_timing cby_0__1_/chany_top_out[8]
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set_disable_timing cby_0__1_/chany_bottom_out[9]
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set_disable_timing cby_0__1_/chany_top_out[9]
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set_disable_timing cby_0__1_/chany_bottom_out[10]
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@ -444,6 +436,8 @@ set_disable_timing cby_0__1_/chany_bottom_out[11]
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set_disable_timing cby_0__1_/chany_top_out[11]
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set_disable_timing cby_0__1_/chany_bottom_out[12]
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set_disable_timing cby_0__1_/chany_top_out[12]
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set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0]
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set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0]
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@ -452,11 +446,13 @@ set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_out
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0]
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set_disable_timing cby_0__1_/mux_left_ipin_0/in[1]
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set_disable_timing cby_0__1_/mux_left_ipin_1/in[1]
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set_disable_timing cby_0__1_/mux_right_ipin_5/in[1]
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set_disable_timing cby_0__1_/mux_left_ipin_0/in[0]
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set_disable_timing cby_0__1_/mux_left_ipin_1/in[0]
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set_disable_timing cby_0__1_/mux_right_ipin_5/in[0]
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set_disable_timing cby_0__1_/mux_left_ipin_1/in[3]
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set_disable_timing cby_0__1_/mux_right_ipin_0/in[1]
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set_disable_timing cby_0__1_/mux_right_ipin_6/in[1]
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set_disable_timing cby_0__1_/mux_left_ipin_1/in[2]
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@ -514,12 +510,10 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4]
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# Disable timing for Connection block cby_1__1_
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##################################################
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set_disable_timing cby_1__1_/chany_top_in[0]
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set_disable_timing cby_1__1_/chany_bottom_in[1]
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set_disable_timing cby_1__1_/chany_top_in[1]
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set_disable_timing cby_1__1_/chany_top_in[2]
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set_disable_timing cby_1__1_/chany_bottom_in[3]
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set_disable_timing cby_1__1_/chany_top_in[3]
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set_disable_timing cby_1__1_/chany_bottom_in[4]
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set_disable_timing cby_1__1_/chany_top_in[4]
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set_disable_timing cby_1__1_/chany_bottom_in[5]
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set_disable_timing cby_1__1_/chany_top_in[5]
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@ -538,12 +532,10 @@ set_disable_timing cby_1__1_/chany_top_in[11]
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set_disable_timing cby_1__1_/chany_bottom_in[12]
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set_disable_timing cby_1__1_/chany_top_in[12]
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set_disable_timing cby_1__1_/chany_top_out[0]
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set_disable_timing cby_1__1_/chany_bottom_out[1]
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set_disable_timing cby_1__1_/chany_top_out[1]
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set_disable_timing cby_1__1_/chany_top_out[2]
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set_disable_timing cby_1__1_/chany_bottom_out[3]
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set_disable_timing cby_1__1_/chany_top_out[3]
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set_disable_timing cby_1__1_/chany_bottom_out[4]
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set_disable_timing cby_1__1_/chany_top_out[4]
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set_disable_timing cby_1__1_/chany_bottom_out[5]
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set_disable_timing cby_1__1_/chany_top_out[5]
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@ -564,11 +556,10 @@ set_disable_timing cby_1__1_/chany_top_out[12]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0]
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set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0]
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set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0]
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set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0]
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set_disable_timing cby_1__1_/mux_left_ipin_0/in[1]
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@ -579,11 +570,11 @@ set_disable_timing cby_1__1_/mux_left_ipin_1/in[0]
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set_disable_timing cby_1__1_/mux_left_ipin_7/in[0]
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set_disable_timing cby_1__1_/mux_left_ipin_1/in[3]
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set_disable_timing cby_1__1_/mux_left_ipin_2/in[1]
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set_disable_timing cby_1__1_/mux_right_ipin_0/in[1]
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set_disable_timing cby_1__1_/mux_left_ipin_1/in[2]
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set_disable_timing cby_1__1_/mux_left_ipin_2/in[0]
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set_disable_timing cby_1__1_/mux_right_ipin_0/in[0]
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set_disable_timing cby_1__1_/mux_left_ipin_2/in[3]
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set_disable_timing cby_1__1_/mux_left_ipin_3/in[1]
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set_disable_timing cby_1__1_/mux_right_ipin_1/in[1]
|
||||
set_disable_timing cby_1__1_/mux_left_ipin_2/in[2]
|
||||
set_disable_timing cby_1__1_/mux_left_ipin_3/in[0]
|
||||
|
|
@ -594,7 +585,6 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1]
|
|||
set_disable_timing cby_1__1_/mux_left_ipin_3/in[2]
|
||||
set_disable_timing cby_1__1_/mux_left_ipin_4/in[0]
|
||||
set_disable_timing cby_1__1_/mux_right_ipin_2/in[0]
|
||||
set_disable_timing cby_1__1_/mux_left_ipin_4/in[3]
|
||||
set_disable_timing cby_1__1_/mux_left_ipin_5/in[1]
|
||||
set_disable_timing cby_1__1_/mux_left_ipin_4/in[2]
|
||||
set_disable_timing cby_1__1_/mux_left_ipin_5/in[0]
|
||||
|
|
@ -639,11 +629,12 @@ set_disable_timing cby_1__1_/mux_left_ipin_6/in[4]
|
|||
##################################################
|
||||
# Disable timing for Switch block sb_0__0_
|
||||
##################################################
|
||||
set_disable_timing sb_0__0_/chany_top_out[0]
|
||||
set_disable_timing sb_0__0_/chany_top_in[0]
|
||||
set_disable_timing sb_0__0_/chany_top_out[1]
|
||||
set_disable_timing sb_0__0_/chany_top_in[1]
|
||||
set_disable_timing sb_0__0_/chany_top_out[2]
|
||||
set_disable_timing sb_0__0_/chany_top_in[2]
|
||||
set_disable_timing sb_0__0_/chany_top_out[3]
|
||||
set_disable_timing sb_0__0_/chany_top_in[3]
|
||||
set_disable_timing sb_0__0_/chany_top_out[4]
|
||||
set_disable_timing sb_0__0_/chany_top_in[4]
|
||||
|
|
@ -654,7 +645,6 @@ set_disable_timing sb_0__0_/chany_top_in[6]
|
|||
set_disable_timing sb_0__0_/chany_top_out[7]
|
||||
set_disable_timing sb_0__0_/chany_top_in[7]
|
||||
set_disable_timing sb_0__0_/chany_top_out[8]
|
||||
set_disable_timing sb_0__0_/chany_top_in[8]
|
||||
set_disable_timing sb_0__0_/chany_top_out[9]
|
||||
set_disable_timing sb_0__0_/chany_top_in[9]
|
||||
set_disable_timing sb_0__0_/chany_top_out[10]
|
||||
|
|
@ -680,7 +670,6 @@ set_disable_timing sb_0__0_/chanx_right_out[7]
|
|||
set_disable_timing sb_0__0_/chanx_right_in[7]
|
||||
set_disable_timing sb_0__0_/chanx_right_out[8]
|
||||
set_disable_timing sb_0__0_/chanx_right_in[8]
|
||||
set_disable_timing sb_0__0_/chanx_right_out[9]
|
||||
set_disable_timing sb_0__0_/chanx_right_in[9]
|
||||
set_disable_timing sb_0__0_/chanx_right_out[10]
|
||||
set_disable_timing sb_0__0_/chanx_right_in[10]
|
||||
|
|
@ -688,7 +677,8 @@ set_disable_timing sb_0__0_/chanx_right_in[11]
|
|||
set_disable_timing sb_0__0_/chanx_right_out[12]
|
||||
set_disable_timing sb_0__0_/chanx_right_in[12]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0]
|
||||
|
|
@ -706,12 +696,13 @@ set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pi
|
|||
set_disable_timing sb_0__0_/mux_top_track_0/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_12/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_24/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_0/in[1]
|
||||
set_disable_timing sb_0__0_/mux_top_track_2/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_14/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_2/in[1]
|
||||
set_disable_timing sb_0__0_/mux_top_track_4/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_16/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_4/in[1]
|
||||
set_disable_timing sb_0__0_/mux_top_track_6/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_18/in[0]
|
||||
set_disable_timing sb_0__0_/mux_top_track_6/in[1]
|
||||
set_disable_timing sb_0__0_/mux_top_track_8/in[0]
|
||||
|
|
@ -761,7 +752,6 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0]
|
|||
set_disable_timing sb_0__0_/mux_right_track_12/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_14/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_16/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_18/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_20/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_24/in[0]
|
||||
set_disable_timing sb_0__0_/mux_right_track_0/in[0]
|
||||
|
|
@ -787,7 +777,6 @@ set_disable_timing sb_0__1_/chanx_right_out[1]
|
|||
set_disable_timing sb_0__1_/chanx_right_out[2]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[2]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[3]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[3]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[4]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[4]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[5]
|
||||
|
|
@ -796,7 +785,6 @@ set_disable_timing sb_0__1_/chanx_right_out[6]
|
|||
set_disable_timing sb_0__1_/chanx_right_in[6]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[7]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[7]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[8]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[8]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[9]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[9]
|
||||
|
|
@ -806,11 +794,12 @@ set_disable_timing sb_0__1_/chanx_right_out[11]
|
|||
set_disable_timing sb_0__1_/chanx_right_in[11]
|
||||
set_disable_timing sb_0__1_/chanx_right_out[12]
|
||||
set_disable_timing sb_0__1_/chanx_right_in[12]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[0]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[0]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[1]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[1]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[2]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[2]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[3]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[3]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[4]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[4]
|
||||
|
|
@ -821,7 +810,6 @@ set_disable_timing sb_0__1_/chany_bottom_out[6]
|
|||
set_disable_timing sb_0__1_/chany_bottom_in[7]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[7]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[8]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[8]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[9]
|
||||
set_disable_timing sb_0__1_/chany_bottom_out[9]
|
||||
set_disable_timing sb_0__1_/chany_bottom_in[10]
|
||||
|
|
@ -840,7 +828,8 @@ set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pi
|
|||
set_disable_timing sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
|
||||
set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
|
||||
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0]
|
||||
|
|
@ -897,7 +886,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_15/in[3]
|
|||
set_disable_timing sb_0__1_/mux_bottom_track_17/in[2]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_23/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_19/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_17/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_15/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_13/in[0]
|
||||
set_disable_timing sb_0__1_/mux_bottom_track_11/in[0]
|
||||
|
|
@ -910,7 +898,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_25/in[0]
|
|||
set_disable_timing sb_0__1_/mux_right_track_22/in[1]
|
||||
set_disable_timing sb_0__1_/mux_right_track_20/in[1]
|
||||
set_disable_timing sb_0__1_/mux_right_track_18/in[1]
|
||||
set_disable_timing sb_0__1_/mux_right_track_16/in[2]
|
||||
set_disable_timing sb_0__1_/mux_right_track_14/in[2]
|
||||
set_disable_timing sb_0__1_/mux_right_track_12/in[3]
|
||||
set_disable_timing sb_0__1_/mux_right_track_10/in[2]
|
||||
|
|
@ -924,12 +911,10 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2]
|
|||
# Disable timing for Switch block sb_1__0_
|
||||
##################################################
|
||||
set_disable_timing sb_1__0_/chany_top_in[0]
|
||||
set_disable_timing sb_1__0_/chany_top_out[1]
|
||||
set_disable_timing sb_1__0_/chany_top_in[1]
|
||||
set_disable_timing sb_1__0_/chany_top_in[2]
|
||||
set_disable_timing sb_1__0_/chany_top_out[3]
|
||||
set_disable_timing sb_1__0_/chany_top_in[3]
|
||||
set_disable_timing sb_1__0_/chany_top_out[4]
|
||||
set_disable_timing sb_1__0_/chany_top_in[4]
|
||||
set_disable_timing sb_1__0_/chany_top_out[5]
|
||||
set_disable_timing sb_1__0_/chany_top_in[5]
|
||||
|
|
@ -965,7 +950,6 @@ set_disable_timing sb_1__0_/chanx_left_in[7]
|
|||
set_disable_timing sb_1__0_/chanx_left_out[7]
|
||||
set_disable_timing sb_1__0_/chanx_left_in[8]
|
||||
set_disable_timing sb_1__0_/chanx_left_out[8]
|
||||
set_disable_timing sb_1__0_/chanx_left_in[9]
|
||||
set_disable_timing sb_1__0_/chanx_left_out[9]
|
||||
set_disable_timing sb_1__0_/chanx_left_in[10]
|
||||
set_disable_timing sb_1__0_/chanx_left_out[10]
|
||||
|
|
@ -979,7 +963,6 @@ set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_
|
|||
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0]
|
||||
set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
|
|
@ -1010,7 +993,6 @@ set_disable_timing sb_1__0_/mux_top_track_24/in[0]
|
|||
set_disable_timing sb_1__0_/mux_top_track_0/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_12/in[1]
|
||||
set_disable_timing sb_1__0_/mux_top_track_14/in[1]
|
||||
set_disable_timing sb_1__0_/mux_top_track_2/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_14/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_16/in[1]
|
||||
set_disable_timing sb_1__0_/mux_left_track_1/in[1]
|
||||
|
|
@ -1062,19 +1044,16 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2]
|
|||
set_disable_timing sb_1__0_/mux_top_track_14/in[3]
|
||||
set_disable_timing sb_1__0_/mux_top_track_12/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_10/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_8/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_6/in[2]
|
||||
set_disable_timing sb_1__0_/mux_top_track_2/in[3]
|
||||
##################################################
|
||||
# Disable timing for Switch block sb_1__1_
|
||||
##################################################
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[0]
|
||||
set_disable_timing sb_1__1_/chany_bottom_in[1]
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[1]
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[2]
|
||||
set_disable_timing sb_1__1_/chany_bottom_in[3]
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[3]
|
||||
set_disable_timing sb_1__1_/chany_bottom_in[4]
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[4]
|
||||
set_disable_timing sb_1__1_/chany_bottom_in[5]
|
||||
set_disable_timing sb_1__1_/chany_bottom_out[5]
|
||||
|
|
@ -1098,7 +1077,6 @@ set_disable_timing sb_1__1_/chanx_left_in[1]
|
|||
set_disable_timing sb_1__1_/chanx_left_in[2]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[2]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[3]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[3]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[4]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[4]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[5]
|
||||
|
|
@ -1107,7 +1085,6 @@ set_disable_timing sb_1__1_/chanx_left_in[6]
|
|||
set_disable_timing sb_1__1_/chanx_left_out[6]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[7]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[7]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[8]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[8]
|
||||
set_disable_timing sb_1__1_/chanx_left_in[9]
|
||||
set_disable_timing sb_1__1_/chanx_left_out[9]
|
||||
|
|
@ -1124,7 +1101,6 @@ set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__p
|
|||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
|
||||
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
|
||||
|
|
@ -1185,7 +1161,6 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3]
|
|||
set_disable_timing sb_1__1_/mux_left_track_15/in[2]
|
||||
set_disable_timing sb_1__1_/mux_left_track_17/in[2]
|
||||
set_disable_timing sb_1__1_/mux_left_track_5/in[0]
|
||||
set_disable_timing sb_1__1_/mux_left_track_7/in[0]
|
||||
set_disable_timing sb_1__1_/mux_left_track_9/in[0]
|
||||
set_disable_timing sb_1__1_/mux_left_track_11/in[0]
|
||||
set_disable_timing sb_1__1_/mux_left_track_13/in[0]
|
||||
|
|
@ -1218,12 +1193,12 @@ set_disable_timing sb_1__1_/mux_bottom_track_23/in[1]
|
|||
#######################################
|
||||
# Disable unused pins for pb_graph_node clb[0]
|
||||
#######################################
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[0]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[1]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[3]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[7]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[9]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0]
|
||||
|
|
@ -1234,8 +1209,8 @@ set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_clk[0]
|
|||
# Disable unused mux_inputs for pb_graph_node clb[0]
|
||||
#######################################
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5]
|
||||
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6]
|
||||
|
|
@ -1564,31 +1539,31 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/*
|
|||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[2][1][3]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/io_inpad[0]
|
||||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc_0_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
|
||||
#######################################
|
||||
# Disable Timing for unused grid[2][1][4]
|
||||
# Disable Timing for unused grid[2][1][3]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/*
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/*
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/*
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[2][1][4]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0]
|
||||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
|
||||
#######################################
|
||||
# Disable Timing for unused grid[2][1][5]
|
||||
#######################################
|
||||
|
|
@ -1612,16 +1587,20 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/*
|
|||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused grid[2][1][7]
|
||||
# Disable Timing for unused resources in grid[2][1][7]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/*
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/io_outpad[0]
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/*
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7//direct_interc_1_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
|
||||
#######################################
|
||||
# Disable Timing for grid[1][0]
|
||||
#######################################
|
||||
|
|
@ -1728,46 +1707,42 @@ set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/*
|
|||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[0][1][1]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/io_outpad[0]
|
||||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1//direct_interc_1_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[0][1][2]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/io_outpad[0]
|
||||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2//direct_interc_1_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
|
||||
#######################################
|
||||
# Disable Timing for unused grid[0][1][3]
|
||||
# Disable Timing for unused grid[0][1][1]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/*
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/*
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused grid[0][1][2]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/*
|
||||
#######################################
|
||||
# Disable all the ports for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
|
||||
#######################################
|
||||
# Disable Timing for unused resources in grid[0][1][3]
|
||||
#######################################
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/io_outpad[0]
|
||||
#######################################
|
||||
# Disable unused mux_inputs for pb_graph_node io[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3//direct_interc_1_/in[0]
|
||||
#######################################
|
||||
# Disable unused pins for pb_graph_node iopad[0]
|
||||
#######################################
|
||||
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
|
||||
#######################################
|
||||
# Disable Timing for unused grid[0][1][4]
|
||||
#######################################
|
||||
|
|
|
|||
|
|
@ -42,14 +42,14 @@ wire [0:0] clk_fm;
|
|||
// ----- End Connect Global ports of FPGA top module -----
|
||||
|
||||
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[26] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[26] = a[0];
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[27] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[27] = a[0];
|
||||
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[25] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[25] = b[0];
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[15] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[15] = b[0];
|
||||
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[11];
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[12];
|
||||
|
||||
// ----- Wire unused FPGA I/Os to constants -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
|
||||
|
|
@ -63,10 +63,9 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0;
|
||||
|
|
@ -76,7 +75,8 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0;
|
||||
|
|
@ -125,14 +125,14 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0111;
|
||||
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -155,10 +155,10 @@ initial begin
|
|||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -197,14 +197,14 @@ initial begin
|
|||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = 3'b011;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = 3'b100;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -241,8 +241,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}};
|
||||
|
|
@ -265,8 +265,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -291,8 +291,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}};
|
||||
|
|
@ -303,14 +303,14 @@ initial begin
|
|||
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -385,8 +385,8 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -443,16 +443,16 @@ initial begin
|
|||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = 3'b110;
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = 3'b001;
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = 3'b101;
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = 3'b010;
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -475,18 +475,18 @@ initial begin
|
|||
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101;
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010;
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
// Bitstream width (LSB -> MSB): 1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -14,9 +14,9 @@
|
|||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -143,12 +143,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -159,9 +156,8 @@
|
|||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -261,6 +257,9 @@
|
|||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
@ -270,39 +269,6 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -336,32 +302,10 @@
|
|||
0
|
||||
0
|
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@ -405,80 +349,136 @@
|
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0
|
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1
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1
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1
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1
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1
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1
|
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1
|
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1
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0
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0
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1
|
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1
|
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1
|
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1
|
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1
|
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1
|
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1
|
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1
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
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1
|
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1
|
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0
|
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0
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0
|
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0
|
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0
|
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0
|
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0
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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|
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0
|
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0
|
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|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
|
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0
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1
|
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1
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0
|
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0
|
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1
|
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1
|
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0
|
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|
|
@ -515,7 +515,6 @@
|
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1
|
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1
|
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1
|
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1
|
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0
|
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1
|
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1
|
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|
|
@ -528,3 +527,4 @@
|
|||
1
|
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1
|
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1
|
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1
|
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|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
</bit>
|
||||
<bit id="525" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
</bit>
|
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<bit id="524" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
<bit id="524" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="523" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -32,11 +32,11 @@
|
|||
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|
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<bit id="514" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
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|
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<bit id="513" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
<bit id="513" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
</bit>
|
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<bit id="512" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
<bit id="512" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
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|
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<bit id="511" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
<bit id="511" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
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|
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|
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</bit>
|
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|
|
@ -290,11 +290,11 @@
|
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|
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|
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|
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|
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|
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|
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|
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|
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<bit id="382" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[0]">
|
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|
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|
|
@ -314,17 +314,17 @@
|
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|
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|
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|
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|
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|
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|
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<bit id="369" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]">
|
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<bit id="368" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[1]">
|
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|
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<bit id="367" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[0]">
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@ -506,7 +506,7 @@
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<bit id="276" value="1" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
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|
@ -516,7 +516,7 @@
|
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|
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<bit id="271" value="1" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]">
|
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|
@ -592,17 +592,17 @@
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|
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<bit id="230" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[2]">
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|
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<bit id="229" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[1]">
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<bit id="228" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[0]">
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|
|
@ -616,9 +616,9 @@
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<bit id="221" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
|
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<bit id="220" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
|
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|
@ -702,21 +702,21 @@
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|
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|
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|
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<bit id="174" value="0" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[1]">
|
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|
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<bit id="173" value="0" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[0]">
|
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|
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<bit id="172" value="1" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[2]">
|
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<bit id="172" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[2]">
|
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|
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|
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<bit id="171" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[1]">
|
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|
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<bit id="170" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[0]">
|
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|
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|
|
@ -736,9 +736,9 @@
|
|||
</bit>
|
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<bit id="162" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[0]">
|
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|
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|
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<bit id="161" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
|
||||
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|
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|
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<bit id="160" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
|
||||
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|
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<bit id="159" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_15.mem_out[2]">
|
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</bit>
|
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|
|
@ -796,7 +796,7 @@
|
|||
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|
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|
||||
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|
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|
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<bit id="131" value="1" path="fpga_top.sb_0__1_.mem_right_track_16.mem_out[0]">
|
||||
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|
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<bit id="130" value="0" path="fpga_top.sb_0__1_.mem_right_track_14.mem_out[1]">
|
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|
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|
|
@ -864,9 +864,9 @@
|
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|
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|
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|
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|
||||
</bit>
|
||||
<bit id="96" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[0]">
|
||||
<bit id="96" value="1" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="95" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_7.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -954,9 +954,9 @@
|
|||
</bit>
|
||||
<bit id="53" value="0" path="fpga_top.sb_1__1_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="52" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
|
||||
<bit id="52" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="51" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
|
||||
<bit id="51" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="50" value="0" path="fpga_top.sb_1__1_.mem_left_track_5.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1034,9 +1034,9 @@
|
|||
</bit>
|
||||
<bit id="13" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="12" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="12" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="11" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="11" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="10" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
|
|||
|
|
@ -431,14 +431,14 @@
|
|||
<instance level="3" name="mem_fle_3_in_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
<path id="6" net_name="unmapped"/>
|
||||
<path id="7" net_name="a"/>
|
||||
<path id="7" net_name="unmapped"/>
|
||||
<path id="8" net_name="unmapped"/>
|
||||
<path id="9" net_name="unmapped"/>
|
||||
<path id="10" net_name="unmapped"/>
|
||||
|
|
@ -449,10 +449,10 @@
|
|||
<output_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="7">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bit memory_port="mem_out[3]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
|
|
@ -498,14 +498,14 @@
|
|||
<instance level="3" name="mem_fle_3_in_3"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
<path id="6" net_name="unmapped"/>
|
||||
<path id="7" net_name="a"/>
|
||||
<path id="7" net_name="unmapped"/>
|
||||
<path id="8" net_name="unmapped"/>
|
||||
<path id="9" net_name="unmapped"/>
|
||||
<path id="10" net_name="unmapped"/>
|
||||
|
|
@ -516,9 +516,9 @@
|
|||
<output_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="3">
|
||||
<bitstream path_id="1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bit memory_port="mem_out[3]" value="1"/>
|
||||
</bitstream>
|
||||
|
|
@ -715,7 +715,7 @@
|
|||
<instance level="4" name="GPIO_DFF_mem"/>
|
||||
</hierarchy>
|
||||
<bitstream>
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
|
|
@ -731,7 +731,7 @@
|
|||
<instance level="4" name="GPIO_DFF_mem"/>
|
||||
</hierarchy>
|
||||
<bitstream>
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
|
|
@ -1054,17 +1054,17 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="1">
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_top_track_2" hierarchy_level="2">
|
||||
|
|
@ -1074,16 +1074,16 @@
|
|||
<instance level="2" name="mem_top_track_2"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="1">
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_top_track_4" hierarchy_level="2">
|
||||
|
|
@ -1093,8 +1093,8 @@
|
|||
<instance level="2" name="mem_top_track_4"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1112,16 +1112,16 @@
|
|||
<instance level="2" name="mem_top_track_6"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_top_track_8" hierarchy_level="2">
|
||||
|
|
@ -1190,7 +1190,7 @@
|
|||
<instance level="2" name="mem_top_track_14"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -1209,7 +1209,7 @@
|
|||
<instance level="2" name="mem_top_track_16"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -1228,7 +1228,7 @@
|
|||
<instance level="2" name="mem_top_track_18"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1480,15 +1480,15 @@
|
|||
<instance level="2" name="mem_right_track_18"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_right_track_20" hierarchy_level="2">
|
||||
|
|
@ -1713,13 +1713,13 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bitstream path_id="2">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
|
|
@ -1749,7 +1749,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1767,7 +1767,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1826,7 +1826,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1846,8 +1846,8 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="2" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1865,8 +1865,8 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1884,7 +1884,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -1961,16 +1961,16 @@
|
|||
<instance level="2" name="mem_bottom_track_17"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_bottom_track_19" hierarchy_level="2">
|
||||
|
|
@ -1981,7 +1981,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -1999,7 +1999,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="a"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="c"/>
|
||||
|
|
@ -2077,16 +2077,16 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bitstream path_id="2">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_top_track_4" hierarchy_level="2">
|
||||
|
|
@ -2136,13 +2136,13 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="c"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bitstream path_id="2">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
|
|
@ -2193,7 +2193,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -2213,7 +2213,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -2559,7 +2559,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -2675,7 +2675,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -2695,8 +2695,8 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="1" net_name="b"/>
|
||||
<path id="2" net_name="a"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -2845,7 +2845,7 @@
|
|||
<instance level="2" name="mem_left_track_5"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -2869,11 +2869,11 @@
|
|||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_left_track_9" hierarchy_level="2">
|
||||
|
|
@ -2902,7 +2902,7 @@
|
|||
<instance level="2" name="mem_left_track_11"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -3128,7 +3128,7 @@
|
|||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="4" net_name="c"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -3266,7 +3266,7 @@
|
|||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="4" net_name="c"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -3287,7 +3287,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="c"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
|
|
@ -3360,7 +3360,7 @@
|
|||
<path id="1" net_name="c"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="4" net_name="a"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
|
|
@ -3382,7 +3382,7 @@
|
|||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="3" net_name="c"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -3403,7 +3403,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="c"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
|
|
@ -3498,15 +3498,15 @@
|
|||
<path id="1" net_name="c"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="4" net_name="a"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bitstream path_id="4">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
|
|
@ -3519,7 +3519,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
|
|
@ -3541,7 +3541,7 @@
|
|||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="1" net_name="c"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
|
|
@ -3565,7 +3565,7 @@
|
|||
<instance level="2" name="mem_left_ipin_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3573,12 +3573,12 @@
|
|||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_left_ipin_1" hierarchy_level="2">
|
||||
|
|
@ -3588,20 +3588,20 @@
|
|||
<instance level="2" name="mem_left_ipin_1"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="2">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_right_ipin_0" hierarchy_level="2">
|
||||
|
|
@ -3611,12 +3611,12 @@
|
|||
<instance level="2" name="mem_right_ipin_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
<path id="5" net_name="c"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -3636,7 +3636,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="a"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
|
|
@ -3657,7 +3657,7 @@
|
|||
<instance level="2" name="mem_right_ipin_2"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3726,7 +3726,7 @@
|
|||
<instance level="2" name="mem_right_ipin_5"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3749,12 +3749,12 @@
|
|||
<instance level="2" name="mem_right_ipin_6"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="a"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
<path id="5" net_name="c"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
|
|
@ -3775,7 +3775,7 @@
|
|||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="3" net_name="c"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
|
|
@ -3822,7 +3822,7 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="b"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
|
|
@ -3843,7 +3843,7 @@
|
|||
<instance level="2" name="mem_left_ipin_2"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="c"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3874,12 +3874,12 @@
|
|||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_left_ipin_4" hierarchy_level="2">
|
||||
|
|
@ -3891,18 +3891,18 @@
|
|||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="2" net_name="c"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
<path id="4" net_name="unmapped"/>
|
||||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bitstream path_id="2">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_left_ipin_5" hierarchy_level="2">
|
||||
|
|
@ -3912,7 +3912,7 @@
|
|||
<instance level="2" name="mem_left_ipin_5"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="c"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3981,7 +3981,7 @@
|
|||
<instance level="2" name="mem_right_ipin_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
<path id="2" net_name="unmapped"/>
|
||||
<path id="3" net_name="unmapped"/>
|
||||
|
|
@ -3989,12 +3989,12 @@
|
|||
<path id="5" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="0" net_name="b"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bitstream path_id="0">
|
||||
<bit memory_port="mem_out[0]" value="1"/>
|
||||
<bit memory_port="mem_out[1]" value="1"/>
|
||||
<bit memory_port="mem_out[2]" value="1"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
<bitstream_block name="mem_right_ipin_1" hierarchy_level="2">
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ set_units -time s
|
|||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10} [get_ports {clk[0]}]
|
||||
create_clock -name clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
-->
|
||||
|
||||
<io_mapping>
|
||||
<io name="gfpga_pad_GPIO_PAD[26:26]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[25:25]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[11:11]" net="c" dir="output"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[27:27]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[15:15]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[12:12]" net="c" dir="output"/>
|
||||
</io_mapping>
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
|
|||
initial begin
|
||||
clk[0] <= 1'b0;
|
||||
while(1) begin
|
||||
#0.5422864556
|
||||
#0.6573184729
|
||||
clk[0] <= !clk[0];
|
||||
end
|
||||
end
|
||||
|
|
@ -109,7 +109,7 @@ initial begin
|
|||
$timeformat(-9, 2, "ns", 20);
|
||||
$display("Simulation start");
|
||||
// ----- Can be changed by the user for his/her need -------
|
||||
#7.592010975
|
||||
#9.202458382
|
||||
if(nb_error == 0) begin
|
||||
$display("Simulation Succeed");
|
||||
end else begin
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -42,14 +42,14 @@ wire [0:0] clk_fm;
|
|||
// ----- End Connect Global ports of FPGA top module -----
|
||||
|
||||
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[13] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[13] = a[0];
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[38] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[38] = a[0];
|
||||
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = b[0];
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[58] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[58] = b[0];
|
||||
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[10] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[10];
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[17] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[17];
|
||||
|
||||
// ----- Wire unused FPGA I/Os to constants -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
|
||||
|
|
@ -62,11 +62,13 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[19] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[20] = 1'b0;
|
||||
|
|
@ -87,7 +89,6 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0;
|
||||
|
|
@ -107,7 +108,6 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[55] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[56] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[57] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[58] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[59] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[60] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[61] = 1'b0;
|
||||
|
|
@ -529,10 +529,10 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -557,14 +557,14 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b1101;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b0010;
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
|
||||
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -865,10 +865,10 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -893,14 +893,14 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
|
||||
force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
|
||||
force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -969,8 +969,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -983,8 +983,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -1241,8 +1241,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1337,8 +1337,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__4_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__4_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1409,8 +1409,8 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = 4'b0111;
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = 4'b1000;
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1457,8 +1457,8 @@ initial begin
|
|||
force U0_formal_verification.sb_1__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0011;
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1100;
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_1__4_.mem_right_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1531,8 +1531,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:3] = 4'b0111;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:3] = 4'b1000;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1593,8 +1593,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__4_.mem_right_track_16.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1613,10 +1613,10 @@ initial begin
|
|||
force U0_formal_verification.sb_2__4_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_out[0:3] = 4'b0010;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = 4'b1101;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = 4'b0010;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = 4'b1101;
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1641,8 +1641,8 @@ initial begin
|
|||
force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = 4'b0111;
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = 4'b1000;
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1683,8 +1683,8 @@ initial begin
|
|||
force U0_formal_verification.sb_3__2_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = 4'b0101;
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = 4'b1010;
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
|
|
@ -1751,8 +1751,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1795,8 +1795,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1833,8 +1833,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1855,8 +1855,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__3_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = 4'b0101;
|
||||
force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = 4'b1010;
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1867,8 +1867,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__3_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__3_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -1889,8 +1889,8 @@ initial begin
|
|||
force U0_formal_verification.sb_4__4_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_4__4_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -2055,8 +2055,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_3.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_4.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2067,10 +2067,10 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_out[0:2] = 3'b010;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_outb[0:2] = 3'b101;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_out[0:2] = 3'b011;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_outb[0:2] = 3'b100;
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__4_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_3__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2133,8 +2133,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_3__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2209,8 +2209,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
|
||||
|
|
@ -2415,8 +2415,8 @@ initial begin
|
|||
force U0_formal_verification.cby_3__2_.mem_right_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
|
||||
force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
|
||||
force U0_formal_verification.cby_3__3_.mem_right_ipin_1.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
|
|||
|
|
@ -213,10 +213,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -225,10 +222,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -277,25 +270,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -830,6 +804,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -853,6 +828,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -863,7 +840,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -885,6 +864,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -897,6 +877,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -945,6 +928,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -955,9 +939,13 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1069,6 +1057,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1244,6 +1234,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1271,7 +1263,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1729,6 +1723,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2111,9 +2108,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2365,6 +2359,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2565,6 +2562,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2819,6 +2817,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3625,8 +3625,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -3805,7 +3805,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3899,8 +3899,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -3908,16 +3908,13 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3934,7 +3931,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3944,11 +3940,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3971,8 +3965,14 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -3993,11 +3993,8 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -4024,6 +4021,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -4133,8 +4133,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
|
|||
|
|
@ -430,13 +430,13 @@
|
|||
</bit>
|
||||
<bit id="3998" value="0" path="fpga_top.sb_1__3_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3997" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
<bit id="3997" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3996" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3995" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
<bit id="3995" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3994" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
<bit id="3994" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3993" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -454,13 +454,13 @@
|
|||
</bit>
|
||||
<bit id="3986" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3985" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
<bit id="3985" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3984" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
<bit id="3984" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3983" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
<bit id="3983" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3982" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
<bit id="3982" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3981" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -558,7 +558,7 @@
|
|||
</bit>
|
||||
<bit id="3934" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3933" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
<bit id="3933" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3932" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -580,19 +580,19 @@
|
|||
</bit>
|
||||
<bit id="3923" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="3922" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
<bit id="3922" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="3921" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="3920" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
<bit id="3920" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="3919" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3918" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
<bit id="3918" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3917" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3916" value="1" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
<bit id="3916" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3915" value="0" path="fpga_top.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1612,7 +1612,7 @@
|
|||
</bit>
|
||||
<bit id="3407" value="0" path="fpga_top.cby_4__4_.mem_left_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3406" value="0" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[1]">
|
||||
<bit id="3406" value="1" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3405" value="0" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -1660,9 +1660,9 @@
|
|||
</bit>
|
||||
<bit id="3383" value="0" path="fpga_top.sb_4__3_.mem_left_track_13.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3382" value="0" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[1]">
|
||||
<bit id="3382" value="1" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3381" value="0" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[0]">
|
||||
<bit id="3381" value="1" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3380" value="0" path="fpga_top.sb_4__3_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1684,11 +1684,11 @@
|
|||
</bit>
|
||||
<bit id="3371" value="0" path="fpga_top.sb_4__3_.mem_left_track_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3370" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[3]">
|
||||
<bit id="3370" value="1" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3369" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3368" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[1]">
|
||||
<bit id="3368" value="1" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3367" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -1732,7 +1732,7 @@
|
|||
</bit>
|
||||
<bit id="3347" value="0" path="fpga_top.sb_4__3_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3346" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
<bit id="3346" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3345" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -1758,11 +1758,11 @@
|
|||
</bit>
|
||||
<bit id="3334" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3333" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
<bit id="3333" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3332" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
<bit id="3332" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3331" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
<bit id="3331" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3330" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -1860,7 +1860,7 @@
|
|||
</bit>
|
||||
<bit id="3283" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3282" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
<bit id="3282" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3281" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -1882,19 +1882,19 @@
|
|||
</bit>
|
||||
<bit id="3272" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="3271" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
<bit id="3271" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="3270" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="3269" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
<bit id="3269" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="3268" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="3267" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
<bit id="3267" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="3266" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3265" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
<bit id="3265" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3264" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -2118,9 +2118,9 @@
|
|||
</bit>
|
||||
<bit id="3154" value="0" path="fpga_top.sb_4__2_.mem_left_track_11.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3153" value="0" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[1]">
|
||||
<bit id="3153" value="1" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="3152" value="0" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[0]">
|
||||
<bit id="3152" value="1" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="3151" value="0" path="fpga_top.sb_4__2_.mem_left_track_7.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -2472,9 +2472,9 @@
|
|||
</bit>
|
||||
<bit id="2977" value="0" path="fpga_top.cby_3__3_.mem_right_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2976" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[1]">
|
||||
<bit id="2976" value="1" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2975" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[0]">
|
||||
<bit id="2975" value="1" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2974" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -2530,11 +2530,11 @@
|
|||
</bit>
|
||||
<bit id="2948" value="0" path="fpga_top.sb_3__2_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2947" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[3]">
|
||||
<bit id="2947" value="1" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="2946" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="2945" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[1]">
|
||||
<bit id="2945" value="1" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2944" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -3450,11 +3450,11 @@
|
|||
</bit>
|
||||
<bit id="2488" value="0" path="fpga_top.sb_1__2_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2487" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[3]">
|
||||
<bit id="2487" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="2486" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[2]">
|
||||
<bit id="2486" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="2485" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[1]">
|
||||
<bit id="2485" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2484" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4226,11 +4226,11 @@
|
|||
</bit>
|
||||
<bit id="2100" value="0" path="fpga_top.sb_2__1_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="2099" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[3]">
|
||||
<bit id="2099" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="2098" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[2]">
|
||||
<bit id="2098" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="2097" value="1" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[1]">
|
||||
<bit id="2097" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="2096" value="0" path="fpga_top.sb_2__1_.mem_left_track_1.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4722,11 +4722,11 @@
|
|||
</bit>
|
||||
<bit id="1852" value="0" path="fpga_top.sb_3__1_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1851" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[3]">
|
||||
<bit id="1851" value="1" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1850" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[2]">
|
||||
<bit id="1850" value="1" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1849" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[1]">
|
||||
<bit id="1849" value="1" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1848" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -5128,7 +5128,7 @@
|
|||
</bit>
|
||||
<bit id="1649" value="0" path="fpga_top.sb_4__1_.mem_left_track_5.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1648" value="0" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[1]">
|
||||
<bit id="1648" value="1" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1647" value="0" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -5638,9 +5638,9 @@
|
|||
</bit>
|
||||
<bit id="1394" value="0" path="fpga_top.sb_4__0_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1393" value="0" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[1]">
|
||||
<bit id="1393" value="1" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1392" value="0" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[0]">
|
||||
<bit id="1392" value="1" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1391" value="0" path="fpga_top.sb_4__0_.mem_top_track_4.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7254,9 +7254,9 @@
|
|||
</bit>
|
||||
<bit id="586" value="0" path="fpga_top.sb_0__1_.mem_top_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="585" value="1" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[3]">
|
||||
<bit id="585" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="584" value="1" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[2]">
|
||||
<bit id="584" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="583" value="0" path="fpga_top.sb_0__1_.mem_top_track_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7614,7 +7614,7 @@
|
|||
</bit>
|
||||
<bit id="406" value="0" path="fpga_top.sb_0__4_.mem_right_track_14.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="405" value="1" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[1]">
|
||||
<bit id="405" value="0" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="404" value="0" path="fpga_top.sb_0__4_.mem_right_track_12.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7802,9 +7802,9 @@
|
|||
</bit>
|
||||
<bit id="312" value="0" path="fpga_top.sb_1__4_.mem_right_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="311" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[3]">
|
||||
<bit id="311" value="1" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="310" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[2]">
|
||||
<bit id="310" value="1" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="309" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7820,7 +7820,7 @@
|
|||
</bit>
|
||||
<bit id="303" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="302" value="0" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="302" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="301" value="1" path="fpga_top.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7830,15 +7830,15 @@
|
|||
</bit>
|
||||
<bit id="298" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="297" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[2]">
|
||||
<bit id="297" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="296" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[1]">
|
||||
<bit id="296" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="295" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="294" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="293" value="1" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[1]">
|
||||
<bit id="293" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="292" value="0" path="fpga_top.cbx_2__4_.mem_top_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -7872,7 +7872,7 @@
|
|||
</bit>
|
||||
<bit id="277" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="276" value="1" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[2]">
|
||||
<bit id="276" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="275" value="0" path="fpga_top.cbx_2__4_.mem_bottom_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7892,7 +7892,7 @@
|
|||
</bit>
|
||||
<bit id="267" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="266" value="1" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[2]">
|
||||
<bit id="266" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="265" value="0" path="fpga_top.sb_2__4_.mem_left_track_17.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7900,7 +7900,7 @@
|
|||
</bit>
|
||||
<bit id="263" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="262" value="1" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[2]">
|
||||
<bit id="262" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="261" value="0" path="fpga_top.sb_2__4_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7946,9 +7946,9 @@
|
|||
</bit>
|
||||
<bit id="240" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_5.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="239" value="1" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[1]">
|
||||
<bit id="239" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="238" value="1" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[0]">
|
||||
<bit id="238" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="237" value="0" path="fpga_top.sb_2__4_.mem_bottom_track_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -7990,7 +7990,7 @@
|
|||
</bit>
|
||||
<bit id="218" value="1" path="fpga_top.grid_io_top_3__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="217" value="1" path="fpga_top.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
<bit id="217" value="0" path="fpga_top.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="216" value="1" path="fpga_top.grid_io_top_3__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -8046,11 +8046,11 @@
|
|||
</bit>
|
||||
<bit id="190" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="189" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[2]">
|
||||
<bit id="189" value="1" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="188" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[1]">
|
||||
<bit id="188" value="1" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="187" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[0]">
|
||||
<bit id="187" value="1" path="fpga_top.cbx_3__4_.mem_bottom_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="186" value="0" path="fpga_top.cbx_3__4_.mem_bottom_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -8270,9 +8270,9 @@
|
|||
</bit>
|
||||
<bit id="78" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_15.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="77" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[1]">
|
||||
<bit id="77" value="1" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="76" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[0]">
|
||||
<bit id="76" value="1" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="75" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_11.mem_out[1]">
|
||||
</bit>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -14,7 +14,7 @@ set_units -time s
|
|||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.084572876e-09 -waveform {0 5.42286438e-10} [get_ports {clk[0]}]
|
||||
create_clock -name clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
-->
|
||||
|
||||
<io_mapping>
|
||||
<io name="gfpga_pad_GPIO_PAD[13:13]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[12:12]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[10:10]" net="c" dir="output"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[38:38]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[58:58]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[17:17]" net="c" dir="output"/>
|
||||
</io_mapping>
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
|
|||
initial begin
|
||||
clk[0] <= 1'b0;
|
||||
while(1) begin
|
||||
#0.5561901927
|
||||
#0.4485172927
|
||||
clk[0] <= !clk[0];
|
||||
end
|
||||
end
|
||||
|
|
@ -109,7 +109,7 @@ initial begin
|
|||
$timeformat(-9, 2, "ns", 20);
|
||||
$display("Simulation start");
|
||||
// ----- Can be changed by the user for his/her need -------
|
||||
#7.786663055
|
||||
#6.279242039
|
||||
if(nb_error == 0) begin
|
||||
$display("Simulation Succeed");
|
||||
end else begin
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -45,14 +45,14 @@ wire [0:0] clk_fm;
|
|||
// ----- End Connect Global ports of FPGA top module -----
|
||||
|
||||
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = a[0];
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[39] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[39] = a[0];
|
||||
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[9] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[9] = b[0];
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[48] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[48] = b[0];
|
||||
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[11];
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[34] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[34];
|
||||
|
||||
// ----- Wire unused FPGA I/Os to constants -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
|
||||
|
|
@ -64,7 +64,10 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[6] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
|
||||
|
|
@ -86,12 +89,10 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[31] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[32] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[33] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[34] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[42] = 1'b0;
|
||||
|
|
@ -100,7 +101,6 @@ wire [0:0] clk_fm;
|
|||
assign gfpga_pad_GPIO_PAD_fm[45] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[46] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[47] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[48] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[49] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[50] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[51] = 1'b0;
|
||||
|
|
@ -316,14 +316,14 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = {17{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = 17'b00000000110000001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = 17'b11111111001111110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0010;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1101;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
|
||||
|
|
@ -354,10 +354,10 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0001001000;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1110110111;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0010001000;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1101110111;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
|
||||
|
|
@ -396,14 +396,14 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = 17'b00000000110000001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = 17'b11111111001111110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = {17{1'b1}};
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0010;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1101;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:2] = 3'b001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
|
||||
|
|
@ -434,10 +434,10 @@ initial begin
|
|||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b1000010000;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b0111101111;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b1000000100;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b0111111011;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:9] = 10'b0000000001;
|
||||
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:9] = 10'b1111111110;
|
||||
force U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -462,8 +462,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -508,8 +508,8 @@ initial begin
|
|||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
|
||||
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
|
||||
|
|
@ -586,8 +586,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -624,8 +624,8 @@ initial begin
|
|||
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00100100;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:7] = 8'b11011011;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:5] = 6'b010001;
|
||||
|
|
@ -694,12 +694,12 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_top_track_0.mem_outb[0:7] = 8'b10111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:7] = 8'b00101000;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:7] = 8'b11010111;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:7] = 8'b01000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:7] = 8'b10111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:7] = 8'b01001000;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:7] = 8'b10110111;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:7] = 8'b01000001;
|
||||
|
|
@ -716,18 +716,18 @@ initial begin
|
|||
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:7] = 8'b10001000;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:7] = 8'b01110111;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:5] = 6'b010010;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:5] = 6'b101101;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:7] = 8'b00000001;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:7] = 8'b11111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:5] = 6'b010001;
|
||||
force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:5] = 6'b101110;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -762,12 +762,12 @@ initial begin
|
|||
force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -798,8 +798,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__1_.mem_left_track_3.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_5.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_5.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:5] = 6'b000010;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:5] = 6'b111101;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -812,8 +812,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -834,8 +834,8 @@ initial begin
|
|||
force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -900,10 +900,10 @@ initial begin
|
|||
force U0_formal_verification.cbx_1__2_.mem_bottom_ipin_7.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:1] = 2'b01;
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:1] = 2'b10;
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b0}};
|
||||
|
|
@ -914,8 +914,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:5] = 6'b010100;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:5] = 6'b101011;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:5] = 6'b000001;
|
||||
|
|
@ -934,8 +934,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:1] = {2{1'b0}};
|
||||
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:1] = {2{1'b1}};
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:5] = 6'b000001;
|
||||
|
|
@ -944,8 +944,8 @@ initial begin
|
|||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_1.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_2.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_2.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_out[0:5] = 6'b001100;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_outb[0:5] = 6'b110011;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_4.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_4.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_5.mem_out[0:5] = 6'b000001;
|
||||
|
|
@ -1062,8 +1062,8 @@ initial begin
|
|||
force U0_formal_verification.cby_2__2_.mem_left_ipin_6.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cby_2__2_.mem_left_ipin_7.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cby_2__2_.mem_left_ipin_7.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:5] = 6'b010100;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:5] = 6'b101011;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:5] = 6'b000001;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:5] = 6'b111110;
|
||||
force U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:5] = 6'b000001;
|
||||
|
|
|
|||
|
|
@ -407,13 +407,13 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
|
|
@ -423,12 +423,12 @@
|
|||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -457,9 +457,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -471,12 +472,11 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -613,10 +613,10 @@
|
|||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -624,15 +624,15 @@
|
|||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -773,11 +773,11 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
|
|
@ -829,8 +829,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -851,6 +850,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -927,13 +927,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -943,7 +940,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1083,26 +1083,26 @@
|
|||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1327,17 +1327,11 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
|
|
@ -1345,6 +1339,7 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1356,6 +1351,9 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1371,10 +1369,12 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -1945,8 +1945,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2041,12 +2041,12 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2211,8 +2211,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -2227,20 +2227,20 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
|
|
@ -2253,7 +2253,7 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
@ -2281,10 +2281,10 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
1
|
||||
|
|
@ -2311,7 +2311,6 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2333,7 +2332,8 @@
|
|||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
|
|
@ -2362,7 +2362,7 @@
|
|||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
|
|
|
|||
|
|
@ -818,19 +818,19 @@
|
|||
</bit>
|
||||
<bit id="1966" value="0" path="fpga_top.sb_1__1_.mem_right_track_16.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1965" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[7]">
|
||||
<bit id="1965" value="1" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1964" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1963" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1962" value="1" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[4]">
|
||||
<bit id="1962" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1961" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1960" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1959" value="1" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[1]">
|
||||
<bit id="1959" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1958" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -850,17 +850,17 @@
|
|||
</bit>
|
||||
<bit id="1950" value="0" path="fpga_top.sb_1__1_.mem_right_track_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1949" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[7]">
|
||||
<bit id="1949" value="1" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1948" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1947" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1946" value="1" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[4]">
|
||||
<bit id="1946" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1945" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1944" value="1" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[2]">
|
||||
<bit id="1944" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1943" value="0" path="fpga_top.sb_1__1_.mem_top_track_16.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -918,11 +918,11 @@
|
|||
</bit>
|
||||
<bit id="1916" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1915" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
|
||||
<bit id="1915" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1914" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1913" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[7]">
|
||||
<bit id="1913" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1912" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[6]">
|
||||
</bit>
|
||||
|
|
@ -936,9 +936,9 @@
|
|||
</bit>
|
||||
<bit id="1907" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1906" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0]">
|
||||
<bit id="1906" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1905" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[9]">
|
||||
<bit id="1905" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1904" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[8]">
|
||||
</bit>
|
||||
|
|
@ -946,7 +946,7 @@
|
|||
</bit>
|
||||
<bit id="1902" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1901" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[5]">
|
||||
<bit id="1901" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1900" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[4]">
|
||||
</bit>
|
||||
|
|
@ -956,7 +956,7 @@
|
|||
</bit>
|
||||
<bit id="1897" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1896" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
|
||||
<bit id="1896" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1895" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[9]">
|
||||
</bit>
|
||||
|
|
@ -1230,9 +1230,9 @@
|
|||
</bit>
|
||||
<bit id="1760" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1759" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[3]">
|
||||
<bit id="1759" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1758" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[2]">
|
||||
<bit id="1758" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1757" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1252,7 +1252,7 @@
|
|||
</bit>
|
||||
<bit id="1749" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1748" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[16]">
|
||||
<bit id="1748" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[16]">
|
||||
</bit>
|
||||
<bit id="1747" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[15]">
|
||||
</bit>
|
||||
|
|
@ -1266,9 +1266,9 @@
|
|||
</bit>
|
||||
<bit id="1742" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[10]">
|
||||
</bit>
|
||||
<bit id="1741" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
|
||||
<bit id="1741" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1740" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
|
||||
<bit id="1740" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1739" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[7]">
|
||||
</bit>
|
||||
|
|
@ -1550,15 +1550,15 @@
|
|||
</bit>
|
||||
<bit id="1600" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1599" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[5]">
|
||||
<bit id="1599" value="1" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1598" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1597" value="1" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[3]">
|
||||
<bit id="1597" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1596" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1595" value="1" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[1]">
|
||||
<bit id="1595" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1594" value="0" path="fpga_top.cby_2__2_.mem_right_ipin_0.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -1662,9 +1662,9 @@
|
|||
</bit>
|
||||
<bit id="1544" value="0" path="fpga_top.cbx_2__1_.mem_bottom_ipin_5.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1543" value="1" path="fpga_top.cbx_2__1_.mem_bottom_ipin_4.mem_out[1]">
|
||||
<bit id="1543" value="0" path="fpga_top.cbx_2__1_.mem_bottom_ipin_4.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1542" value="1" path="fpga_top.cbx_2__1_.mem_bottom_ipin_4.mem_out[0]">
|
||||
<bit id="1542" value="0" path="fpga_top.cbx_2__1_.mem_bottom_ipin_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1541" value="0" path="fpga_top.cbx_2__1_.mem_bottom_ipin_3.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -1694,9 +1694,9 @@
|
|||
</bit>
|
||||
<bit id="1528" value="0" path="fpga_top.sb_2__1_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1527" value="0" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[5]">
|
||||
<bit id="1527" value="1" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1526" value="1" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[4]">
|
||||
<bit id="1526" value="0" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1525" value="0" path="fpga_top.sb_2__1_.mem_left_track_7.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -1858,13 +1858,13 @@
|
|||
</bit>
|
||||
<bit id="1446" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1445" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
|
||||
<bit id="1445" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1444" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1443" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1442" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[6]">
|
||||
<bit id="1442" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1441" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[5]">
|
||||
</bit>
|
||||
|
|
@ -1872,25 +1872,25 @@
|
|||
</bit>
|
||||
<bit id="1439" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1438" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[2]">
|
||||
<bit id="1438" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1437" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1436" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1435" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[9]">
|
||||
<bit id="1435" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1434" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1433" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="1432" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[6]">
|
||||
<bit id="1432" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="1431" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1430" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1429" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[3]">
|
||||
<bit id="1429" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1428" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[2]">
|
||||
</bit>
|
||||
|
|
@ -2170,9 +2170,9 @@
|
|||
</bit>
|
||||
<bit id="1290" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1289" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[3]">
|
||||
<bit id="1289" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1288" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[2]">
|
||||
<bit id="1288" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1287" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -2192,7 +2192,7 @@
|
|||
</bit>
|
||||
<bit id="1279" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1278" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[16]">
|
||||
<bit id="1278" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[16]">
|
||||
</bit>
|
||||
<bit id="1277" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[15]">
|
||||
</bit>
|
||||
|
|
@ -2206,9 +2206,9 @@
|
|||
</bit>
|
||||
<bit id="1272" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[10]">
|
||||
</bit>
|
||||
<bit id="1271" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
|
||||
<bit id="1271" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
|
||||
</bit>
|
||||
<bit id="1270" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
|
||||
<bit id="1270" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
|
||||
</bit>
|
||||
<bit id="1269" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[7]">
|
||||
</bit>
|
||||
|
|
@ -2658,15 +2658,15 @@
|
|||
</bit>
|
||||
<bit id="1046" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1045" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[5]">
|
||||
<bit id="1045" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="1044" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="1043" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[3]">
|
||||
<bit id="1043" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="1042" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="1041" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[1]">
|
||||
<bit id="1041" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1040" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -2706,11 +2706,11 @@
|
|||
</bit>
|
||||
<bit id="1022" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1021" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[1]">
|
||||
<bit id="1021" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1020" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[0]">
|
||||
<bit id="1020" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1019" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[1]">
|
||||
<bit id="1019" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1018" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -2742,7 +2742,7 @@
|
|||
</bit>
|
||||
<bit id="1004" value="0" path="fpga_top.sb_2__0_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="1003" value="0" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[1]">
|
||||
<bit id="1003" value="1" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="1002" value="0" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -2752,7 +2752,7 @@
|
|||
</bit>
|
||||
<bit id="999" value="0" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="998" value="0" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[0]">
|
||||
<bit id="998" value="1" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="997" value="0" path="fpga_top.sb_2__0_.mem_left_track_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -3894,9 +3894,9 @@
|
|||
</bit>
|
||||
<bit id="428" value="0" path="fpga_top.sb_0__0_.mem_right_track_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="427" value="0" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[1]">
|
||||
<bit id="427" value="1" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="426" value="0" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[0]">
|
||||
<bit id="426" value="1" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="425" value="0" path="fpga_top.sb_0__0_.mem_right_track_0.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4086,17 +4086,17 @@
|
|||
</bit>
|
||||
<bit id="332" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="331" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[7]">
|
||||
<bit id="331" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="330" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="329" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[5]">
|
||||
<bit id="329" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="328" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="327" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="326" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[2]">
|
||||
<bit id="326" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="325" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4426,9 +4426,9 @@
|
|||
</bit>
|
||||
<bit id="162" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="161" value="1" path="fpga_top.sb_1__2_.mem_bottom_track_7.mem_out[1]">
|
||||
<bit id="161" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_7.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="160" value="1" path="fpga_top.sb_1__2_.mem_bottom_track_7.mem_out[0]">
|
||||
<bit id="160" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_7.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="159" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_5.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4458,9 +4458,9 @@
|
|||
</bit>
|
||||
<bit id="146" value="0" path="fpga_top.sb_1__2_.mem_bottom_track_1.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="145" value="0" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[5]">
|
||||
<bit id="145" value="1" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="144" value="1" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[4]">
|
||||
<bit id="144" value="0" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="143" value="0" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -4470,13 +4470,13 @@
|
|||
</bit>
|
||||
<bit id="140" value="0" path="fpga_top.sb_1__2_.mem_right_track_16.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="139" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[7]">
|
||||
<bit id="139" value="1" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[7]">
|
||||
</bit>
|
||||
<bit id="138" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[6]">
|
||||
</bit>
|
||||
<bit id="137" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="136" value="1" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[4]">
|
||||
<bit id="136" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="135" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[3]">
|
||||
</bit>
|
||||
|
|
@ -4484,7 +4484,7 @@
|
|||
</bit>
|
||||
<bit id="133" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="132" value="1" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[0]">
|
||||
<bit id="132" value="0" path="fpga_top.sb_1__2_.mem_right_track_8.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="131" value="1" path="fpga_top.sb_1__2_.mem_right_track_0.mem_out[7]">
|
||||
</bit>
|
||||
|
|
@ -4510,7 +4510,7 @@
|
|||
</bit>
|
||||
<bit id="120" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="119" value="0" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
<bit id="119" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="118" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4566,13 +4566,13 @@
|
|||
</bit>
|
||||
<bit id="92" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_4.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="91" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[5]">
|
||||
<bit id="91" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[5]">
|
||||
</bit>
|
||||
<bit id="90" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[4]">
|
||||
</bit>
|
||||
<bit id="89" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[3]">
|
||||
<bit id="89" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[3]">
|
||||
</bit>
|
||||
<bit id="88" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[2]">
|
||||
<bit id="88" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[2]">
|
||||
</bit>
|
||||
<bit id="87" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_3.mem_out[1]">
|
||||
</bit>
|
||||
|
|
@ -4626,7 +4626,7 @@
|
|||
</bit>
|
||||
<bit id="62" value="0" path="fpga_top.sb_2__2_.mem_left_track_11.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="61" value="1" path="fpga_top.sb_2__2_.mem_left_track_9.mem_out[1]">
|
||||
<bit id="61" value="0" path="fpga_top.sb_2__2_.mem_left_track_9.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="60" value="0" path="fpga_top.sb_2__2_.mem_left_track_9.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4670,7 +4670,7 @@
|
|||
</bit>
|
||||
<bit id="40" value="0" path="fpga_top.sb_2__2_.mem_bottom_track_9.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="39" value="1" path="fpga_top.sb_2__2_.mem_bottom_track_7.mem_out[1]">
|
||||
<bit id="39" value="0" path="fpga_top.sb_2__2_.mem_bottom_track_7.mem_out[1]">
|
||||
</bit>
|
||||
<bit id="38" value="0" path="fpga_top.sb_2__2_.mem_bottom_track_7.mem_out[0]">
|
||||
</bit>
|
||||
|
|
@ -4728,7 +4728,7 @@
|
|||
</bit>
|
||||
<bit id="11" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="10" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
<bit id="10" value="0" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
<bit id="9" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
|
||||
</bit>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -14,7 +14,7 @@ set_units -time s
|
|||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.11238041e-09 -waveform {0 5.56190205e-10} [get_ports {clk[0]}]
|
||||
create_clock -name clk[0] -period 8.970345577e-10 -waveform {0 4.485172789e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
-->
|
||||
|
||||
<io_mapping>
|
||||
<io name="gfpga_pad_GPIO_PAD[12:12]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[9:9]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[11:11]" net="c" dir="output"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[39:39]" net="a" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[48:48]" net="b" dir="input"/>
|
||||
<io name="gfpga_pad_GPIO_PAD[34:34]" net="c" dir="output"/>
|
||||
</io_mapping>
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
|
|||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||
# VPR parameters
|
||||
# # Use a fixed routing channel width to save runtime
|
||||
vpr_route_chan_width=60
|
||||
vpr_route_chan_width=80
|
||||
openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
|
||||
|
||||
[ARCHITECTURES]
|
||||
|
|
|
|||
|
|
@ -16,10 +16,10 @@ timeout_each_job = 20*60
|
|||
fpga_flow=vpr_blif
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
external_fabric_key_file=
|
||||
openfpga_vpr_device_layout=2x2
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit ff83963de3e4c12f372d4d80fd039305b8344440
|
||||
Subproject commit 4834fd012621fe50736ec4f194f0dc459ddee794
|
||||
Loading…
Reference in New Issue