diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
index b02d4881b..f82c458e3 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
@@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
initial begin
clk[0] <= 1'b0;
while(1) begin
- #0.5744515657
+ #0.7626540661
clk[0] <= !clk[0];
end
end
@@ -109,7 +109,7 @@ initial begin
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
- #8.042322159
+ #10.6771574
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
index 4310fdd1e..acf0f91b8 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
@@ -9,14 +9,14 @@
##################################################
# Create clock
##################################################
-create_clock clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10}
+create_clock clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10}
##################################################
# Create input and output delays for used I/Os
##################################################
-set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[26]
-set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[25]
-set_output_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[11]
+set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[27]
+set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[15]
+set_output_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[12]
##################################################
# Disable timing for unused I/Os
@@ -32,10 +32,9 @@ set_disable_timing gfpga_pad_GPIO_PAD[7]
set_disable_timing gfpga_pad_GPIO_PAD[8]
set_disable_timing gfpga_pad_GPIO_PAD[9]
set_disable_timing gfpga_pad_GPIO_PAD[10]
-set_disable_timing gfpga_pad_GPIO_PAD[12]
+set_disable_timing gfpga_pad_GPIO_PAD[11]
set_disable_timing gfpga_pad_GPIO_PAD[13]
set_disable_timing gfpga_pad_GPIO_PAD[14]
-set_disable_timing gfpga_pad_GPIO_PAD[15]
set_disable_timing gfpga_pad_GPIO_PAD[16]
set_disable_timing gfpga_pad_GPIO_PAD[17]
set_disable_timing gfpga_pad_GPIO_PAD[18]
@@ -45,7 +44,8 @@ set_disable_timing gfpga_pad_GPIO_PAD[21]
set_disable_timing gfpga_pad_GPIO_PAD[22]
set_disable_timing gfpga_pad_GPIO_PAD[23]
set_disable_timing gfpga_pad_GPIO_PAD[24]
-set_disable_timing gfpga_pad_GPIO_PAD[27]
+set_disable_timing gfpga_pad_GPIO_PAD[25]
+set_disable_timing gfpga_pad_GPIO_PAD[26]
set_disable_timing gfpga_pad_GPIO_PAD[28]
set_disable_timing gfpga_pad_GPIO_PAD[29]
set_disable_timing gfpga_pad_GPIO_PAD[30]
@@ -156,7 +156,6 @@ set_disable_timing cbx_1__0_/chanx_left_in[7]
set_disable_timing cbx_1__0_/chanx_right_in[7]
set_disable_timing cbx_1__0_/chanx_left_in[8]
set_disable_timing cbx_1__0_/chanx_right_in[8]
-set_disable_timing cbx_1__0_/chanx_left_in[9]
set_disable_timing cbx_1__0_/chanx_right_in[9]
set_disable_timing cbx_1__0_/chanx_left_in[10]
set_disable_timing cbx_1__0_/chanx_right_in[10]
@@ -181,7 +180,6 @@ set_disable_timing cbx_1__0_/chanx_left_out[7]
set_disable_timing cbx_1__0_/chanx_right_out[7]
set_disable_timing cbx_1__0_/chanx_left_out[8]
set_disable_timing cbx_1__0_/chanx_right_out[8]
-set_disable_timing cbx_1__0_/chanx_left_out[9]
set_disable_timing cbx_1__0_/chanx_right_out[9]
set_disable_timing cbx_1__0_/chanx_left_out[10]
set_disable_timing cbx_1__0_/chanx_right_out[10]
@@ -274,7 +272,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[1]
set_disable_timing cbx_1__1_/chanx_left_in[2]
set_disable_timing cbx_1__1_/chanx_right_in[2]
set_disable_timing cbx_1__1_/chanx_left_in[3]
-set_disable_timing cbx_1__1_/chanx_right_in[3]
set_disable_timing cbx_1__1_/chanx_left_in[4]
set_disable_timing cbx_1__1_/chanx_right_in[4]
set_disable_timing cbx_1__1_/chanx_left_in[5]
@@ -283,7 +280,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[6]
set_disable_timing cbx_1__1_/chanx_right_in[6]
set_disable_timing cbx_1__1_/chanx_left_in[7]
set_disable_timing cbx_1__1_/chanx_right_in[7]
-set_disable_timing cbx_1__1_/chanx_left_in[8]
set_disable_timing cbx_1__1_/chanx_right_in[8]
set_disable_timing cbx_1__1_/chanx_left_in[9]
set_disable_timing cbx_1__1_/chanx_right_in[9]
@@ -299,7 +295,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[1]
set_disable_timing cbx_1__1_/chanx_left_out[2]
set_disable_timing cbx_1__1_/chanx_right_out[2]
set_disable_timing cbx_1__1_/chanx_left_out[3]
-set_disable_timing cbx_1__1_/chanx_right_out[3]
set_disable_timing cbx_1__1_/chanx_left_out[4]
set_disable_timing cbx_1__1_/chanx_right_out[4]
set_disable_timing cbx_1__1_/chanx_left_out[5]
@@ -308,7 +303,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[6]
set_disable_timing cbx_1__1_/chanx_right_out[6]
set_disable_timing cbx_1__1_/chanx_left_out[7]
set_disable_timing cbx_1__1_/chanx_right_out[7]
-set_disable_timing cbx_1__1_/chanx_left_out[8]
set_disable_timing cbx_1__1_/chanx_right_out[8]
set_disable_timing cbx_1__1_/chanx_left_out[9]
set_disable_timing cbx_1__1_/chanx_right_out[9]
@@ -326,7 +320,6 @@ set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_out
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0]
-set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0]
set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0]
set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0]
set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1]
@@ -374,7 +367,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[4]
set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[4]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[2]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[5]
-set_disable_timing cbx_1__1_/mux_top_ipin_0/in[5]
set_disable_timing cbx_1__1_/mux_top_ipin_1/in[3]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[4]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[4]
@@ -398,11 +390,12 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[4]
##################################################
# Disable timing for Connection block cby_0__1_
##################################################
+set_disable_timing cby_0__1_/chany_bottom_in[0]
set_disable_timing cby_0__1_/chany_top_in[0]
+set_disable_timing cby_0__1_/chany_bottom_in[1]
set_disable_timing cby_0__1_/chany_top_in[1]
set_disable_timing cby_0__1_/chany_bottom_in[2]
set_disable_timing cby_0__1_/chany_top_in[2]
-set_disable_timing cby_0__1_/chany_bottom_in[3]
set_disable_timing cby_0__1_/chany_top_in[3]
set_disable_timing cby_0__1_/chany_bottom_in[4]
set_disable_timing cby_0__1_/chany_top_in[4]
@@ -413,7 +406,6 @@ set_disable_timing cby_0__1_/chany_top_in[6]
set_disable_timing cby_0__1_/chany_bottom_in[7]
set_disable_timing cby_0__1_/chany_top_in[7]
set_disable_timing cby_0__1_/chany_bottom_in[8]
-set_disable_timing cby_0__1_/chany_top_in[8]
set_disable_timing cby_0__1_/chany_bottom_in[9]
set_disable_timing cby_0__1_/chany_top_in[9]
set_disable_timing cby_0__1_/chany_bottom_in[10]
@@ -421,11 +413,12 @@ set_disable_timing cby_0__1_/chany_bottom_in[11]
set_disable_timing cby_0__1_/chany_top_in[11]
set_disable_timing cby_0__1_/chany_bottom_in[12]
set_disable_timing cby_0__1_/chany_top_in[12]
+set_disable_timing cby_0__1_/chany_bottom_out[0]
set_disable_timing cby_0__1_/chany_top_out[0]
+set_disable_timing cby_0__1_/chany_bottom_out[1]
set_disable_timing cby_0__1_/chany_top_out[1]
set_disable_timing cby_0__1_/chany_bottom_out[2]
set_disable_timing cby_0__1_/chany_top_out[2]
-set_disable_timing cby_0__1_/chany_bottom_out[3]
set_disable_timing cby_0__1_/chany_top_out[3]
set_disable_timing cby_0__1_/chany_bottom_out[4]
set_disable_timing cby_0__1_/chany_top_out[4]
@@ -436,7 +429,6 @@ set_disable_timing cby_0__1_/chany_top_out[6]
set_disable_timing cby_0__1_/chany_bottom_out[7]
set_disable_timing cby_0__1_/chany_top_out[7]
set_disable_timing cby_0__1_/chany_bottom_out[8]
-set_disable_timing cby_0__1_/chany_top_out[8]
set_disable_timing cby_0__1_/chany_bottom_out[9]
set_disable_timing cby_0__1_/chany_top_out[9]
set_disable_timing cby_0__1_/chany_bottom_out[10]
@@ -444,6 +436,8 @@ set_disable_timing cby_0__1_/chany_bottom_out[11]
set_disable_timing cby_0__1_/chany_top_out[11]
set_disable_timing cby_0__1_/chany_bottom_out[12]
set_disable_timing cby_0__1_/chany_top_out[12]
+set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0]
+set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0]
@@ -452,11 +446,13 @@ set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_out
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0]
+set_disable_timing cby_0__1_/mux_left_ipin_0/in[1]
set_disable_timing cby_0__1_/mux_left_ipin_1/in[1]
set_disable_timing cby_0__1_/mux_right_ipin_5/in[1]
set_disable_timing cby_0__1_/mux_left_ipin_0/in[0]
set_disable_timing cby_0__1_/mux_left_ipin_1/in[0]
set_disable_timing cby_0__1_/mux_right_ipin_5/in[0]
+set_disable_timing cby_0__1_/mux_left_ipin_1/in[3]
set_disable_timing cby_0__1_/mux_right_ipin_0/in[1]
set_disable_timing cby_0__1_/mux_right_ipin_6/in[1]
set_disable_timing cby_0__1_/mux_left_ipin_1/in[2]
@@ -514,12 +510,10 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4]
# Disable timing for Connection block cby_1__1_
##################################################
set_disable_timing cby_1__1_/chany_top_in[0]
-set_disable_timing cby_1__1_/chany_bottom_in[1]
set_disable_timing cby_1__1_/chany_top_in[1]
set_disable_timing cby_1__1_/chany_top_in[2]
set_disable_timing cby_1__1_/chany_bottom_in[3]
set_disable_timing cby_1__1_/chany_top_in[3]
-set_disable_timing cby_1__1_/chany_bottom_in[4]
set_disable_timing cby_1__1_/chany_top_in[4]
set_disable_timing cby_1__1_/chany_bottom_in[5]
set_disable_timing cby_1__1_/chany_top_in[5]
@@ -538,12 +532,10 @@ set_disable_timing cby_1__1_/chany_top_in[11]
set_disable_timing cby_1__1_/chany_bottom_in[12]
set_disable_timing cby_1__1_/chany_top_in[12]
set_disable_timing cby_1__1_/chany_top_out[0]
-set_disable_timing cby_1__1_/chany_bottom_out[1]
set_disable_timing cby_1__1_/chany_top_out[1]
set_disable_timing cby_1__1_/chany_top_out[2]
set_disable_timing cby_1__1_/chany_bottom_out[3]
set_disable_timing cby_1__1_/chany_top_out[3]
-set_disable_timing cby_1__1_/chany_bottom_out[4]
set_disable_timing cby_1__1_/chany_top_out[4]
set_disable_timing cby_1__1_/chany_bottom_out[5]
set_disable_timing cby_1__1_/chany_top_out[5]
@@ -564,11 +556,10 @@ set_disable_timing cby_1__1_/chany_top_out[12]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0]
-set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0]
+set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0]
-set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0]
set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0]
set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0]
set_disable_timing cby_1__1_/mux_left_ipin_0/in[1]
@@ -579,11 +570,11 @@ set_disable_timing cby_1__1_/mux_left_ipin_1/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_7/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[3]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[1]
-set_disable_timing cby_1__1_/mux_right_ipin_0/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[0]
set_disable_timing cby_1__1_/mux_right_ipin_0/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[3]
+set_disable_timing cby_1__1_/mux_left_ipin_3/in[1]
set_disable_timing cby_1__1_/mux_right_ipin_1/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_3/in[0]
@@ -594,7 +585,6 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_3/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[0]
set_disable_timing cby_1__1_/mux_right_ipin_2/in[0]
-set_disable_timing cby_1__1_/mux_left_ipin_4/in[3]
set_disable_timing cby_1__1_/mux_left_ipin_5/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_5/in[0]
@@ -639,11 +629,12 @@ set_disable_timing cby_1__1_/mux_left_ipin_6/in[4]
##################################################
# Disable timing for Switch block sb_0__0_
##################################################
+set_disable_timing sb_0__0_/chany_top_out[0]
set_disable_timing sb_0__0_/chany_top_in[0]
+set_disable_timing sb_0__0_/chany_top_out[1]
set_disable_timing sb_0__0_/chany_top_in[1]
set_disable_timing sb_0__0_/chany_top_out[2]
set_disable_timing sb_0__0_/chany_top_in[2]
-set_disable_timing sb_0__0_/chany_top_out[3]
set_disable_timing sb_0__0_/chany_top_in[3]
set_disable_timing sb_0__0_/chany_top_out[4]
set_disable_timing sb_0__0_/chany_top_in[4]
@@ -654,7 +645,6 @@ set_disable_timing sb_0__0_/chany_top_in[6]
set_disable_timing sb_0__0_/chany_top_out[7]
set_disable_timing sb_0__0_/chany_top_in[7]
set_disable_timing sb_0__0_/chany_top_out[8]
-set_disable_timing sb_0__0_/chany_top_in[8]
set_disable_timing sb_0__0_/chany_top_out[9]
set_disable_timing sb_0__0_/chany_top_in[9]
set_disable_timing sb_0__0_/chany_top_out[10]
@@ -680,7 +670,6 @@ set_disable_timing sb_0__0_/chanx_right_out[7]
set_disable_timing sb_0__0_/chanx_right_in[7]
set_disable_timing sb_0__0_/chanx_right_out[8]
set_disable_timing sb_0__0_/chanx_right_in[8]
-set_disable_timing sb_0__0_/chanx_right_out[9]
set_disable_timing sb_0__0_/chanx_right_in[9]
set_disable_timing sb_0__0_/chanx_right_out[10]
set_disable_timing sb_0__0_/chanx_right_in[10]
@@ -688,7 +677,8 @@ set_disable_timing sb_0__0_/chanx_right_in[11]
set_disable_timing sb_0__0_/chanx_right_out[12]
set_disable_timing sb_0__0_/chanx_right_in[12]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
-set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
+set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
+set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0]
@@ -706,12 +696,13 @@ set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pi
set_disable_timing sb_0__0_/mux_top_track_0/in[0]
set_disable_timing sb_0__0_/mux_top_track_12/in[0]
set_disable_timing sb_0__0_/mux_top_track_24/in[0]
+set_disable_timing sb_0__0_/mux_top_track_0/in[1]
set_disable_timing sb_0__0_/mux_top_track_2/in[0]
set_disable_timing sb_0__0_/mux_top_track_14/in[0]
+set_disable_timing sb_0__0_/mux_top_track_2/in[1]
set_disable_timing sb_0__0_/mux_top_track_4/in[0]
set_disable_timing sb_0__0_/mux_top_track_16/in[0]
set_disable_timing sb_0__0_/mux_top_track_4/in[1]
-set_disable_timing sb_0__0_/mux_top_track_6/in[0]
set_disable_timing sb_0__0_/mux_top_track_18/in[0]
set_disable_timing sb_0__0_/mux_top_track_6/in[1]
set_disable_timing sb_0__0_/mux_top_track_8/in[0]
@@ -761,7 +752,6 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0]
set_disable_timing sb_0__0_/mux_right_track_12/in[0]
set_disable_timing sb_0__0_/mux_right_track_14/in[0]
set_disable_timing sb_0__0_/mux_right_track_16/in[0]
-set_disable_timing sb_0__0_/mux_right_track_18/in[0]
set_disable_timing sb_0__0_/mux_right_track_20/in[0]
set_disable_timing sb_0__0_/mux_right_track_24/in[0]
set_disable_timing sb_0__0_/mux_right_track_0/in[0]
@@ -787,7 +777,6 @@ set_disable_timing sb_0__1_/chanx_right_out[1]
set_disable_timing sb_0__1_/chanx_right_out[2]
set_disable_timing sb_0__1_/chanx_right_in[2]
set_disable_timing sb_0__1_/chanx_right_out[3]
-set_disable_timing sb_0__1_/chanx_right_in[3]
set_disable_timing sb_0__1_/chanx_right_out[4]
set_disable_timing sb_0__1_/chanx_right_in[4]
set_disable_timing sb_0__1_/chanx_right_out[5]
@@ -796,7 +785,6 @@ set_disable_timing sb_0__1_/chanx_right_out[6]
set_disable_timing sb_0__1_/chanx_right_in[6]
set_disable_timing sb_0__1_/chanx_right_out[7]
set_disable_timing sb_0__1_/chanx_right_in[7]
-set_disable_timing sb_0__1_/chanx_right_out[8]
set_disable_timing sb_0__1_/chanx_right_in[8]
set_disable_timing sb_0__1_/chanx_right_out[9]
set_disable_timing sb_0__1_/chanx_right_in[9]
@@ -806,11 +794,12 @@ set_disable_timing sb_0__1_/chanx_right_out[11]
set_disable_timing sb_0__1_/chanx_right_in[11]
set_disable_timing sb_0__1_/chanx_right_out[12]
set_disable_timing sb_0__1_/chanx_right_in[12]
+set_disable_timing sb_0__1_/chany_bottom_in[0]
set_disable_timing sb_0__1_/chany_bottom_out[0]
+set_disable_timing sb_0__1_/chany_bottom_in[1]
set_disable_timing sb_0__1_/chany_bottom_out[1]
set_disable_timing sb_0__1_/chany_bottom_in[2]
set_disable_timing sb_0__1_/chany_bottom_out[2]
-set_disable_timing sb_0__1_/chany_bottom_in[3]
set_disable_timing sb_0__1_/chany_bottom_out[3]
set_disable_timing sb_0__1_/chany_bottom_in[4]
set_disable_timing sb_0__1_/chany_bottom_out[4]
@@ -821,7 +810,6 @@ set_disable_timing sb_0__1_/chany_bottom_out[6]
set_disable_timing sb_0__1_/chany_bottom_in[7]
set_disable_timing sb_0__1_/chany_bottom_out[7]
set_disable_timing sb_0__1_/chany_bottom_in[8]
-set_disable_timing sb_0__1_/chany_bottom_out[8]
set_disable_timing sb_0__1_/chany_bottom_in[9]
set_disable_timing sb_0__1_/chany_bottom_out[9]
set_disable_timing sb_0__1_/chany_bottom_in[10]
@@ -840,7 +828,8 @@ set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pi
set_disable_timing sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
-set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
+set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
+set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0]
@@ -897,7 +886,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_15/in[3]
set_disable_timing sb_0__1_/mux_bottom_track_17/in[2]
set_disable_timing sb_0__1_/mux_bottom_track_23/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_19/in[0]
-set_disable_timing sb_0__1_/mux_bottom_track_17/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_15/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_13/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_11/in[0]
@@ -910,7 +898,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_25/in[0]
set_disable_timing sb_0__1_/mux_right_track_22/in[1]
set_disable_timing sb_0__1_/mux_right_track_20/in[1]
set_disable_timing sb_0__1_/mux_right_track_18/in[1]
-set_disable_timing sb_0__1_/mux_right_track_16/in[2]
set_disable_timing sb_0__1_/mux_right_track_14/in[2]
set_disable_timing sb_0__1_/mux_right_track_12/in[3]
set_disable_timing sb_0__1_/mux_right_track_10/in[2]
@@ -924,12 +911,10 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2]
# Disable timing for Switch block sb_1__0_
##################################################
set_disable_timing sb_1__0_/chany_top_in[0]
-set_disable_timing sb_1__0_/chany_top_out[1]
set_disable_timing sb_1__0_/chany_top_in[1]
set_disable_timing sb_1__0_/chany_top_in[2]
set_disable_timing sb_1__0_/chany_top_out[3]
set_disable_timing sb_1__0_/chany_top_in[3]
-set_disable_timing sb_1__0_/chany_top_out[4]
set_disable_timing sb_1__0_/chany_top_in[4]
set_disable_timing sb_1__0_/chany_top_out[5]
set_disable_timing sb_1__0_/chany_top_in[5]
@@ -965,7 +950,6 @@ set_disable_timing sb_1__0_/chanx_left_in[7]
set_disable_timing sb_1__0_/chanx_left_out[7]
set_disable_timing sb_1__0_/chanx_left_in[8]
set_disable_timing sb_1__0_/chanx_left_out[8]
-set_disable_timing sb_1__0_/chanx_left_in[9]
set_disable_timing sb_1__0_/chanx_left_out[9]
set_disable_timing sb_1__0_/chanx_left_in[10]
set_disable_timing sb_1__0_/chanx_left_out[10]
@@ -979,7 +963,6 @@ set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
-set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0]
set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0]
@@ -1010,7 +993,6 @@ set_disable_timing sb_1__0_/mux_top_track_24/in[0]
set_disable_timing sb_1__0_/mux_top_track_0/in[2]
set_disable_timing sb_1__0_/mux_top_track_12/in[1]
set_disable_timing sb_1__0_/mux_top_track_14/in[1]
-set_disable_timing sb_1__0_/mux_top_track_2/in[2]
set_disable_timing sb_1__0_/mux_top_track_14/in[2]
set_disable_timing sb_1__0_/mux_top_track_16/in[1]
set_disable_timing sb_1__0_/mux_left_track_1/in[1]
@@ -1062,19 +1044,16 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2]
set_disable_timing sb_1__0_/mux_top_track_14/in[3]
set_disable_timing sb_1__0_/mux_top_track_12/in[2]
set_disable_timing sb_1__0_/mux_top_track_10/in[2]
-set_disable_timing sb_1__0_/mux_top_track_8/in[2]
set_disable_timing sb_1__0_/mux_top_track_6/in[2]
set_disable_timing sb_1__0_/mux_top_track_2/in[3]
##################################################
# Disable timing for Switch block sb_1__1_
##################################################
set_disable_timing sb_1__1_/chany_bottom_out[0]
-set_disable_timing sb_1__1_/chany_bottom_in[1]
set_disable_timing sb_1__1_/chany_bottom_out[1]
set_disable_timing sb_1__1_/chany_bottom_out[2]
set_disable_timing sb_1__1_/chany_bottom_in[3]
set_disable_timing sb_1__1_/chany_bottom_out[3]
-set_disable_timing sb_1__1_/chany_bottom_in[4]
set_disable_timing sb_1__1_/chany_bottom_out[4]
set_disable_timing sb_1__1_/chany_bottom_in[5]
set_disable_timing sb_1__1_/chany_bottom_out[5]
@@ -1098,7 +1077,6 @@ set_disable_timing sb_1__1_/chanx_left_in[1]
set_disable_timing sb_1__1_/chanx_left_in[2]
set_disable_timing sb_1__1_/chanx_left_out[2]
set_disable_timing sb_1__1_/chanx_left_in[3]
-set_disable_timing sb_1__1_/chanx_left_out[3]
set_disable_timing sb_1__1_/chanx_left_in[4]
set_disable_timing sb_1__1_/chanx_left_out[4]
set_disable_timing sb_1__1_/chanx_left_in[5]
@@ -1107,7 +1085,6 @@ set_disable_timing sb_1__1_/chanx_left_in[6]
set_disable_timing sb_1__1_/chanx_left_out[6]
set_disable_timing sb_1__1_/chanx_left_in[7]
set_disable_timing sb_1__1_/chanx_left_out[7]
-set_disable_timing sb_1__1_/chanx_left_in[8]
set_disable_timing sb_1__1_/chanx_left_out[8]
set_disable_timing sb_1__1_/chanx_left_in[9]
set_disable_timing sb_1__1_/chanx_left_out[9]
@@ -1124,7 +1101,6 @@ set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__p
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
-set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
@@ -1185,7 +1161,6 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3]
set_disable_timing sb_1__1_/mux_left_track_15/in[2]
set_disable_timing sb_1__1_/mux_left_track_17/in[2]
set_disable_timing sb_1__1_/mux_left_track_5/in[0]
-set_disable_timing sb_1__1_/mux_left_track_7/in[0]
set_disable_timing sb_1__1_/mux_left_track_9/in[0]
set_disable_timing sb_1__1_/mux_left_track_11/in[0]
set_disable_timing sb_1__1_/mux_left_track_13/in[0]
@@ -1218,12 +1193,12 @@ set_disable_timing sb_1__1_/mux_bottom_track_23/in[1]
#######################################
# Disable unused pins for pb_graph_node clb[0]
#######################################
-set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[0]
-set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[1]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2]
+set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[3]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6]
+set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[7]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[9]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0]
@@ -1234,8 +1209,8 @@ set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_clk[0]
# Disable unused mux_inputs for pb_graph_node clb[0]
#######################################
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0]
-set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2]
+set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6]
@@ -1564,31 +1539,31 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/*
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused resources in grid[2][1][3]
-#######################################
-#######################################
-# Disable unused pins for pb_graph_node io[0]
-#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/io_inpad[0]
-#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
-#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc_0_/in[0]
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
-#######################################
-# Disable Timing for unused grid[2][1][4]
+# Disable Timing for unused grid[2][1][3]
#######################################
#######################################
# Disable all the ports for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/*
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/*
#######################################
# Disable all the ports for pb_graph_node iopad[0]
#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
+#######################################
+# Disable Timing for unused resources in grid[2][1][4]
+#######################################
+#######################################
+# Disable unused pins for pb_graph_node io[0]
+#######################################
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0]
+#######################################
+# Disable unused mux_inputs for pb_graph_node io[0]
+#######################################
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
#######################################
# Disable Timing for unused grid[2][1][5]
#######################################
@@ -1612,16 +1587,20 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/*
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused grid[2][1][7]
+# Disable Timing for unused resources in grid[2][1][7]
#######################################
#######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/*
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/io_outpad[0]
#######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7//direct_interc_1_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for grid[1][0]
#######################################
@@ -1728,46 +1707,42 @@ set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/*
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused resources in grid[0][1][1]
-#######################################
-#######################################
-# Disable unused pins for pb_graph_node io[0]
-#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/io_outpad[0]
-#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
-#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1//direct_interc_1_/in[0]
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
-#######################################
-# Disable Timing for unused resources in grid[0][1][2]
-#######################################
-#######################################
-# Disable unused pins for pb_graph_node io[0]
-#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/io_outpad[0]
-#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
-#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2//direct_interc_1_/in[0]
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
-#######################################
-# Disable Timing for unused grid[0][1][3]
+# Disable Timing for unused grid[0][1][1]
#######################################
#######################################
# Disable all the ports for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/*
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/*
#######################################
# Disable all the ports for pb_graph_node iopad[0]
#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
+#######################################
+# Disable Timing for unused grid[0][1][2]
+#######################################
+#######################################
+# Disable all the ports for pb_graph_node io[0]
+#######################################
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/*
+#######################################
+# Disable all the ports for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
+#######################################
+# Disable Timing for unused resources in grid[0][1][3]
+#######################################
+#######################################
+# Disable unused pins for pb_graph_node io[0]
+#######################################
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/io_outpad[0]
+#######################################
+# Disable unused mux_inputs for pb_graph_node io[0]
+#######################################
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3//direct_interc_1_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for unused grid[0][1][4]
#######################################
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v
index b287ec87c..237dad23a 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v
@@ -42,14 +42,14 @@ wire [0:0] clk_fm;
// ----- End Connect Global ports of FPGA top module -----
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
-// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[26] -----
- assign gfpga_pad_GPIO_PAD_fm[26] = a[0];
+// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[27] -----
+ assign gfpga_pad_GPIO_PAD_fm[27] = a[0];
-// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[25] -----
- assign gfpga_pad_GPIO_PAD_fm[25] = b[0];
+// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[15] -----
+ assign gfpga_pad_GPIO_PAD_fm[15] = b[0];
-// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] -----
- assign c[0] = gfpga_pad_GPIO_PAD_fm[11];
+// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
+ assign c[0] = gfpga_pad_GPIO_PAD_fm[12];
// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
@@ -63,10 +63,9 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0;
@@ -76,7 +75,8 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0;
@@ -125,14 +125,14 @@ initial begin
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0001;
- force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1110;
+ force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}};
+ force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0011;
- force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1100;
+ force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0111;
+ force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@@ -155,10 +155,10 @@ initial begin
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
- force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
- force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
- force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
- force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
+ force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
+ force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
+ force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
+ force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@@ -197,14 +197,14 @@ initial begin
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
- force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = 3'b011;
- force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = 3'b100;
- force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = 2'b01;
- force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = 2'b10;
+ force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
+ force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
+ force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
@@ -241,8 +241,8 @@ initial begin
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}};
@@ -265,8 +265,8 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = 2'b10;
+ force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
@@ -291,8 +291,8 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}};
@@ -303,14 +303,14 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
- force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
- force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = 3'b001;
+ force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = 3'b110;
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10;
+ force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
@@ -385,8 +385,8 @@ initial begin
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
@@ -443,16 +443,16 @@ initial begin
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
- force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = 3'b110;
+ force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = 3'b001;
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b1}};
- force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b0}};
- force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = 3'b101;
- force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = 3'b010;
+ force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
+ force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}};
+ force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
@@ -475,18 +475,18 @@ initial begin
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b1}};
- force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b0}};
- force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
- force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
+ force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101;
+ force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010;
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
- force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b1}};
+ force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}};
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit
index 5127c7105..7ed88111a 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit
@@ -3,7 +3,7 @@
// Bitstream width (LSB -> MSB): 1
1
1
-0
+1
0
0
0
@@ -14,9 +14,9 @@
0
0
1
-0
-0
-0
+1
+1
+1
0
0
0
@@ -143,12 +143,9 @@
0
0
0
-0
-0
-0
-0
-0
-0
+1
+1
+1
0
0
0
@@ -159,9 +156,8 @@
0
0
1
-1
-1
0
+1
0
0
0
@@ -261,6 +257,9 @@
0
1
1
+0
+0
+1
1
1
1
@@ -270,39 +269,6 @@
1
1
1
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-1
-0
-1
-1
-1
-1
-0
-0
-1
1
0
0
@@ -336,32 +302,10 @@
0
0
0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-1
-0
1
1
0
0
-0
-0
-0
1
1
0
@@ -405,80 +349,136 @@
0
0
0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-1
-1
-1
-1
-1
-1
-1
-1
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
+1
+1
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+1
+1
+0
+0
+1
+1
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+1
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+1
+1
+1
+1
+1
+1
+1
+1
+0
+0
+0
+0
+0
+0
+0
+1
+1
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+1
+1
+0
+0
1
1
0
@@ -515,7 +515,6 @@
1
1
1
-1
0
1
1
@@ -528,3 +527,4 @@
1
1
1
+1
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml
index 558580484..419917847 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml
@@ -10,7 +10,7 @@
-
+
@@ -32,11 +32,11 @@
-
+
-
+
-
+
@@ -290,11 +290,11 @@
-
+
-
+
-
+
@@ -314,17 +314,17 @@
-
+
-
+
-
+
-
+
-
+
@@ -506,7 +506,7 @@
-
+
@@ -516,7 +516,7 @@
-
+
@@ -592,17 +592,17 @@
-
+
-
+
-
+
-
+
-
+
@@ -616,9 +616,9 @@
-
+
-
+
@@ -702,21 +702,21 @@
-
+
-
+
-
+
-
+
-
+
@@ -736,9 +736,9 @@
-
+
-
+
@@ -796,7 +796,7 @@
-
+
@@ -864,9 +864,9 @@
-
+
-
+
@@ -954,9 +954,9 @@
-
+
-
+
@@ -1034,9 +1034,9 @@
-
+
-
+
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
index 1b97176e2..eddb1a906 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
@@ -431,14 +431,14 @@
-
-
+
+
-
+
-
+
@@ -449,10 +449,10 @@
-
-
-
-
+
+
+
+
@@ -498,14 +498,14 @@
-
-
+
+
-
+
-
+
@@ -516,9 +516,9 @@
-
+
-
+
@@ -715,7 +715,7 @@
-
+
@@ -731,7 +731,7 @@
-
+
@@ -1054,17 +1054,17 @@
-
+
-
+
-
+
-
-
+
+
@@ -1074,16 +1074,16 @@
-
-
+
+
-
+
-
+
-
+
@@ -1093,8 +1093,8 @@
-
-
+
+
@@ -1112,16 +1112,16 @@
-
+
-
+
-
-
-
+
+
+
@@ -1190,7 +1190,7 @@
-
+
@@ -1209,7 +1209,7 @@
-
+
@@ -1228,7 +1228,7 @@
-
+
@@ -1480,15 +1480,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -1713,13 +1713,13 @@
-
+
-
+
-
-
+
+
@@ -1749,7 +1749,7 @@
-
+
@@ -1767,7 +1767,7 @@
-
+
@@ -1826,7 +1826,7 @@
-
+
@@ -1846,8 +1846,8 @@
-
-
+
+
@@ -1865,8 +1865,8 @@
-
-
+
+
@@ -1884,7 +1884,7 @@
-
+
@@ -1961,16 +1961,16 @@
-
-
+
+
-
+
-
-
-
+
+
+
@@ -1981,7 +1981,7 @@
-
+
@@ -1999,7 +1999,7 @@
-
+
@@ -2077,16 +2077,16 @@
-
+
-
+
-
+
-
+
@@ -2136,13 +2136,13 @@
-
+
-
+
-
-
+
+
@@ -2193,7 +2193,7 @@
-
+
@@ -2213,7 +2213,7 @@
-
+
@@ -2559,7 +2559,7 @@
-
+
@@ -2675,7 +2675,7 @@
-
+
@@ -2695,8 +2695,8 @@
-
-
+
+
@@ -2845,7 +2845,7 @@
-
+
@@ -2869,11 +2869,11 @@
-
+
-
-
-
+
+
+
@@ -2902,7 +2902,7 @@
-
+
@@ -3128,7 +3128,7 @@
-
+
@@ -3266,7 +3266,7 @@
-
+
@@ -3287,7 +3287,7 @@
-
+
@@ -3360,7 +3360,7 @@
-
+
@@ -3382,7 +3382,7 @@
-
+
@@ -3403,7 +3403,7 @@
-
+
@@ -3498,15 +3498,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -3519,7 +3519,7 @@
-
+
@@ -3541,7 +3541,7 @@
-
+
@@ -3565,7 +3565,7 @@
-
+
@@ -3573,12 +3573,12 @@
-
+
-
-
-
-
+
+
+
+
@@ -3588,20 +3588,20 @@
-
+
-
+
-
+
-
-
+
+
-
+
@@ -3611,12 +3611,12 @@
-
+
-
+
@@ -3636,7 +3636,7 @@
-
+
@@ -3657,7 +3657,7 @@
-
+
@@ -3726,7 +3726,7 @@
-
+
@@ -3749,12 +3749,12 @@
-
+
-
+
@@ -3775,7 +3775,7 @@
-
+
@@ -3822,7 +3822,7 @@
-
+
@@ -3843,7 +3843,7 @@
-
+
@@ -3874,12 +3874,12 @@
-
+
-
-
-
-
+
+
+
+
@@ -3891,18 +3891,18 @@
-
+
-
+
-
-
+
+
-
+
@@ -3912,7 +3912,7 @@
-
+
@@ -3981,7 +3981,7 @@
-
+
@@ -3989,12 +3989,12 @@
-
+
-
-
-
-
+
+
+
+
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc
index 15b7bb175..7b26126b2 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc
@@ -14,7 +14,7 @@ set_units -time s
##################################################
# Create clock
##################################################
-create_clock -name clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10} [get_ports {clk[0]}]
+create_clock -name clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10} [get_ports {clk[0]}]
##################################################
# Create programmable clock
##################################################
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml
index 8a17b9176..e39c498fe 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml
@@ -3,7 +3,7 @@
-->
-
-
-
+
+
+
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
index 95483119a..85ed90930 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
@@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
initial begin
clk[0] <= 1'b0;
while(1) begin
- #0.5422864556
+ #0.6573184729
clk[0] <= !clk[0];
end
end
@@ -109,7 +109,7 @@ initial begin
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
- #7.592010975
+ #9.202458382
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
index c10622702..7053e16d9 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
@@ -9,14 +9,14 @@
##################################################
# Create clock
##################################################
-create_clock clk[0] -period 1.084572876e-09 -waveform {0 5.42286438e-10}
+create_clock clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10}
##################################################
# Create input and output delays for used I/Os
##################################################
-set_input_delay -clock clk[0] -max 1.084572876e-09 gfpga_pad_GPIO_PAD[13]
-set_input_delay -clock clk[0] -max 1.084572876e-09 gfpga_pad_GPIO_PAD[12]
-set_output_delay -clock clk[0] -max 1.084572876e-09 gfpga_pad_GPIO_PAD[10]
+set_input_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[38]
+set_input_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[58]
+set_output_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[17]
##################################################
# Disable timing for unused I/Os
@@ -31,11 +31,13 @@ set_disable_timing gfpga_pad_GPIO_PAD[6]
set_disable_timing gfpga_pad_GPIO_PAD[7]
set_disable_timing gfpga_pad_GPIO_PAD[8]
set_disable_timing gfpga_pad_GPIO_PAD[9]
+set_disable_timing gfpga_pad_GPIO_PAD[10]
set_disable_timing gfpga_pad_GPIO_PAD[11]
+set_disable_timing gfpga_pad_GPIO_PAD[12]
+set_disable_timing gfpga_pad_GPIO_PAD[13]
set_disable_timing gfpga_pad_GPIO_PAD[14]
set_disable_timing gfpga_pad_GPIO_PAD[15]
set_disable_timing gfpga_pad_GPIO_PAD[16]
-set_disable_timing gfpga_pad_GPIO_PAD[17]
set_disable_timing gfpga_pad_GPIO_PAD[18]
set_disable_timing gfpga_pad_GPIO_PAD[19]
set_disable_timing gfpga_pad_GPIO_PAD[20]
@@ -56,7 +58,6 @@ set_disable_timing gfpga_pad_GPIO_PAD[34]
set_disable_timing gfpga_pad_GPIO_PAD[35]
set_disable_timing gfpga_pad_GPIO_PAD[36]
set_disable_timing gfpga_pad_GPIO_PAD[37]
-set_disable_timing gfpga_pad_GPIO_PAD[38]
set_disable_timing gfpga_pad_GPIO_PAD[39]
set_disable_timing gfpga_pad_GPIO_PAD[40]
set_disable_timing gfpga_pad_GPIO_PAD[41]
@@ -76,7 +77,6 @@ set_disable_timing gfpga_pad_GPIO_PAD[54]
set_disable_timing gfpga_pad_GPIO_PAD[55]
set_disable_timing gfpga_pad_GPIO_PAD[56]
set_disable_timing gfpga_pad_GPIO_PAD[57]
-set_disable_timing gfpga_pad_GPIO_PAD[58]
set_disable_timing gfpga_pad_GPIO_PAD[59]
set_disable_timing gfpga_pad_GPIO_PAD[60]
set_disable_timing gfpga_pad_GPIO_PAD[61]
@@ -397,6 +397,7 @@ set_disable_timing cbx_1__0_/mux_top_ipin_6/in[2]
set_disable_timing cbx_1__1_/chanx_left_in[0]
set_disable_timing cbx_1__1_/chanx_right_in[0]
set_disable_timing cbx_1__1_/chanx_left_in[1]
+set_disable_timing cbx_1__1_/chanx_right_in[1]
set_disable_timing cbx_1__1_/chanx_left_in[2]
set_disable_timing cbx_1__1_/chanx_right_in[2]
set_disable_timing cbx_1__1_/chanx_left_in[3]
@@ -416,6 +417,7 @@ set_disable_timing cbx_1__1_/chanx_right_in[9]
set_disable_timing cbx_1__1_/chanx_left_out[0]
set_disable_timing cbx_1__1_/chanx_right_out[0]
set_disable_timing cbx_1__1_/chanx_left_out[1]
+set_disable_timing cbx_1__1_/chanx_right_out[1]
set_disable_timing cbx_1__1_/chanx_left_out[2]
set_disable_timing cbx_1__1_/chanx_right_out[2]
set_disable_timing cbx_1__1_/chanx_left_out[3]
@@ -466,7 +468,6 @@ set_disable_timing cbx_1__2_/chanx_right_in[0]
set_disable_timing cbx_1__2_/chanx_left_in[1]
set_disable_timing cbx_1__2_/chanx_right_in[1]
set_disable_timing cbx_1__2_/chanx_left_in[2]
-set_disable_timing cbx_1__2_/chanx_right_in[2]
set_disable_timing cbx_1__2_/chanx_left_in[3]
set_disable_timing cbx_1__2_/chanx_right_in[3]
set_disable_timing cbx_1__2_/chanx_left_in[4]
@@ -476,7 +477,6 @@ set_disable_timing cbx_1__2_/chanx_right_in[5]
set_disable_timing cbx_1__2_/chanx_left_in[6]
set_disable_timing cbx_1__2_/chanx_right_in[6]
set_disable_timing cbx_1__2_/chanx_left_in[7]
-set_disable_timing cbx_1__2_/chanx_right_in[7]
set_disable_timing cbx_1__2_/chanx_left_in[8]
set_disable_timing cbx_1__2_/chanx_right_in[8]
set_disable_timing cbx_1__2_/chanx_left_in[9]
@@ -486,7 +486,6 @@ set_disable_timing cbx_1__2_/chanx_right_out[0]
set_disable_timing cbx_1__2_/chanx_left_out[1]
set_disable_timing cbx_1__2_/chanx_right_out[1]
set_disable_timing cbx_1__2_/chanx_left_out[2]
-set_disable_timing cbx_1__2_/chanx_right_out[2]
set_disable_timing cbx_1__2_/chanx_left_out[3]
set_disable_timing cbx_1__2_/chanx_right_out[3]
set_disable_timing cbx_1__2_/chanx_left_out[4]
@@ -496,7 +495,6 @@ set_disable_timing cbx_1__2_/chanx_right_out[5]
set_disable_timing cbx_1__2_/chanx_left_out[6]
set_disable_timing cbx_1__2_/chanx_right_out[6]
set_disable_timing cbx_1__2_/chanx_left_out[7]
-set_disable_timing cbx_1__2_/chanx_right_out[7]
set_disable_timing cbx_1__2_/chanx_left_out[8]
set_disable_timing cbx_1__2_/chanx_right_out[8]
set_disable_timing cbx_1__2_/chanx_left_out[9]
@@ -610,12 +608,15 @@ set_disable_timing cbx_1__4_/chanx_right_in[3]
set_disable_timing cbx_1__4_/chanx_left_in[4]
set_disable_timing cbx_1__4_/chanx_right_in[4]
set_disable_timing cbx_1__4_/chanx_left_in[5]
+set_disable_timing cbx_1__4_/chanx_right_in[5]
+set_disable_timing cbx_1__4_/chanx_left_in[6]
set_disable_timing cbx_1__4_/chanx_right_in[6]
set_disable_timing cbx_1__4_/chanx_left_in[7]
set_disable_timing cbx_1__4_/chanx_right_in[7]
set_disable_timing cbx_1__4_/chanx_left_in[8]
set_disable_timing cbx_1__4_/chanx_right_in[8]
set_disable_timing cbx_1__4_/chanx_left_in[9]
+set_disable_timing cbx_1__4_/chanx_right_in[9]
set_disable_timing cbx_1__4_/chanx_left_out[0]
set_disable_timing cbx_1__4_/chanx_right_out[0]
set_disable_timing cbx_1__4_/chanx_left_out[1]
@@ -627,12 +628,15 @@ set_disable_timing cbx_1__4_/chanx_right_out[3]
set_disable_timing cbx_1__4_/chanx_left_out[4]
set_disable_timing cbx_1__4_/chanx_right_out[4]
set_disable_timing cbx_1__4_/chanx_left_out[5]
+set_disable_timing cbx_1__4_/chanx_right_out[5]
+set_disable_timing cbx_1__4_/chanx_left_out[6]
set_disable_timing cbx_1__4_/chanx_right_out[6]
set_disable_timing cbx_1__4_/chanx_left_out[7]
set_disable_timing cbx_1__4_/chanx_right_out[7]
set_disable_timing cbx_1__4_/chanx_left_out[8]
set_disable_timing cbx_1__4_/chanx_right_out[8]
set_disable_timing cbx_1__4_/chanx_left_out[9]
+set_disable_timing cbx_1__4_/chanx_right_out[9]
set_disable_timing cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0]
@@ -786,12 +790,12 @@ set_disable_timing cbx_2__0_/mux_top_ipin_6/in[2]
# Disable timing for Connection block cbx_1__1_
##################################################
set_disable_timing cbx_2__1_/chanx_left_in[0]
+set_disable_timing cbx_2__1_/chanx_right_in[0]
set_disable_timing cbx_2__1_/chanx_left_in[1]
set_disable_timing cbx_2__1_/chanx_right_in[1]
set_disable_timing cbx_2__1_/chanx_left_in[2]
set_disable_timing cbx_2__1_/chanx_right_in[2]
set_disable_timing cbx_2__1_/chanx_left_in[3]
-set_disable_timing cbx_2__1_/chanx_right_in[3]
set_disable_timing cbx_2__1_/chanx_left_in[4]
set_disable_timing cbx_2__1_/chanx_right_in[4]
set_disable_timing cbx_2__1_/chanx_left_in[5]
@@ -805,12 +809,12 @@ set_disable_timing cbx_2__1_/chanx_right_in[8]
set_disable_timing cbx_2__1_/chanx_left_in[9]
set_disable_timing cbx_2__1_/chanx_right_in[9]
set_disable_timing cbx_2__1_/chanx_left_out[0]
+set_disable_timing cbx_2__1_/chanx_right_out[0]
set_disable_timing cbx_2__1_/chanx_left_out[1]
set_disable_timing cbx_2__1_/chanx_right_out[1]
set_disable_timing cbx_2__1_/chanx_left_out[2]
set_disable_timing cbx_2__1_/chanx_right_out[2]
set_disable_timing cbx_2__1_/chanx_left_out[3]
-set_disable_timing cbx_2__1_/chanx_right_out[3]
set_disable_timing cbx_2__1_/chanx_left_out[4]
set_disable_timing cbx_2__1_/chanx_right_out[4]
set_disable_timing cbx_2__1_/chanx_left_out[5]
@@ -855,7 +859,6 @@ set_disable_timing cbx_2__1_/mux_top_ipin_1/in[2]
set_disable_timing cbx_2__2_/chanx_left_in[0]
set_disable_timing cbx_2__2_/chanx_right_in[0]
set_disable_timing cbx_2__2_/chanx_left_in[1]
-set_disable_timing cbx_2__2_/chanx_right_in[1]
set_disable_timing cbx_2__2_/chanx_left_in[2]
set_disable_timing cbx_2__2_/chanx_right_in[2]
set_disable_timing cbx_2__2_/chanx_left_in[3]
@@ -865,7 +868,6 @@ set_disable_timing cbx_2__2_/chanx_right_in[4]
set_disable_timing cbx_2__2_/chanx_left_in[5]
set_disable_timing cbx_2__2_/chanx_right_in[5]
set_disable_timing cbx_2__2_/chanx_left_in[6]
-set_disable_timing cbx_2__2_/chanx_right_in[6]
set_disable_timing cbx_2__2_/chanx_left_in[7]
set_disable_timing cbx_2__2_/chanx_right_in[7]
set_disable_timing cbx_2__2_/chanx_left_in[8]
@@ -875,7 +877,6 @@ set_disable_timing cbx_2__2_/chanx_right_in[9]
set_disable_timing cbx_2__2_/chanx_left_out[0]
set_disable_timing cbx_2__2_/chanx_right_out[0]
set_disable_timing cbx_2__2_/chanx_left_out[1]
-set_disable_timing cbx_2__2_/chanx_right_out[1]
set_disable_timing cbx_2__2_/chanx_left_out[2]
set_disable_timing cbx_2__2_/chanx_right_out[2]
set_disable_timing cbx_2__2_/chanx_left_out[3]
@@ -885,7 +886,6 @@ set_disable_timing cbx_2__2_/chanx_right_out[4]
set_disable_timing cbx_2__2_/chanx_left_out[5]
set_disable_timing cbx_2__2_/chanx_right_out[5]
set_disable_timing cbx_2__2_/chanx_left_out[6]
-set_disable_timing cbx_2__2_/chanx_right_out[6]
set_disable_timing cbx_2__2_/chanx_left_out[7]
set_disable_timing cbx_2__2_/chanx_right_out[7]
set_disable_timing cbx_2__2_/chanx_left_out[8]
@@ -936,7 +936,6 @@ set_disable_timing cbx_2__3_/chanx_right_in[5]
set_disable_timing cbx_2__3_/chanx_left_in[6]
set_disable_timing cbx_2__3_/chanx_right_in[6]
set_disable_timing cbx_2__3_/chanx_left_in[7]
-set_disable_timing cbx_2__3_/chanx_right_in[7]
set_disable_timing cbx_2__3_/chanx_left_in[8]
set_disable_timing cbx_2__3_/chanx_right_in[8]
set_disable_timing cbx_2__3_/chanx_left_in[9]
@@ -956,7 +955,6 @@ set_disable_timing cbx_2__3_/chanx_right_out[5]
set_disable_timing cbx_2__3_/chanx_left_out[6]
set_disable_timing cbx_2__3_/chanx_right_out[6]
set_disable_timing cbx_2__3_/chanx_left_out[7]
-set_disable_timing cbx_2__3_/chanx_right_out[7]
set_disable_timing cbx_2__3_/chanx_left_out[8]
set_disable_timing cbx_2__3_/chanx_right_out[8]
set_disable_timing cbx_2__3_/chanx_left_out[9]
@@ -990,7 +988,6 @@ set_disable_timing cbx_2__3_/mux_top_ipin_1/in[2]
##################################################
# Disable timing for Connection block cbx_1__4_
##################################################
-set_disable_timing cbx_2__4_/chanx_left_in[0]
set_disable_timing cbx_2__4_/chanx_right_in[0]
set_disable_timing cbx_2__4_/chanx_left_in[1]
set_disable_timing cbx_2__4_/chanx_right_in[1]
@@ -999,15 +996,17 @@ set_disable_timing cbx_2__4_/chanx_right_in[2]
set_disable_timing cbx_2__4_/chanx_left_in[3]
set_disable_timing cbx_2__4_/chanx_right_in[3]
set_disable_timing cbx_2__4_/chanx_left_in[4]
+set_disable_timing cbx_2__4_/chanx_right_in[4]
set_disable_timing cbx_2__4_/chanx_left_in[5]
set_disable_timing cbx_2__4_/chanx_right_in[5]
set_disable_timing cbx_2__4_/chanx_left_in[6]
set_disable_timing cbx_2__4_/chanx_right_in[6]
+set_disable_timing cbx_2__4_/chanx_left_in[7]
set_disable_timing cbx_2__4_/chanx_right_in[7]
set_disable_timing cbx_2__4_/chanx_left_in[8]
+set_disable_timing cbx_2__4_/chanx_right_in[8]
set_disable_timing cbx_2__4_/chanx_left_in[9]
set_disable_timing cbx_2__4_/chanx_right_in[9]
-set_disable_timing cbx_2__4_/chanx_left_out[0]
set_disable_timing cbx_2__4_/chanx_right_out[0]
set_disable_timing cbx_2__4_/chanx_left_out[1]
set_disable_timing cbx_2__4_/chanx_right_out[1]
@@ -1016,21 +1015,27 @@ set_disable_timing cbx_2__4_/chanx_right_out[2]
set_disable_timing cbx_2__4_/chanx_left_out[3]
set_disable_timing cbx_2__4_/chanx_right_out[3]
set_disable_timing cbx_2__4_/chanx_left_out[4]
+set_disable_timing cbx_2__4_/chanx_right_out[4]
set_disable_timing cbx_2__4_/chanx_left_out[5]
set_disable_timing cbx_2__4_/chanx_right_out[5]
set_disable_timing cbx_2__4_/chanx_left_out[6]
set_disable_timing cbx_2__4_/chanx_right_out[6]
+set_disable_timing cbx_2__4_/chanx_left_out[7]
set_disable_timing cbx_2__4_/chanx_right_out[7]
set_disable_timing cbx_2__4_/chanx_left_out[8]
+set_disable_timing cbx_2__4_/chanx_right_out[8]
set_disable_timing cbx_2__4_/chanx_left_out[9]
set_disable_timing cbx_2__4_/chanx_right_out[9]
set_disable_timing cbx_2__4_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cbx_2__4_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0]
+set_disable_timing cbx_2__4_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0]
set_disable_timing cbx_2__4_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0]
set_disable_timing cbx_2__4_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0]
set_disable_timing cbx_2__4_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cbx_2__4_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cbx_2__4_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0]
+set_disable_timing cbx_2__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0]
+set_disable_timing cbx_2__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0]
set_disable_timing cbx_2__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0]
set_disable_timing cbx_2__4_/mux_bottom_ipin_0/in[1]
set_disable_timing cbx_2__4_/mux_bottom_ipin_5/in[1]
@@ -1053,6 +1058,7 @@ set_disable_timing cbx_2__4_/mux_top_ipin_0/in[0]
set_disable_timing cbx_2__4_/mux_bottom_ipin_4/in[1]
set_disable_timing cbx_2__4_/mux_top_ipin_1/in[1]
set_disable_timing cbx_2__4_/mux_bottom_ipin_4/in[0]
+set_disable_timing cbx_2__4_/mux_top_ipin_1/in[0]
set_disable_timing cbx_2__4_/mux_bottom_ipin_0/in[3]
set_disable_timing cbx_2__4_/mux_bottom_ipin_5/in[3]
set_disable_timing cbx_2__4_/mux_bottom_ipin_0/in[2]
@@ -1061,12 +1067,14 @@ set_disable_timing cbx_2__4_/mux_bottom_ipin_1/in[3]
set_disable_timing cbx_2__4_/mux_bottom_ipin_6/in[3]
set_disable_timing cbx_2__4_/mux_bottom_ipin_1/in[2]
set_disable_timing cbx_2__4_/mux_bottom_ipin_6/in[2]
+set_disable_timing cbx_2__4_/mux_bottom_ipin_2/in[3]
set_disable_timing cbx_2__4_/mux_bottom_ipin_7/in[3]
set_disable_timing cbx_2__4_/mux_bottom_ipin_2/in[2]
set_disable_timing cbx_2__4_/mux_bottom_ipin_7/in[2]
set_disable_timing cbx_2__4_/mux_bottom_ipin_3/in[3]
set_disable_timing cbx_2__4_/mux_top_ipin_0/in[3]
set_disable_timing cbx_2__4_/mux_bottom_ipin_3/in[2]
+set_disable_timing cbx_2__4_/mux_top_ipin_0/in[2]
set_disable_timing cbx_2__4_/mux_bottom_ipin_4/in[3]
set_disable_timing cbx_2__4_/mux_top_ipin_1/in[3]
set_disable_timing cbx_2__4_/mux_bottom_ipin_4/in[2]
@@ -1175,7 +1183,6 @@ set_disable_timing cbx_3__1_/chanx_right_in[0]
set_disable_timing cbx_3__1_/chanx_left_in[1]
set_disable_timing cbx_3__1_/chanx_right_in[1]
set_disable_timing cbx_3__1_/chanx_left_in[2]
-set_disable_timing cbx_3__1_/chanx_right_in[2]
set_disable_timing cbx_3__1_/chanx_left_in[3]
set_disable_timing cbx_3__1_/chanx_right_in[3]
set_disable_timing cbx_3__1_/chanx_left_in[4]
@@ -1195,7 +1202,6 @@ set_disable_timing cbx_3__1_/chanx_right_out[0]
set_disable_timing cbx_3__1_/chanx_left_out[1]
set_disable_timing cbx_3__1_/chanx_right_out[1]
set_disable_timing cbx_3__1_/chanx_left_out[2]
-set_disable_timing cbx_3__1_/chanx_right_out[2]
set_disable_timing cbx_3__1_/chanx_left_out[3]
set_disable_timing cbx_3__1_/chanx_right_out[3]
set_disable_timing cbx_3__1_/chanx_left_out[4]
@@ -1240,7 +1246,6 @@ set_disable_timing cbx_3__1_/mux_top_ipin_1/in[2]
# Disable timing for Connection block cbx_1__1_
##################################################
set_disable_timing cbx_3__2_/chanx_left_in[0]
-set_disable_timing cbx_3__2_/chanx_right_in[0]
set_disable_timing cbx_3__2_/chanx_left_in[1]
set_disable_timing cbx_3__2_/chanx_right_in[1]
set_disable_timing cbx_3__2_/chanx_left_in[2]
@@ -1250,7 +1255,6 @@ set_disable_timing cbx_3__2_/chanx_right_in[3]
set_disable_timing cbx_3__2_/chanx_left_in[4]
set_disable_timing cbx_3__2_/chanx_right_in[4]
set_disable_timing cbx_3__2_/chanx_left_in[5]
-set_disable_timing cbx_3__2_/chanx_right_in[5]
set_disable_timing cbx_3__2_/chanx_left_in[6]
set_disable_timing cbx_3__2_/chanx_right_in[6]
set_disable_timing cbx_3__2_/chanx_left_in[7]
@@ -1260,7 +1264,6 @@ set_disable_timing cbx_3__2_/chanx_right_in[8]
set_disable_timing cbx_3__2_/chanx_left_in[9]
set_disable_timing cbx_3__2_/chanx_right_in[9]
set_disable_timing cbx_3__2_/chanx_left_out[0]
-set_disable_timing cbx_3__2_/chanx_right_out[0]
set_disable_timing cbx_3__2_/chanx_left_out[1]
set_disable_timing cbx_3__2_/chanx_right_out[1]
set_disable_timing cbx_3__2_/chanx_left_out[2]
@@ -1270,7 +1273,6 @@ set_disable_timing cbx_3__2_/chanx_right_out[3]
set_disable_timing cbx_3__2_/chanx_left_out[4]
set_disable_timing cbx_3__2_/chanx_right_out[4]
set_disable_timing cbx_3__2_/chanx_left_out[5]
-set_disable_timing cbx_3__2_/chanx_right_out[5]
set_disable_timing cbx_3__2_/chanx_left_out[6]
set_disable_timing cbx_3__2_/chanx_right_out[6]
set_disable_timing cbx_3__2_/chanx_left_out[7]
@@ -1321,7 +1323,6 @@ set_disable_timing cbx_3__3_/chanx_right_in[4]
set_disable_timing cbx_3__3_/chanx_left_in[5]
set_disable_timing cbx_3__3_/chanx_right_in[5]
set_disable_timing cbx_3__3_/chanx_left_in[6]
-set_disable_timing cbx_3__3_/chanx_right_in[6]
set_disable_timing cbx_3__3_/chanx_left_in[7]
set_disable_timing cbx_3__3_/chanx_right_in[7]
set_disable_timing cbx_3__3_/chanx_left_in[8]
@@ -1341,7 +1342,6 @@ set_disable_timing cbx_3__3_/chanx_right_out[4]
set_disable_timing cbx_3__3_/chanx_left_out[5]
set_disable_timing cbx_3__3_/chanx_right_out[5]
set_disable_timing cbx_3__3_/chanx_left_out[6]
-set_disable_timing cbx_3__3_/chanx_right_out[6]
set_disable_timing cbx_3__3_/chanx_left_out[7]
set_disable_timing cbx_3__3_/chanx_right_out[7]
set_disable_timing cbx_3__3_/chanx_left_out[8]
@@ -1379,7 +1379,6 @@ set_disable_timing cbx_3__3_/mux_top_ipin_1/in[2]
##################################################
set_disable_timing cbx_3__4_/chanx_left_in[0]
set_disable_timing cbx_3__4_/chanx_right_in[0]
-set_disable_timing cbx_3__4_/chanx_left_in[1]
set_disable_timing cbx_3__4_/chanx_right_in[1]
set_disable_timing cbx_3__4_/chanx_left_in[2]
set_disable_timing cbx_3__4_/chanx_right_in[2]
@@ -1399,7 +1398,6 @@ set_disable_timing cbx_3__4_/chanx_left_in[9]
set_disable_timing cbx_3__4_/chanx_right_in[9]
set_disable_timing cbx_3__4_/chanx_left_out[0]
set_disable_timing cbx_3__4_/chanx_right_out[0]
-set_disable_timing cbx_3__4_/chanx_left_out[1]
set_disable_timing cbx_3__4_/chanx_right_out[1]
set_disable_timing cbx_3__4_/chanx_left_out[2]
set_disable_timing cbx_3__4_/chanx_right_out[2]
@@ -1418,7 +1416,6 @@ set_disable_timing cbx_3__4_/chanx_right_out[8]
set_disable_timing cbx_3__4_/chanx_left_out[9]
set_disable_timing cbx_3__4_/chanx_right_out[9]
set_disable_timing cbx_3__4_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0]
-set_disable_timing cbx_3__4_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cbx_3__4_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0]
set_disable_timing cbx_3__4_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0]
set_disable_timing cbx_3__4_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0]
@@ -1434,7 +1431,6 @@ set_disable_timing cbx_3__4_/mux_top_ipin_2/in[1]
set_disable_timing cbx_3__4_/mux_bottom_ipin_0/in[0]
set_disable_timing cbx_3__4_/mux_bottom_ipin_5/in[0]
set_disable_timing cbx_3__4_/mux_top_ipin_2/in[0]
-set_disable_timing cbx_3__4_/mux_bottom_ipin_1/in[1]
set_disable_timing cbx_3__4_/mux_bottom_ipin_6/in[1]
set_disable_timing cbx_3__4_/mux_bottom_ipin_1/in[0]
set_disable_timing cbx_3__4_/mux_bottom_ipin_6/in[0]
@@ -1572,7 +1568,6 @@ set_disable_timing cbx_4__0_/mux_top_ipin_6/in[2]
set_disable_timing cbx_4__1_/chanx_left_in[0]
set_disable_timing cbx_4__1_/chanx_right_in[0]
set_disable_timing cbx_4__1_/chanx_left_in[1]
-set_disable_timing cbx_4__1_/chanx_right_in[1]
set_disable_timing cbx_4__1_/chanx_left_in[2]
set_disable_timing cbx_4__1_/chanx_right_in[2]
set_disable_timing cbx_4__1_/chanx_left_in[3]
@@ -1592,7 +1587,6 @@ set_disable_timing cbx_4__1_/chanx_right_in[9]
set_disable_timing cbx_4__1_/chanx_left_out[0]
set_disable_timing cbx_4__1_/chanx_right_out[0]
set_disable_timing cbx_4__1_/chanx_left_out[1]
-set_disable_timing cbx_4__1_/chanx_right_out[1]
set_disable_timing cbx_4__1_/chanx_left_out[2]
set_disable_timing cbx_4__1_/chanx_right_out[2]
set_disable_timing cbx_4__1_/chanx_left_out[3]
@@ -1647,7 +1641,6 @@ set_disable_timing cbx_4__2_/chanx_right_in[2]
set_disable_timing cbx_4__2_/chanx_left_in[3]
set_disable_timing cbx_4__2_/chanx_right_in[3]
set_disable_timing cbx_4__2_/chanx_left_in[4]
-set_disable_timing cbx_4__2_/chanx_right_in[4]
set_disable_timing cbx_4__2_/chanx_left_in[5]
set_disable_timing cbx_4__2_/chanx_right_in[5]
set_disable_timing cbx_4__2_/chanx_left_in[6]
@@ -1667,7 +1660,6 @@ set_disable_timing cbx_4__2_/chanx_right_out[2]
set_disable_timing cbx_4__2_/chanx_left_out[3]
set_disable_timing cbx_4__2_/chanx_right_out[3]
set_disable_timing cbx_4__2_/chanx_left_out[4]
-set_disable_timing cbx_4__2_/chanx_right_out[4]
set_disable_timing cbx_4__2_/chanx_left_out[5]
set_disable_timing cbx_4__2_/chanx_right_out[5]
set_disable_timing cbx_4__2_/chanx_left_out[6]
@@ -1718,7 +1710,6 @@ set_disable_timing cbx_4__3_/chanx_right_in[3]
set_disable_timing cbx_4__3_/chanx_left_in[4]
set_disable_timing cbx_4__3_/chanx_right_in[4]
set_disable_timing cbx_4__3_/chanx_left_in[5]
-set_disable_timing cbx_4__3_/chanx_right_in[5]
set_disable_timing cbx_4__3_/chanx_left_in[6]
set_disable_timing cbx_4__3_/chanx_right_in[6]
set_disable_timing cbx_4__3_/chanx_left_in[7]
@@ -1738,7 +1729,6 @@ set_disable_timing cbx_4__3_/chanx_right_out[3]
set_disable_timing cbx_4__3_/chanx_left_out[4]
set_disable_timing cbx_4__3_/chanx_right_out[4]
set_disable_timing cbx_4__3_/chanx_left_out[5]
-set_disable_timing cbx_4__3_/chanx_right_out[5]
set_disable_timing cbx_4__3_/chanx_left_out[6]
set_disable_timing cbx_4__3_/chanx_right_out[6]
set_disable_timing cbx_4__3_/chanx_left_out[7]
@@ -1752,7 +1742,6 @@ set_disable_timing cbx_4__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6
set_disable_timing cbx_4__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0]
set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0]
set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0]
-set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0]
set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[1]
set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[0]
set_disable_timing cbx_4__3_/mux_bottom_ipin_1/in[1]
@@ -1766,7 +1755,6 @@ set_disable_timing cbx_4__3_/mux_top_ipin_1/in[0]
set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[3]
set_disable_timing cbx_4__3_/mux_top_ipin_2/in[1]
set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[2]
-set_disable_timing cbx_4__3_/mux_top_ipin_2/in[0]
set_disable_timing cbx_4__3_/mux_bottom_ipin_2/in[3]
set_disable_timing cbx_4__3_/mux_bottom_ipin_2/in[2]
set_disable_timing cbx_4__3_/mux_top_ipin_0/in[3]
@@ -1780,7 +1768,6 @@ set_disable_timing cbx_4__4_/chanx_left_in[0]
set_disable_timing cbx_4__4_/chanx_right_in[0]
set_disable_timing cbx_4__4_/chanx_left_in[1]
set_disable_timing cbx_4__4_/chanx_right_in[1]
-set_disable_timing cbx_4__4_/chanx_left_in[2]
set_disable_timing cbx_4__4_/chanx_right_in[2]
set_disable_timing cbx_4__4_/chanx_left_in[3]
set_disable_timing cbx_4__4_/chanx_right_in[3]
@@ -1800,7 +1787,6 @@ set_disable_timing cbx_4__4_/chanx_left_out[0]
set_disable_timing cbx_4__4_/chanx_right_out[0]
set_disable_timing cbx_4__4_/chanx_left_out[1]
set_disable_timing cbx_4__4_/chanx_right_out[1]
-set_disable_timing cbx_4__4_/chanx_left_out[2]
set_disable_timing cbx_4__4_/chanx_right_out[2]
set_disable_timing cbx_4__4_/chanx_left_out[3]
set_disable_timing cbx_4__4_/chanx_right_out[3]
@@ -1963,6 +1949,7 @@ set_disable_timing cby_0__1_/mux_right_ipin_7/in[2]
##################################################
# Disable timing for Connection block cby_0__1_
##################################################
+set_disable_timing cby_0__2_/chany_bottom_in[0]
set_disable_timing cby_0__2_/chany_top_in[0]
set_disable_timing cby_0__2_/chany_bottom_in[1]
set_disable_timing cby_0__2_/chany_top_in[1]
@@ -1982,6 +1969,7 @@ set_disable_timing cby_0__2_/chany_bottom_in[8]
set_disable_timing cby_0__2_/chany_top_in[8]
set_disable_timing cby_0__2_/chany_bottom_in[9]
set_disable_timing cby_0__2_/chany_top_in[9]
+set_disable_timing cby_0__2_/chany_bottom_out[0]
set_disable_timing cby_0__2_/chany_top_out[0]
set_disable_timing cby_0__2_/chany_bottom_out[1]
set_disable_timing cby_0__2_/chany_top_out[1]
@@ -2054,6 +2042,7 @@ set_disable_timing cby_0__2_/mux_right_ipin_7/in[2]
##################################################
set_disable_timing cby_0__3_/chany_bottom_in[0]
set_disable_timing cby_0__3_/chany_top_in[0]
+set_disable_timing cby_0__3_/chany_bottom_in[1]
set_disable_timing cby_0__3_/chany_top_in[1]
set_disable_timing cby_0__3_/chany_bottom_in[2]
set_disable_timing cby_0__3_/chany_top_in[2]
@@ -2073,6 +2062,7 @@ set_disable_timing cby_0__3_/chany_bottom_in[9]
set_disable_timing cby_0__3_/chany_top_in[9]
set_disable_timing cby_0__3_/chany_bottom_out[0]
set_disable_timing cby_0__3_/chany_top_out[0]
+set_disable_timing cby_0__3_/chany_bottom_out[1]
set_disable_timing cby_0__3_/chany_top_out[1]
set_disable_timing cby_0__3_/chany_bottom_out[2]
set_disable_timing cby_0__3_/chany_top_out[2]
@@ -2145,6 +2135,7 @@ set_disable_timing cby_0__4_/chany_bottom_in[0]
set_disable_timing cby_0__4_/chany_top_in[0]
set_disable_timing cby_0__4_/chany_bottom_in[1]
set_disable_timing cby_0__4_/chany_top_in[1]
+set_disable_timing cby_0__4_/chany_bottom_in[2]
set_disable_timing cby_0__4_/chany_top_in[2]
set_disable_timing cby_0__4_/chany_bottom_in[3]
set_disable_timing cby_0__4_/chany_top_in[3]
@@ -2164,6 +2155,7 @@ set_disable_timing cby_0__4_/chany_bottom_out[0]
set_disable_timing cby_0__4_/chany_top_out[0]
set_disable_timing cby_0__4_/chany_bottom_out[1]
set_disable_timing cby_0__4_/chany_top_out[1]
+set_disable_timing cby_0__4_/chany_bottom_out[2]
set_disable_timing cby_0__4_/chany_top_out[2]
set_disable_timing cby_0__4_/chany_bottom_out[3]
set_disable_timing cby_0__4_/chany_top_out[3]
@@ -2354,7 +2346,6 @@ set_disable_timing cby_1__2_/mux_right_ipin_0/in[2]
##################################################
# Disable timing for Connection block cby_1__1_
##################################################
-set_disable_timing cby_1__3_/chany_bottom_in[0]
set_disable_timing cby_1__3_/chany_top_in[0]
set_disable_timing cby_1__3_/chany_bottom_in[1]
set_disable_timing cby_1__3_/chany_top_in[1]
@@ -2374,7 +2365,6 @@ set_disable_timing cby_1__3_/chany_bottom_in[8]
set_disable_timing cby_1__3_/chany_top_in[8]
set_disable_timing cby_1__3_/chany_bottom_in[9]
set_disable_timing cby_1__3_/chany_top_in[9]
-set_disable_timing cby_1__3_/chany_bottom_out[0]
set_disable_timing cby_1__3_/chany_top_out[0]
set_disable_timing cby_1__3_/chany_bottom_out[1]
set_disable_timing cby_1__3_/chany_top_out[1]
@@ -2418,7 +2408,6 @@ set_disable_timing cby_1__3_/mux_right_ipin_0/in[2]
##################################################
set_disable_timing cby_1__4_/chany_bottom_in[0]
set_disable_timing cby_1__4_/chany_top_in[0]
-set_disable_timing cby_1__4_/chany_bottom_in[1]
set_disable_timing cby_1__4_/chany_top_in[1]
set_disable_timing cby_1__4_/chany_bottom_in[2]
set_disable_timing cby_1__4_/chany_top_in[2]
@@ -2438,7 +2427,6 @@ set_disable_timing cby_1__4_/chany_bottom_in[9]
set_disable_timing cby_1__4_/chany_top_in[9]
set_disable_timing cby_1__4_/chany_bottom_out[0]
set_disable_timing cby_1__4_/chany_top_out[0]
-set_disable_timing cby_1__4_/chany_bottom_out[1]
set_disable_timing cby_1__4_/chany_top_out[1]
set_disable_timing cby_1__4_/chany_bottom_out[2]
set_disable_timing cby_1__4_/chany_top_out[2]
@@ -2547,6 +2535,7 @@ set_disable_timing cby_2__2_/chany_top_in[1]
set_disable_timing cby_2__2_/chany_bottom_in[2]
set_disable_timing cby_2__2_/chany_top_in[2]
set_disable_timing cby_2__2_/chany_bottom_in[3]
+set_disable_timing cby_2__2_/chany_top_in[3]
set_disable_timing cby_2__2_/chany_bottom_in[4]
set_disable_timing cby_2__2_/chany_top_in[4]
set_disable_timing cby_2__2_/chany_bottom_in[5]
@@ -2566,6 +2555,7 @@ set_disable_timing cby_2__2_/chany_top_out[1]
set_disable_timing cby_2__2_/chany_bottom_out[2]
set_disable_timing cby_2__2_/chany_top_out[2]
set_disable_timing cby_2__2_/chany_bottom_out[3]
+set_disable_timing cby_2__2_/chany_top_out[3]
set_disable_timing cby_2__2_/chany_bottom_out[4]
set_disable_timing cby_2__2_/chany_top_out[4]
set_disable_timing cby_2__2_/chany_bottom_out[5]
@@ -2605,6 +2595,7 @@ set_disable_timing cby_2__3_/chany_top_in[0]
set_disable_timing cby_2__3_/chany_bottom_in[1]
set_disable_timing cby_2__3_/chany_top_in[1]
set_disable_timing cby_2__3_/chany_bottom_in[2]
+set_disable_timing cby_2__3_/chany_top_in[2]
set_disable_timing cby_2__3_/chany_bottom_in[3]
set_disable_timing cby_2__3_/chany_top_in[3]
set_disable_timing cby_2__3_/chany_bottom_in[4]
@@ -2624,6 +2615,7 @@ set_disable_timing cby_2__3_/chany_top_out[0]
set_disable_timing cby_2__3_/chany_bottom_out[1]
set_disable_timing cby_2__3_/chany_top_out[1]
set_disable_timing cby_2__3_/chany_bottom_out[2]
+set_disable_timing cby_2__3_/chany_top_out[2]
set_disable_timing cby_2__3_/chany_bottom_out[3]
set_disable_timing cby_2__3_/chany_top_out[3]
set_disable_timing cby_2__3_/chany_bottom_out[4]
@@ -2663,6 +2655,7 @@ set_disable_timing cby_2__3_/mux_right_ipin_0/in[2]
set_disable_timing cby_2__4_/chany_bottom_in[0]
set_disable_timing cby_2__4_/chany_top_in[0]
set_disable_timing cby_2__4_/chany_bottom_in[1]
+set_disable_timing cby_2__4_/chany_top_in[1]
set_disable_timing cby_2__4_/chany_bottom_in[2]
set_disable_timing cby_2__4_/chany_top_in[2]
set_disable_timing cby_2__4_/chany_bottom_in[3]
@@ -2682,6 +2675,7 @@ set_disable_timing cby_2__4_/chany_top_in[9]
set_disable_timing cby_2__4_/chany_bottom_out[0]
set_disable_timing cby_2__4_/chany_top_out[0]
set_disable_timing cby_2__4_/chany_bottom_out[1]
+set_disable_timing cby_2__4_/chany_top_out[1]
set_disable_timing cby_2__4_/chany_bottom_out[2]
set_disable_timing cby_2__4_/chany_top_out[2]
set_disable_timing cby_2__4_/chany_bottom_out[3]
@@ -2782,7 +2776,6 @@ set_disable_timing cby_3__1_/mux_right_ipin_0/in[2]
##################################################
# Disable timing for Connection block cby_1__1_
##################################################
-set_disable_timing cby_3__2_/chany_bottom_in[0]
set_disable_timing cby_3__2_/chany_top_in[0]
set_disable_timing cby_3__2_/chany_bottom_in[1]
set_disable_timing cby_3__2_/chany_top_in[1]
@@ -2802,7 +2795,6 @@ set_disable_timing cby_3__2_/chany_bottom_in[8]
set_disable_timing cby_3__2_/chany_top_in[8]
set_disable_timing cby_3__2_/chany_bottom_in[9]
set_disable_timing cby_3__2_/chany_top_in[9]
-set_disable_timing cby_3__2_/chany_bottom_out[0]
set_disable_timing cby_3__2_/chany_top_out[0]
set_disable_timing cby_3__2_/chany_bottom_out[1]
set_disable_timing cby_3__2_/chany_top_out[1]
@@ -2846,7 +2838,6 @@ set_disable_timing cby_3__2_/mux_right_ipin_0/in[2]
##################################################
set_disable_timing cby_3__3_/chany_bottom_in[0]
set_disable_timing cby_3__3_/chany_top_in[0]
-set_disable_timing cby_3__3_/chany_bottom_in[1]
set_disable_timing cby_3__3_/chany_top_in[1]
set_disable_timing cby_3__3_/chany_bottom_in[2]
set_disable_timing cby_3__3_/chany_top_in[2]
@@ -2866,7 +2857,6 @@ set_disable_timing cby_3__3_/chany_bottom_in[9]
set_disable_timing cby_3__3_/chany_top_in[9]
set_disable_timing cby_3__3_/chany_bottom_out[0]
set_disable_timing cby_3__3_/chany_top_out[0]
-set_disable_timing cby_3__3_/chany_bottom_out[1]
set_disable_timing cby_3__3_/chany_top_out[1]
set_disable_timing cby_3__3_/chany_bottom_out[2]
set_disable_timing cby_3__3_/chany_top_out[2]
@@ -2885,13 +2875,11 @@ set_disable_timing cby_3__3_/chany_top_out[8]
set_disable_timing cby_3__3_/chany_bottom_out[9]
set_disable_timing cby_3__3_/chany_top_out[9]
set_disable_timing cby_3__3_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0]
-set_disable_timing cby_3__3_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0]
set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0]
set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0]
set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0]
set_disable_timing cby_3__3_/mux_left_ipin_0/in[1]
set_disable_timing cby_3__3_/mux_left_ipin_0/in[0]
-set_disable_timing cby_3__3_/mux_left_ipin_1/in[1]
set_disable_timing cby_3__3_/mux_left_ipin_1/in[0]
set_disable_timing cby_3__3_/mux_right_ipin_0/in[1]
set_disable_timing cby_3__3_/mux_right_ipin_0/in[0]
@@ -2910,7 +2898,6 @@ set_disable_timing cby_3__4_/chany_bottom_in[0]
set_disable_timing cby_3__4_/chany_top_in[0]
set_disable_timing cby_3__4_/chany_bottom_in[1]
set_disable_timing cby_3__4_/chany_top_in[1]
-set_disable_timing cby_3__4_/chany_bottom_in[2]
set_disable_timing cby_3__4_/chany_top_in[2]
set_disable_timing cby_3__4_/chany_bottom_in[3]
set_disable_timing cby_3__4_/chany_top_in[3]
@@ -2930,7 +2917,6 @@ set_disable_timing cby_3__4_/chany_bottom_out[0]
set_disable_timing cby_3__4_/chany_top_out[0]
set_disable_timing cby_3__4_/chany_bottom_out[1]
set_disable_timing cby_3__4_/chany_top_out[1]
-set_disable_timing cby_3__4_/chany_bottom_out[2]
set_disable_timing cby_3__4_/chany_top_out[2]
set_disable_timing cby_3__4_/chany_bottom_out[3]
set_disable_timing cby_3__4_/chany_top_out[3]
@@ -2974,7 +2960,6 @@ set_disable_timing cby_4__1_/chany_bottom_in[1]
set_disable_timing cby_4__1_/chany_top_in[1]
set_disable_timing cby_4__1_/chany_bottom_in[2]
set_disable_timing cby_4__1_/chany_top_in[2]
-set_disable_timing cby_4__1_/chany_bottom_in[3]
set_disable_timing cby_4__1_/chany_top_in[3]
set_disable_timing cby_4__1_/chany_bottom_in[4]
set_disable_timing cby_4__1_/chany_top_in[4]
@@ -2994,7 +2979,6 @@ set_disable_timing cby_4__1_/chany_bottom_out[1]
set_disable_timing cby_4__1_/chany_top_out[1]
set_disable_timing cby_4__1_/chany_bottom_out[2]
set_disable_timing cby_4__1_/chany_top_out[2]
-set_disable_timing cby_4__1_/chany_bottom_out[3]
set_disable_timing cby_4__1_/chany_top_out[3]
set_disable_timing cby_4__1_/chany_bottom_out[4]
set_disable_timing cby_4__1_/chany_top_out[4]
@@ -3081,7 +3065,6 @@ set_disable_timing cby_4__2_/chany_top_in[7]
set_disable_timing cby_4__2_/chany_bottom_in[8]
set_disable_timing cby_4__2_/chany_top_in[8]
set_disable_timing cby_4__2_/chany_bottom_in[9]
-set_disable_timing cby_4__2_/chany_top_in[9]
set_disable_timing cby_4__2_/chany_bottom_out[0]
set_disable_timing cby_4__2_/chany_top_out[0]
set_disable_timing cby_4__2_/chany_bottom_out[1]
@@ -3101,7 +3084,6 @@ set_disable_timing cby_4__2_/chany_top_out[7]
set_disable_timing cby_4__2_/chany_bottom_out[8]
set_disable_timing cby_4__2_/chany_top_out[8]
set_disable_timing cby_4__2_/chany_bottom_out[9]
-set_disable_timing cby_4__2_/chany_top_out[9]
set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0]
@@ -3171,9 +3153,7 @@ set_disable_timing cby_4__3_/chany_top_in[5]
set_disable_timing cby_4__3_/chany_bottom_in[6]
set_disable_timing cby_4__3_/chany_top_in[6]
set_disable_timing cby_4__3_/chany_bottom_in[7]
-set_disable_timing cby_4__3_/chany_top_in[7]
set_disable_timing cby_4__3_/chany_bottom_in[8]
-set_disable_timing cby_4__3_/chany_top_in[8]
set_disable_timing cby_4__3_/chany_bottom_in[9]
set_disable_timing cby_4__3_/chany_top_in[9]
set_disable_timing cby_4__3_/chany_bottom_out[0]
@@ -3191,9 +3171,7 @@ set_disable_timing cby_4__3_/chany_top_out[5]
set_disable_timing cby_4__3_/chany_bottom_out[6]
set_disable_timing cby_4__3_/chany_top_out[6]
set_disable_timing cby_4__3_/chany_bottom_out[7]
-set_disable_timing cby_4__3_/chany_top_out[7]
set_disable_timing cby_4__3_/chany_bottom_out[8]
-set_disable_timing cby_4__3_/chany_top_out[8]
set_disable_timing cby_4__3_/chany_bottom_out[9]
set_disable_timing cby_4__3_/chany_top_out[9]
set_disable_timing cby_4__3_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0]
@@ -3263,7 +3241,6 @@ set_disable_timing cby_4__4_/chany_top_in[4]
set_disable_timing cby_4__4_/chany_bottom_in[5]
set_disable_timing cby_4__4_/chany_top_in[5]
set_disable_timing cby_4__4_/chany_bottom_in[6]
-set_disable_timing cby_4__4_/chany_top_in[6]
set_disable_timing cby_4__4_/chany_bottom_in[7]
set_disable_timing cby_4__4_/chany_top_in[7]
set_disable_timing cby_4__4_/chany_bottom_in[8]
@@ -3283,7 +3260,6 @@ set_disable_timing cby_4__4_/chany_top_out[4]
set_disable_timing cby_4__4_/chany_bottom_out[5]
set_disable_timing cby_4__4_/chany_top_out[5]
set_disable_timing cby_4__4_/chany_bottom_out[6]
-set_disable_timing cby_4__4_/chany_top_out[6]
set_disable_timing cby_4__4_/chany_bottom_out[7]
set_disable_timing cby_4__4_/chany_top_out[7]
set_disable_timing cby_4__4_/chany_bottom_out[8]
@@ -3441,6 +3417,7 @@ set_disable_timing sb_0__0_/mux_top_track_16/in[1]
##################################################
# Disable timing for Switch block sb_0__1_
##################################################
+set_disable_timing sb_0__1_/chany_top_out[0]
set_disable_timing sb_0__1_/chany_top_in[0]
set_disable_timing sb_0__1_/chany_top_out[1]
set_disable_timing sb_0__1_/chany_top_in[1]
@@ -3463,6 +3440,7 @@ set_disable_timing sb_0__1_/chany_top_in[9]
set_disable_timing sb_0__1_/chanx_right_out[0]
set_disable_timing sb_0__1_/chanx_right_in[0]
set_disable_timing sb_0__1_/chanx_right_out[1]
+set_disable_timing sb_0__1_/chanx_right_in[1]
set_disable_timing sb_0__1_/chanx_right_out[2]
set_disable_timing sb_0__1_/chanx_right_in[2]
set_disable_timing sb_0__1_/chanx_right_out[3]
@@ -3557,6 +3535,7 @@ set_disable_timing sb_0__1_/mux_bottom_track_1/in[2]
set_disable_timing sb_0__1_/mux_right_track_6/in[1]
set_disable_timing sb_0__1_/mux_top_track_16/in[3]
set_disable_timing sb_0__1_/mux_bottom_track_9/in[2]
+set_disable_timing sb_0__1_/mux_top_track_0/in[3]
set_disable_timing sb_0__1_/mux_bottom_track_1/in[3]
set_disable_timing sb_0__1_/mux_top_track_8/in[3]
set_disable_timing sb_0__1_/mux_bottom_track_17/in[2]
@@ -3596,6 +3575,7 @@ set_disable_timing sb_0__1_/mux_right_track_12/in[2]
##################################################
set_disable_timing sb_0__2_/chany_top_out[0]
set_disable_timing sb_0__2_/chany_top_in[0]
+set_disable_timing sb_0__2_/chany_top_out[1]
set_disable_timing sb_0__2_/chany_top_in[1]
set_disable_timing sb_0__2_/chany_top_out[2]
set_disable_timing sb_0__2_/chany_top_in[2]
@@ -3618,7 +3598,6 @@ set_disable_timing sb_0__2_/chanx_right_in[0]
set_disable_timing sb_0__2_/chanx_right_out[1]
set_disable_timing sb_0__2_/chanx_right_in[1]
set_disable_timing sb_0__2_/chanx_right_out[2]
-set_disable_timing sb_0__2_/chanx_right_in[2]
set_disable_timing sb_0__2_/chanx_right_out[3]
set_disable_timing sb_0__2_/chanx_right_in[3]
set_disable_timing sb_0__2_/chanx_right_out[4]
@@ -3628,11 +3607,11 @@ set_disable_timing sb_0__2_/chanx_right_in[5]
set_disable_timing sb_0__2_/chanx_right_out[6]
set_disable_timing sb_0__2_/chanx_right_in[6]
set_disable_timing sb_0__2_/chanx_right_out[7]
-set_disable_timing sb_0__2_/chanx_right_in[7]
set_disable_timing sb_0__2_/chanx_right_out[8]
set_disable_timing sb_0__2_/chanx_right_in[8]
set_disable_timing sb_0__2_/chanx_right_out[9]
set_disable_timing sb_0__2_/chanx_right_in[9]
+set_disable_timing sb_0__2_/chany_bottom_in[0]
set_disable_timing sb_0__2_/chany_bottom_out[0]
set_disable_timing sb_0__2_/chany_bottom_in[1]
set_disable_timing sb_0__2_/chany_bottom_out[1]
@@ -3752,6 +3731,7 @@ set_disable_timing sb_0__3_/chany_top_out[0]
set_disable_timing sb_0__3_/chany_top_in[0]
set_disable_timing sb_0__3_/chany_top_out[1]
set_disable_timing sb_0__3_/chany_top_in[1]
+set_disable_timing sb_0__3_/chany_top_out[2]
set_disable_timing sb_0__3_/chany_top_in[2]
set_disable_timing sb_0__3_/chany_top_out[3]
set_disable_timing sb_0__3_/chany_top_in[3]
@@ -3789,6 +3769,7 @@ set_disable_timing sb_0__3_/chanx_right_out[9]
set_disable_timing sb_0__3_/chanx_right_in[9]
set_disable_timing sb_0__3_/chany_bottom_in[0]
set_disable_timing sb_0__3_/chany_bottom_out[0]
+set_disable_timing sb_0__3_/chany_bottom_in[1]
set_disable_timing sb_0__3_/chany_bottom_out[1]
set_disable_timing sb_0__3_/chany_bottom_in[2]
set_disable_timing sb_0__3_/chany_bottom_out[2]
@@ -3913,16 +3894,20 @@ set_disable_timing sb_0__4_/chanx_right_in[3]
set_disable_timing sb_0__4_/chanx_right_out[4]
set_disable_timing sb_0__4_/chanx_right_in[4]
set_disable_timing sb_0__4_/chanx_right_out[5]
+set_disable_timing sb_0__4_/chanx_right_in[5]
+set_disable_timing sb_0__4_/chanx_right_out[6]
set_disable_timing sb_0__4_/chanx_right_in[6]
set_disable_timing sb_0__4_/chanx_right_out[7]
set_disable_timing sb_0__4_/chanx_right_in[7]
set_disable_timing sb_0__4_/chanx_right_out[8]
set_disable_timing sb_0__4_/chanx_right_in[8]
set_disable_timing sb_0__4_/chanx_right_out[9]
+set_disable_timing sb_0__4_/chanx_right_in[9]
set_disable_timing sb_0__4_/chany_bottom_in[0]
set_disable_timing sb_0__4_/chany_bottom_out[0]
set_disable_timing sb_0__4_/chany_bottom_in[1]
set_disable_timing sb_0__4_/chany_bottom_out[1]
+set_disable_timing sb_0__4_/chany_bottom_in[2]
set_disable_timing sb_0__4_/chany_bottom_out[2]
set_disable_timing sb_0__4_/chany_bottom_in[3]
set_disable_timing sb_0__4_/chany_bottom_out[3]
@@ -3985,6 +3970,7 @@ set_disable_timing sb_0__4_/mux_bottom_track_3/in[0]
set_disable_timing sb_0__4_/mux_bottom_track_1/in[0]
set_disable_timing sb_0__4_/mux_right_track_16/in[1]
set_disable_timing sb_0__4_/mux_right_track_14/in[1]
+set_disable_timing sb_0__4_/mux_right_track_12/in[1]
set_disable_timing sb_0__4_/mux_right_track_10/in[1]
set_disable_timing sb_0__4_/mux_right_track_8/in[1]
set_disable_timing sb_0__4_/mux_right_track_6/in[1]
@@ -4168,12 +4154,12 @@ set_disable_timing sb_1__1_/chany_top_in[8]
set_disable_timing sb_1__1_/chany_top_out[9]
set_disable_timing sb_1__1_/chany_top_in[9]
set_disable_timing sb_1__1_/chanx_right_out[0]
+set_disable_timing sb_1__1_/chanx_right_in[0]
set_disable_timing sb_1__1_/chanx_right_out[1]
set_disable_timing sb_1__1_/chanx_right_in[1]
set_disable_timing sb_1__1_/chanx_right_out[2]
set_disable_timing sb_1__1_/chanx_right_in[2]
set_disable_timing sb_1__1_/chanx_right_out[3]
-set_disable_timing sb_1__1_/chanx_right_in[3]
set_disable_timing sb_1__1_/chanx_right_out[4]
set_disable_timing sb_1__1_/chanx_right_in[4]
set_disable_timing sb_1__1_/chanx_right_out[5]
@@ -4209,6 +4195,7 @@ set_disable_timing sb_1__1_/chany_bottom_out[9]
set_disable_timing sb_1__1_/chanx_left_in[0]
set_disable_timing sb_1__1_/chanx_left_out[0]
set_disable_timing sb_1__1_/chanx_left_in[1]
+set_disable_timing sb_1__1_/chanx_left_out[1]
set_disable_timing sb_1__1_/chanx_left_in[2]
set_disable_timing sb_1__1_/chanx_left_out[2]
set_disable_timing sb_1__1_/chanx_left_in[3]
@@ -4352,7 +4339,6 @@ set_disable_timing sb_1__1_/mux_bottom_track_9/in[9]
##################################################
# Disable timing for Switch block sb_1__1_
##################################################
-set_disable_timing sb_1__2_/chany_top_out[0]
set_disable_timing sb_1__2_/chany_top_in[0]
set_disable_timing sb_1__2_/chany_top_out[1]
set_disable_timing sb_1__2_/chany_top_in[1]
@@ -4375,7 +4361,6 @@ set_disable_timing sb_1__2_/chany_top_in[9]
set_disable_timing sb_1__2_/chanx_right_out[0]
set_disable_timing sb_1__2_/chanx_right_in[0]
set_disable_timing sb_1__2_/chanx_right_out[1]
-set_disable_timing sb_1__2_/chanx_right_in[1]
set_disable_timing sb_1__2_/chanx_right_out[2]
set_disable_timing sb_1__2_/chanx_right_in[2]
set_disable_timing sb_1__2_/chanx_right_out[3]
@@ -4385,7 +4370,6 @@ set_disable_timing sb_1__2_/chanx_right_in[4]
set_disable_timing sb_1__2_/chanx_right_out[5]
set_disable_timing sb_1__2_/chanx_right_in[5]
set_disable_timing sb_1__2_/chanx_right_out[6]
-set_disable_timing sb_1__2_/chanx_right_in[6]
set_disable_timing sb_1__2_/chanx_right_out[7]
set_disable_timing sb_1__2_/chanx_right_in[7]
set_disable_timing sb_1__2_/chanx_right_out[8]
@@ -4417,7 +4401,6 @@ set_disable_timing sb_1__2_/chanx_left_out[0]
set_disable_timing sb_1__2_/chanx_left_in[1]
set_disable_timing sb_1__2_/chanx_left_out[1]
set_disable_timing sb_1__2_/chanx_left_in[2]
-set_disable_timing sb_1__2_/chanx_left_out[2]
set_disable_timing sb_1__2_/chanx_left_in[3]
set_disable_timing sb_1__2_/chanx_left_out[3]
set_disable_timing sb_1__2_/chanx_left_in[4]
@@ -4427,7 +4410,6 @@ set_disable_timing sb_1__2_/chanx_left_out[5]
set_disable_timing sb_1__2_/chanx_left_in[6]
set_disable_timing sb_1__2_/chanx_left_out[6]
set_disable_timing sb_1__2_/chanx_left_in[7]
-set_disable_timing sb_1__2_/chanx_left_out[7]
set_disable_timing sb_1__2_/chanx_left_in[8]
set_disable_timing sb_1__2_/chanx_left_out[8]
set_disable_timing sb_1__2_/chanx_left_in[9]
@@ -4478,7 +4460,6 @@ set_disable_timing sb_1__2_/mux_left_track_9/in[2]
set_disable_timing sb_1__2_/mux_top_track_16/in[0]
set_disable_timing sb_1__2_/mux_bottom_track_9/in[2]
set_disable_timing sb_1__2_/mux_left_track_1/in[4]
-set_disable_timing sb_1__2_/mux_top_track_0/in[1]
set_disable_timing sb_1__2_/mux_bottom_track_1/in[3]
set_disable_timing sb_1__2_/mux_left_track_9/in[3]
set_disable_timing sb_1__2_/mux_top_track_8/in[1]
@@ -4561,7 +4542,6 @@ set_disable_timing sb_1__2_/mux_bottom_track_9/in[9]
##################################################
set_disable_timing sb_1__3_/chany_top_out[0]
set_disable_timing sb_1__3_/chany_top_in[0]
-set_disable_timing sb_1__3_/chany_top_out[1]
set_disable_timing sb_1__3_/chany_top_in[1]
set_disable_timing sb_1__3_/chany_top_out[2]
set_disable_timing sb_1__3_/chany_top_in[2]
@@ -4594,12 +4574,10 @@ set_disable_timing sb_1__3_/chanx_right_in[5]
set_disable_timing sb_1__3_/chanx_right_out[6]
set_disable_timing sb_1__3_/chanx_right_in[6]
set_disable_timing sb_1__3_/chanx_right_out[7]
-set_disable_timing sb_1__3_/chanx_right_in[7]
set_disable_timing sb_1__3_/chanx_right_out[8]
set_disable_timing sb_1__3_/chanx_right_in[8]
set_disable_timing sb_1__3_/chanx_right_out[9]
set_disable_timing sb_1__3_/chanx_right_in[9]
-set_disable_timing sb_1__3_/chany_bottom_in[0]
set_disable_timing sb_1__3_/chany_bottom_out[0]
set_disable_timing sb_1__3_/chany_bottom_in[1]
set_disable_timing sb_1__3_/chany_bottom_out[1]
@@ -4766,7 +4744,6 @@ set_disable_timing sb_1__3_/mux_bottom_track_9/in[9]
##################################################
# Disable timing for Switch block sb_1__4_
##################################################
-set_disable_timing sb_1__4_/chanx_right_out[0]
set_disable_timing sb_1__4_/chanx_right_in[0]
set_disable_timing sb_1__4_/chanx_right_out[1]
set_disable_timing sb_1__4_/chanx_right_in[1]
@@ -4775,17 +4752,19 @@ set_disable_timing sb_1__4_/chanx_right_in[2]
set_disable_timing sb_1__4_/chanx_right_out[3]
set_disable_timing sb_1__4_/chanx_right_in[3]
set_disable_timing sb_1__4_/chanx_right_out[4]
+set_disable_timing sb_1__4_/chanx_right_in[4]
set_disable_timing sb_1__4_/chanx_right_out[5]
set_disable_timing sb_1__4_/chanx_right_in[5]
set_disable_timing sb_1__4_/chanx_right_out[6]
set_disable_timing sb_1__4_/chanx_right_in[6]
+set_disable_timing sb_1__4_/chanx_right_out[7]
set_disable_timing sb_1__4_/chanx_right_in[7]
set_disable_timing sb_1__4_/chanx_right_out[8]
+set_disable_timing sb_1__4_/chanx_right_in[8]
set_disable_timing sb_1__4_/chanx_right_out[9]
set_disable_timing sb_1__4_/chanx_right_in[9]
set_disable_timing sb_1__4_/chany_bottom_in[0]
set_disable_timing sb_1__4_/chany_bottom_out[0]
-set_disable_timing sb_1__4_/chany_bottom_in[1]
set_disable_timing sb_1__4_/chany_bottom_out[1]
set_disable_timing sb_1__4_/chany_bottom_in[2]
set_disable_timing sb_1__4_/chany_bottom_out[2]
@@ -4814,16 +4793,21 @@ set_disable_timing sb_1__4_/chanx_left_out[3]
set_disable_timing sb_1__4_/chanx_left_in[4]
set_disable_timing sb_1__4_/chanx_left_out[4]
set_disable_timing sb_1__4_/chanx_left_in[5]
+set_disable_timing sb_1__4_/chanx_left_out[5]
+set_disable_timing sb_1__4_/chanx_left_in[6]
set_disable_timing sb_1__4_/chanx_left_out[6]
set_disable_timing sb_1__4_/chanx_left_in[7]
set_disable_timing sb_1__4_/chanx_left_out[7]
set_disable_timing sb_1__4_/chanx_left_in[8]
set_disable_timing sb_1__4_/chanx_left_out[8]
set_disable_timing sb_1__4_/chanx_left_in[9]
+set_disable_timing sb_1__4_/chanx_left_out[9]
set_disable_timing sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0]
+set_disable_timing sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0]
+set_disable_timing sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_1__4_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__4_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
@@ -4877,7 +4861,6 @@ set_disable_timing sb_1__4_/mux_left_track_1/in[2]
set_disable_timing sb_1__4_/mux_bottom_track_13/in[1]
set_disable_timing sb_1__4_/mux_right_track_8/in[3]
set_disable_timing sb_1__4_/mux_left_track_9/in[2]
-set_disable_timing sb_1__4_/mux_right_track_0/in[3]
set_disable_timing sb_1__4_/mux_left_track_17/in[2]
set_disable_timing sb_1__4_/mux_right_track_16/in[3]
set_disable_timing sb_1__4_/mux_left_track_1/in[3]
@@ -5075,6 +5058,7 @@ set_disable_timing sb_2__1_/chany_top_in[1]
set_disable_timing sb_2__1_/chany_top_out[2]
set_disable_timing sb_2__1_/chany_top_in[2]
set_disable_timing sb_2__1_/chany_top_out[3]
+set_disable_timing sb_2__1_/chany_top_in[3]
set_disable_timing sb_2__1_/chany_top_out[4]
set_disable_timing sb_2__1_/chany_top_in[4]
set_disable_timing sb_2__1_/chany_top_out[5]
@@ -5092,7 +5076,6 @@ set_disable_timing sb_2__1_/chanx_right_in[0]
set_disable_timing sb_2__1_/chanx_right_out[1]
set_disable_timing sb_2__1_/chanx_right_in[1]
set_disable_timing sb_2__1_/chanx_right_out[2]
-set_disable_timing sb_2__1_/chanx_right_in[2]
set_disable_timing sb_2__1_/chanx_right_out[3]
set_disable_timing sb_2__1_/chanx_right_in[3]
set_disable_timing sb_2__1_/chanx_right_out[4]
@@ -5128,12 +5111,12 @@ set_disable_timing sb_2__1_/chany_bottom_out[8]
set_disable_timing sb_2__1_/chany_bottom_in[9]
set_disable_timing sb_2__1_/chany_bottom_out[9]
set_disable_timing sb_2__1_/chanx_left_in[0]
+set_disable_timing sb_2__1_/chanx_left_out[0]
set_disable_timing sb_2__1_/chanx_left_in[1]
set_disable_timing sb_2__1_/chanx_left_out[1]
set_disable_timing sb_2__1_/chanx_left_in[2]
set_disable_timing sb_2__1_/chanx_left_out[2]
set_disable_timing sb_2__1_/chanx_left_in[3]
-set_disable_timing sb_2__1_/chanx_left_out[3]
set_disable_timing sb_2__1_/chanx_left_in[4]
set_disable_timing sb_2__1_/chanx_left_out[4]
set_disable_timing sb_2__1_/chanx_left_in[5]
@@ -5172,6 +5155,7 @@ set_disable_timing sb_2__1_/mux_right_track_0/in[0]
set_disable_timing sb_2__1_/mux_bottom_track_17/in[0]
set_disable_timing sb_2__1_/mux_left_track_9/in[0]
set_disable_timing sb_2__1_/mux_right_track_8/in[1]
+set_disable_timing sb_2__1_/mux_left_track_1/in[1]
set_disable_timing sb_2__1_/mux_right_track_8/in[2]
set_disable_timing sb_2__1_/mux_bottom_track_1/in[1]
set_disable_timing sb_2__1_/mux_left_track_1/in[2]
@@ -5277,6 +5261,7 @@ set_disable_timing sb_2__2_/chany_top_in[0]
set_disable_timing sb_2__2_/chany_top_out[1]
set_disable_timing sb_2__2_/chany_top_in[1]
set_disable_timing sb_2__2_/chany_top_out[2]
+set_disable_timing sb_2__2_/chany_top_in[2]
set_disable_timing sb_2__2_/chany_top_out[3]
set_disable_timing sb_2__2_/chany_top_in[3]
set_disable_timing sb_2__2_/chany_top_out[4]
@@ -5292,7 +5277,6 @@ set_disable_timing sb_2__2_/chany_top_in[8]
set_disable_timing sb_2__2_/chany_top_out[9]
set_disable_timing sb_2__2_/chany_top_in[9]
set_disable_timing sb_2__2_/chanx_right_out[0]
-set_disable_timing sb_2__2_/chanx_right_in[0]
set_disable_timing sb_2__2_/chanx_right_out[1]
set_disable_timing sb_2__2_/chanx_right_in[1]
set_disable_timing sb_2__2_/chanx_right_out[2]
@@ -5302,7 +5286,6 @@ set_disable_timing sb_2__2_/chanx_right_in[3]
set_disable_timing sb_2__2_/chanx_right_out[4]
set_disable_timing sb_2__2_/chanx_right_in[4]
set_disable_timing sb_2__2_/chanx_right_out[5]
-set_disable_timing sb_2__2_/chanx_right_in[5]
set_disable_timing sb_2__2_/chanx_right_out[6]
set_disable_timing sb_2__2_/chanx_right_in[6]
set_disable_timing sb_2__2_/chanx_right_out[7]
@@ -5318,6 +5301,7 @@ set_disable_timing sb_2__2_/chany_bottom_out[1]
set_disable_timing sb_2__2_/chany_bottom_in[2]
set_disable_timing sb_2__2_/chany_bottom_out[2]
set_disable_timing sb_2__2_/chany_bottom_in[3]
+set_disable_timing sb_2__2_/chany_bottom_out[3]
set_disable_timing sb_2__2_/chany_bottom_in[4]
set_disable_timing sb_2__2_/chany_bottom_out[4]
set_disable_timing sb_2__2_/chany_bottom_in[5]
@@ -5333,7 +5317,6 @@ set_disable_timing sb_2__2_/chany_bottom_out[9]
set_disable_timing sb_2__2_/chanx_left_in[0]
set_disable_timing sb_2__2_/chanx_left_out[0]
set_disable_timing sb_2__2_/chanx_left_in[1]
-set_disable_timing sb_2__2_/chanx_left_out[1]
set_disable_timing sb_2__2_/chanx_left_in[2]
set_disable_timing sb_2__2_/chanx_left_out[2]
set_disable_timing sb_2__2_/chanx_left_in[3]
@@ -5343,7 +5326,6 @@ set_disable_timing sb_2__2_/chanx_left_out[4]
set_disable_timing sb_2__2_/chanx_left_in[5]
set_disable_timing sb_2__2_/chanx_left_out[5]
set_disable_timing sb_2__2_/chanx_left_in[6]
-set_disable_timing sb_2__2_/chanx_left_out[6]
set_disable_timing sb_2__2_/chanx_left_in[7]
set_disable_timing sb_2__2_/chanx_left_out[7]
set_disable_timing sb_2__2_/chanx_left_in[8]
@@ -5480,6 +5462,7 @@ set_disable_timing sb_2__2_/mux_bottom_track_9/in[9]
set_disable_timing sb_2__3_/chany_top_out[0]
set_disable_timing sb_2__3_/chany_top_in[0]
set_disable_timing sb_2__3_/chany_top_out[1]
+set_disable_timing sb_2__3_/chany_top_in[1]
set_disable_timing sb_2__3_/chany_top_out[2]
set_disable_timing sb_2__3_/chany_top_in[2]
set_disable_timing sb_2__3_/chany_top_out[3]
@@ -5509,7 +5492,6 @@ set_disable_timing sb_2__3_/chanx_right_in[4]
set_disable_timing sb_2__3_/chanx_right_out[5]
set_disable_timing sb_2__3_/chanx_right_in[5]
set_disable_timing sb_2__3_/chanx_right_out[6]
-set_disable_timing sb_2__3_/chanx_right_in[6]
set_disable_timing sb_2__3_/chanx_right_out[7]
set_disable_timing sb_2__3_/chanx_right_in[7]
set_disable_timing sb_2__3_/chanx_right_out[8]
@@ -5521,6 +5503,7 @@ set_disable_timing sb_2__3_/chany_bottom_out[0]
set_disable_timing sb_2__3_/chany_bottom_in[1]
set_disable_timing sb_2__3_/chany_bottom_out[1]
set_disable_timing sb_2__3_/chany_bottom_in[2]
+set_disable_timing sb_2__3_/chany_bottom_out[2]
set_disable_timing sb_2__3_/chany_bottom_in[3]
set_disable_timing sb_2__3_/chany_bottom_out[3]
set_disable_timing sb_2__3_/chany_bottom_in[4]
@@ -5550,11 +5533,11 @@ set_disable_timing sb_2__3_/chanx_left_out[5]
set_disable_timing sb_2__3_/chanx_left_in[6]
set_disable_timing sb_2__3_/chanx_left_out[6]
set_disable_timing sb_2__3_/chanx_left_in[7]
-set_disable_timing sb_2__3_/chanx_left_out[7]
set_disable_timing sb_2__3_/chanx_left_in[8]
set_disable_timing sb_2__3_/chanx_left_out[8]
set_disable_timing sb_2__3_/chanx_left_in[9]
set_disable_timing sb_2__3_/chanx_left_out[9]
+set_disable_timing sb_2__3_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0]
set_disable_timing sb_2__3_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0]
set_disable_timing sb_2__3_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0]
set_disable_timing sb_2__3_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
@@ -5683,7 +5666,6 @@ set_disable_timing sb_2__3_/mux_bottom_track_9/in[9]
##################################################
set_disable_timing sb_2__4_/chanx_right_out[0]
set_disable_timing sb_2__4_/chanx_right_in[0]
-set_disable_timing sb_2__4_/chanx_right_out[1]
set_disable_timing sb_2__4_/chanx_right_in[1]
set_disable_timing sb_2__4_/chanx_right_out[2]
set_disable_timing sb_2__4_/chanx_right_in[2]
@@ -5704,6 +5686,7 @@ set_disable_timing sb_2__4_/chanx_right_in[9]
set_disable_timing sb_2__4_/chany_bottom_in[0]
set_disable_timing sb_2__4_/chany_bottom_out[0]
set_disable_timing sb_2__4_/chany_bottom_in[1]
+set_disable_timing sb_2__4_/chany_bottom_out[1]
set_disable_timing sb_2__4_/chany_bottom_in[2]
set_disable_timing sb_2__4_/chany_bottom_out[2]
set_disable_timing sb_2__4_/chany_bottom_in[3]
@@ -5720,7 +5703,6 @@ set_disable_timing sb_2__4_/chany_bottom_in[8]
set_disable_timing sb_2__4_/chany_bottom_out[8]
set_disable_timing sb_2__4_/chany_bottom_in[9]
set_disable_timing sb_2__4_/chany_bottom_out[9]
-set_disable_timing sb_2__4_/chanx_left_in[0]
set_disable_timing sb_2__4_/chanx_left_out[0]
set_disable_timing sb_2__4_/chanx_left_in[1]
set_disable_timing sb_2__4_/chanx_left_out[1]
@@ -5729,12 +5711,15 @@ set_disable_timing sb_2__4_/chanx_left_out[2]
set_disable_timing sb_2__4_/chanx_left_in[3]
set_disable_timing sb_2__4_/chanx_left_out[3]
set_disable_timing sb_2__4_/chanx_left_in[4]
+set_disable_timing sb_2__4_/chanx_left_out[4]
set_disable_timing sb_2__4_/chanx_left_in[5]
set_disable_timing sb_2__4_/chanx_left_out[5]
set_disable_timing sb_2__4_/chanx_left_in[6]
set_disable_timing sb_2__4_/chanx_left_out[6]
+set_disable_timing sb_2__4_/chanx_left_in[7]
set_disable_timing sb_2__4_/chanx_left_out[7]
set_disable_timing sb_2__4_/chanx_left_in[8]
+set_disable_timing sb_2__4_/chanx_left_out[8]
set_disable_timing sb_2__4_/chanx_left_in[9]
set_disable_timing sb_2__4_/chanx_left_out[9]
set_disable_timing sb_2__4_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
@@ -5747,10 +5732,13 @@ set_disable_timing sb_2__4_/right_top_grid_bottom_width_0_height_0_subtile_6__pi
set_disable_timing sb_2__4_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_2__4_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
set_disable_timing sb_2__4_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0]
+set_disable_timing sb_2__4_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0]
set_disable_timing sb_2__4_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_2__4_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_2__4_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_2__4_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0]
+set_disable_timing sb_2__4_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0]
+set_disable_timing sb_2__4_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_2__4_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_2__4_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_2__4_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
@@ -5764,10 +5752,13 @@ set_disable_timing sb_2__4_/mux_right_track_0/in[2]
set_disable_timing sb_2__4_/mux_right_track_8/in[2]
set_disable_timing sb_2__4_/mux_right_track_16/in[2]
set_disable_timing sb_2__4_/mux_bottom_track_1/in[0]
+set_disable_timing sb_2__4_/mux_bottom_track_3/in[0]
set_disable_timing sb_2__4_/mux_left_track_1/in[6]
set_disable_timing sb_2__4_/mux_left_track_9/in[6]
set_disable_timing sb_2__4_/mux_left_track_17/in[5]
set_disable_timing sb_2__4_/mux_left_track_1/in[7]
+set_disable_timing sb_2__4_/mux_left_track_9/in[7]
+set_disable_timing sb_2__4_/mux_left_track_17/in[6]
set_disable_timing sb_2__4_/mux_left_track_1/in[8]
set_disable_timing sb_2__4_/mux_left_track_9/in[8]
set_disable_timing sb_2__4_/mux_left_track_17/in[7]
@@ -5981,7 +5972,6 @@ set_disable_timing sb_3__0_/mux_top_track_16/in[1]
##################################################
# Disable timing for Switch block sb_1__1_
##################################################
-set_disable_timing sb_3__1_/chany_top_out[0]
set_disable_timing sb_3__1_/chany_top_in[0]
set_disable_timing sb_3__1_/chany_top_out[1]
set_disable_timing sb_3__1_/chany_top_in[1]
@@ -6004,7 +5994,6 @@ set_disable_timing sb_3__1_/chany_top_in[9]
set_disable_timing sb_3__1_/chanx_right_out[0]
set_disable_timing sb_3__1_/chanx_right_in[0]
set_disable_timing sb_3__1_/chanx_right_out[1]
-set_disable_timing sb_3__1_/chanx_right_in[1]
set_disable_timing sb_3__1_/chanx_right_out[2]
set_disable_timing sb_3__1_/chanx_right_in[2]
set_disable_timing sb_3__1_/chanx_right_out[3]
@@ -6046,7 +6035,6 @@ set_disable_timing sb_3__1_/chanx_left_out[0]
set_disable_timing sb_3__1_/chanx_left_in[1]
set_disable_timing sb_3__1_/chanx_left_out[1]
set_disable_timing sb_3__1_/chanx_left_in[2]
-set_disable_timing sb_3__1_/chanx_left_out[2]
set_disable_timing sb_3__1_/chanx_left_in[3]
set_disable_timing sb_3__1_/chanx_left_out[3]
set_disable_timing sb_3__1_/chanx_left_in[4]
@@ -6107,7 +6095,6 @@ set_disable_timing sb_3__1_/mux_left_track_9/in[2]
set_disable_timing sb_3__1_/mux_top_track_16/in[0]
set_disable_timing sb_3__1_/mux_bottom_track_9/in[2]
set_disable_timing sb_3__1_/mux_left_track_1/in[4]
-set_disable_timing sb_3__1_/mux_top_track_0/in[1]
set_disable_timing sb_3__1_/mux_bottom_track_1/in[3]
set_disable_timing sb_3__1_/mux_left_track_9/in[3]
set_disable_timing sb_3__1_/mux_top_track_8/in[1]
@@ -6190,7 +6177,6 @@ set_disable_timing sb_3__1_/mux_bottom_track_9/in[9]
##################################################
set_disable_timing sb_3__2_/chany_top_out[0]
set_disable_timing sb_3__2_/chany_top_in[0]
-set_disable_timing sb_3__2_/chany_top_out[1]
set_disable_timing sb_3__2_/chany_top_in[1]
set_disable_timing sb_3__2_/chany_top_out[2]
set_disable_timing sb_3__2_/chany_top_in[2]
@@ -6217,7 +6203,6 @@ set_disable_timing sb_3__2_/chanx_right_in[2]
set_disable_timing sb_3__2_/chanx_right_out[3]
set_disable_timing sb_3__2_/chanx_right_in[3]
set_disable_timing sb_3__2_/chanx_right_out[4]
-set_disable_timing sb_3__2_/chanx_right_in[4]
set_disable_timing sb_3__2_/chanx_right_out[5]
set_disable_timing sb_3__2_/chanx_right_in[5]
set_disable_timing sb_3__2_/chanx_right_out[6]
@@ -6228,7 +6213,6 @@ set_disable_timing sb_3__2_/chanx_right_out[8]
set_disable_timing sb_3__2_/chanx_right_in[8]
set_disable_timing sb_3__2_/chanx_right_out[9]
set_disable_timing sb_3__2_/chanx_right_in[9]
-set_disable_timing sb_3__2_/chany_bottom_in[0]
set_disable_timing sb_3__2_/chany_bottom_out[0]
set_disable_timing sb_3__2_/chany_bottom_in[1]
set_disable_timing sb_3__2_/chany_bottom_out[1]
@@ -6249,7 +6233,6 @@ set_disable_timing sb_3__2_/chany_bottom_out[8]
set_disable_timing sb_3__2_/chany_bottom_in[9]
set_disable_timing sb_3__2_/chany_bottom_out[9]
set_disable_timing sb_3__2_/chanx_left_in[0]
-set_disable_timing sb_3__2_/chanx_left_out[0]
set_disable_timing sb_3__2_/chanx_left_in[1]
set_disable_timing sb_3__2_/chanx_left_out[1]
set_disable_timing sb_3__2_/chanx_left_in[2]
@@ -6259,7 +6242,6 @@ set_disable_timing sb_3__2_/chanx_left_out[3]
set_disable_timing sb_3__2_/chanx_left_in[4]
set_disable_timing sb_3__2_/chanx_left_out[4]
set_disable_timing sb_3__2_/chanx_left_in[5]
-set_disable_timing sb_3__2_/chanx_left_out[5]
set_disable_timing sb_3__2_/chanx_left_in[6]
set_disable_timing sb_3__2_/chanx_left_out[6]
set_disable_timing sb_3__2_/chanx_left_in[7]
@@ -6324,7 +6306,6 @@ set_disable_timing sb_3__2_/mux_top_track_16/in[1]
set_disable_timing sb_3__2_/mux_bottom_track_9/in[3]
set_disable_timing sb_3__2_/mux_top_track_16/in[2]
set_disable_timing sb_3__2_/mux_bottom_track_9/in[4]
-set_disable_timing sb_3__2_/mux_left_track_1/in[5]
set_disable_timing sb_3__2_/mux_top_track_0/in[2]
set_disable_timing sb_3__2_/mux_bottom_track_1/in[4]
set_disable_timing sb_3__2_/mux_left_track_9/in[4]
@@ -6399,7 +6380,6 @@ set_disable_timing sb_3__3_/chany_top_out[0]
set_disable_timing sb_3__3_/chany_top_in[0]
set_disable_timing sb_3__3_/chany_top_out[1]
set_disable_timing sb_3__3_/chany_top_in[1]
-set_disable_timing sb_3__3_/chany_top_out[2]
set_disable_timing sb_3__3_/chany_top_in[2]
set_disable_timing sb_3__3_/chany_top_out[3]
set_disable_timing sb_3__3_/chany_top_in[3]
@@ -6426,7 +6406,6 @@ set_disable_timing sb_3__3_/chanx_right_in[3]
set_disable_timing sb_3__3_/chanx_right_out[4]
set_disable_timing sb_3__3_/chanx_right_in[4]
set_disable_timing sb_3__3_/chanx_right_out[5]
-set_disable_timing sb_3__3_/chanx_right_in[5]
set_disable_timing sb_3__3_/chanx_right_out[6]
set_disable_timing sb_3__3_/chanx_right_in[6]
set_disable_timing sb_3__3_/chanx_right_out[7]
@@ -6437,7 +6416,6 @@ set_disable_timing sb_3__3_/chanx_right_out[9]
set_disable_timing sb_3__3_/chanx_right_in[9]
set_disable_timing sb_3__3_/chany_bottom_in[0]
set_disable_timing sb_3__3_/chany_bottom_out[0]
-set_disable_timing sb_3__3_/chany_bottom_in[1]
set_disable_timing sb_3__3_/chany_bottom_out[1]
set_disable_timing sb_3__3_/chany_bottom_in[2]
set_disable_timing sb_3__3_/chany_bottom_out[2]
@@ -6468,7 +6446,6 @@ set_disable_timing sb_3__3_/chanx_left_out[4]
set_disable_timing sb_3__3_/chanx_left_in[5]
set_disable_timing sb_3__3_/chanx_left_out[5]
set_disable_timing sb_3__3_/chanx_left_in[6]
-set_disable_timing sb_3__3_/chanx_left_out[6]
set_disable_timing sb_3__3_/chanx_left_in[7]
set_disable_timing sb_3__3_/chanx_left_out[7]
set_disable_timing sb_3__3_/chanx_left_in[8]
@@ -6606,7 +6583,6 @@ set_disable_timing sb_3__4_/chanx_right_out[0]
set_disable_timing sb_3__4_/chanx_right_in[0]
set_disable_timing sb_3__4_/chanx_right_out[1]
set_disable_timing sb_3__4_/chanx_right_in[1]
-set_disable_timing sb_3__4_/chanx_right_out[2]
set_disable_timing sb_3__4_/chanx_right_in[2]
set_disable_timing sb_3__4_/chanx_right_out[3]
set_disable_timing sb_3__4_/chanx_right_in[3]
@@ -6626,7 +6602,6 @@ set_disable_timing sb_3__4_/chany_bottom_in[0]
set_disable_timing sb_3__4_/chany_bottom_out[0]
set_disable_timing sb_3__4_/chany_bottom_in[1]
set_disable_timing sb_3__4_/chany_bottom_out[1]
-set_disable_timing sb_3__4_/chany_bottom_in[2]
set_disable_timing sb_3__4_/chany_bottom_out[2]
set_disable_timing sb_3__4_/chany_bottom_in[3]
set_disable_timing sb_3__4_/chany_bottom_out[3]
@@ -6644,7 +6619,6 @@ set_disable_timing sb_3__4_/chany_bottom_in[9]
set_disable_timing sb_3__4_/chany_bottom_out[9]
set_disable_timing sb_3__4_/chanx_left_in[0]
set_disable_timing sb_3__4_/chanx_left_out[0]
-set_disable_timing sb_3__4_/chanx_left_in[1]
set_disable_timing sb_3__4_/chanx_left_out[1]
set_disable_timing sb_3__4_/chanx_left_in[2]
set_disable_timing sb_3__4_/chanx_left_out[2]
@@ -6765,7 +6739,6 @@ set_disable_timing sb_4__0_/chany_top_out[1]
set_disable_timing sb_4__0_/chany_top_in[1]
set_disable_timing sb_4__0_/chany_top_out[2]
set_disable_timing sb_4__0_/chany_top_in[2]
-set_disable_timing sb_4__0_/chany_top_out[3]
set_disable_timing sb_4__0_/chany_top_in[3]
set_disable_timing sb_4__0_/chany_top_out[4]
set_disable_timing sb_4__0_/chany_top_in[4]
@@ -6802,7 +6775,6 @@ set_disable_timing sb_4__0_/chanx_left_out[9]
set_disable_timing sb_4__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0]
set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0]
-set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0]
set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
@@ -6820,7 +6792,6 @@ set_disable_timing sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin
set_disable_timing sb_4__0_/mux_top_track_0/in[0]
set_disable_timing sb_4__0_/mux_top_track_2/in[0]
set_disable_timing sb_4__0_/mux_top_track_4/in[0]
-set_disable_timing sb_4__0_/mux_top_track_6/in[0]
set_disable_timing sb_4__0_/mux_top_track_8/in[0]
set_disable_timing sb_4__0_/mux_top_track_10/in[0]
set_disable_timing sb_4__0_/mux_top_track_12/in[0]
@@ -6875,14 +6846,12 @@ set_disable_timing sb_4__1_/chany_top_in[7]
set_disable_timing sb_4__1_/chany_top_out[8]
set_disable_timing sb_4__1_/chany_top_in[8]
set_disable_timing sb_4__1_/chany_top_out[9]
-set_disable_timing sb_4__1_/chany_top_in[9]
set_disable_timing sb_4__1_/chany_bottom_in[0]
set_disable_timing sb_4__1_/chany_bottom_out[0]
set_disable_timing sb_4__1_/chany_bottom_in[1]
set_disable_timing sb_4__1_/chany_bottom_out[1]
set_disable_timing sb_4__1_/chany_bottom_in[2]
set_disable_timing sb_4__1_/chany_bottom_out[2]
-set_disable_timing sb_4__1_/chany_bottom_in[3]
set_disable_timing sb_4__1_/chany_bottom_out[3]
set_disable_timing sb_4__1_/chany_bottom_in[4]
set_disable_timing sb_4__1_/chany_bottom_out[4]
@@ -6899,7 +6868,6 @@ set_disable_timing sb_4__1_/chany_bottom_out[9]
set_disable_timing sb_4__1_/chanx_left_in[0]
set_disable_timing sb_4__1_/chanx_left_out[0]
set_disable_timing sb_4__1_/chanx_left_in[1]
-set_disable_timing sb_4__1_/chanx_left_out[1]
set_disable_timing sb_4__1_/chanx_left_in[2]
set_disable_timing sb_4__1_/chanx_left_out[2]
set_disable_timing sb_4__1_/chanx_left_in[3]
@@ -6927,7 +6895,6 @@ set_disable_timing sb_4__1_/top_right_grid_left_width_0_height_0_subtile_6__pin_
set_disable_timing sb_4__1_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0]
-set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0]
set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
@@ -6979,7 +6946,6 @@ set_disable_timing sb_4__1_/mux_top_track_8/in[3]
set_disable_timing sb_4__1_/mux_left_track_5/in[0]
set_disable_timing sb_4__1_/mux_top_track_16/in[3]
set_disable_timing sb_4__1_/mux_left_track_7/in[0]
-set_disable_timing sb_4__1_/mux_left_track_3/in[1]
set_disable_timing sb_4__1_/mux_top_track_0/in[4]
set_disable_timing sb_4__1_/mux_left_track_9/in[1]
set_disable_timing sb_4__1_/mux_top_track_8/in[4]
@@ -7028,9 +6994,7 @@ set_disable_timing sb_4__2_/chany_top_in[5]
set_disable_timing sb_4__2_/chany_top_out[6]
set_disable_timing sb_4__2_/chany_top_in[6]
set_disable_timing sb_4__2_/chany_top_out[7]
-set_disable_timing sb_4__2_/chany_top_in[7]
set_disable_timing sb_4__2_/chany_top_out[8]
-set_disable_timing sb_4__2_/chany_top_in[8]
set_disable_timing sb_4__2_/chany_top_out[9]
set_disable_timing sb_4__2_/chany_top_in[9]
set_disable_timing sb_4__2_/chany_bottom_in[0]
@@ -7052,7 +7016,6 @@ set_disable_timing sb_4__2_/chany_bottom_out[7]
set_disable_timing sb_4__2_/chany_bottom_in[8]
set_disable_timing sb_4__2_/chany_bottom_out[8]
set_disable_timing sb_4__2_/chany_bottom_in[9]
-set_disable_timing sb_4__2_/chany_bottom_out[9]
set_disable_timing sb_4__2_/chanx_left_in[0]
set_disable_timing sb_4__2_/chanx_left_out[0]
set_disable_timing sb_4__2_/chanx_left_in[1]
@@ -7062,7 +7025,6 @@ set_disable_timing sb_4__2_/chanx_left_out[2]
set_disable_timing sb_4__2_/chanx_left_in[3]
set_disable_timing sb_4__2_/chanx_left_out[3]
set_disable_timing sb_4__2_/chanx_left_in[4]
-set_disable_timing sb_4__2_/chanx_left_out[4]
set_disable_timing sb_4__2_/chanx_left_in[5]
set_disable_timing sb_4__2_/chanx_left_out[5]
set_disable_timing sb_4__2_/chanx_left_in[6]
@@ -7073,7 +7035,6 @@ set_disable_timing sb_4__2_/chanx_left_in[8]
set_disable_timing sb_4__2_/chanx_left_out[8]
set_disable_timing sb_4__2_/chanx_left_in[9]
set_disable_timing sb_4__2_/chanx_left_out[9]
-set_disable_timing sb_4__2_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0]
set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0]
@@ -7128,7 +7089,6 @@ set_disable_timing sb_4__2_/mux_bottom_track_17/in[1]
set_disable_timing sb_4__2_/mux_left_track_11/in[0]
set_disable_timing sb_4__2_/mux_left_track_19/in[1]
set_disable_timing sb_4__2_/mux_bottom_track_1/in[2]
-set_disable_timing sb_4__2_/mux_left_track_9/in[0]
set_disable_timing sb_4__2_/mux_left_track_17/in[1]
set_disable_timing sb_4__2_/mux_top_track_0/in[3]
set_disable_timing sb_4__2_/mux_left_track_3/in[0]
@@ -7183,7 +7143,6 @@ set_disable_timing sb_4__3_/chany_top_in[4]
set_disable_timing sb_4__3_/chany_top_out[5]
set_disable_timing sb_4__3_/chany_top_in[5]
set_disable_timing sb_4__3_/chany_top_out[6]
-set_disable_timing sb_4__3_/chany_top_in[6]
set_disable_timing sb_4__3_/chany_top_out[7]
set_disable_timing sb_4__3_/chany_top_in[7]
set_disable_timing sb_4__3_/chany_top_out[8]
@@ -7205,9 +7164,7 @@ set_disable_timing sb_4__3_/chany_bottom_out[5]
set_disable_timing sb_4__3_/chany_bottom_in[6]
set_disable_timing sb_4__3_/chany_bottom_out[6]
set_disable_timing sb_4__3_/chany_bottom_in[7]
-set_disable_timing sb_4__3_/chany_bottom_out[7]
set_disable_timing sb_4__3_/chany_bottom_in[8]
-set_disable_timing sb_4__3_/chany_bottom_out[8]
set_disable_timing sb_4__3_/chany_bottom_in[9]
set_disable_timing sb_4__3_/chany_bottom_out[9]
set_disable_timing sb_4__3_/chanx_left_in[0]
@@ -7221,7 +7178,6 @@ set_disable_timing sb_4__3_/chanx_left_out[3]
set_disable_timing sb_4__3_/chanx_left_in[4]
set_disable_timing sb_4__3_/chanx_left_out[4]
set_disable_timing sb_4__3_/chanx_left_in[5]
-set_disable_timing sb_4__3_/chanx_left_out[5]
set_disable_timing sb_4__3_/chanx_left_in[6]
set_disable_timing sb_4__3_/chanx_left_out[6]
set_disable_timing sb_4__3_/chanx_left_in[7]
@@ -7237,7 +7193,6 @@ set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_2__pin_
set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0]
set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
-set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0]
@@ -7247,7 +7202,6 @@ set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_4__p
set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
-set_disable_timing sb_4__3_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0]
set_disable_timing sb_4__3_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0]
set_disable_timing sb_4__3_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
set_disable_timing sb_4__3_/mux_top_track_0/in[0]
@@ -7267,7 +7221,6 @@ set_disable_timing sb_4__3_/mux_bottom_track_9/in[3]
set_disable_timing sb_4__3_/mux_bottom_track_17/in[3]
set_disable_timing sb_4__3_/mux_bottom_track_1/in[5]
set_disable_timing sb_4__3_/mux_bottom_track_9/in[4]
-set_disable_timing sb_4__3_/mux_bottom_track_17/in[4]
set_disable_timing sb_4__3_/mux_left_track_1/in[2]
set_disable_timing sb_4__3_/mux_left_track_3/in[2]
set_disable_timing sb_4__3_/mux_bottom_track_1/in[0]
@@ -7282,7 +7235,6 @@ set_disable_timing sb_4__3_/mux_left_track_15/in[0]
set_disable_timing sb_4__3_/mux_bottom_track_9/in[1]
set_disable_timing sb_4__3_/mux_left_track_13/in[0]
set_disable_timing sb_4__3_/mux_bottom_track_17/in[1]
-set_disable_timing sb_4__3_/mux_left_track_11/in[0]
set_disable_timing sb_4__3_/mux_left_track_19/in[1]
set_disable_timing sb_4__3_/mux_bottom_track_1/in[2]
set_disable_timing sb_4__3_/mux_left_track_9/in[0]
@@ -7340,7 +7292,6 @@ set_disable_timing sb_4__4_/chany_bottom_out[4]
set_disable_timing sb_4__4_/chany_bottom_in[5]
set_disable_timing sb_4__4_/chany_bottom_out[5]
set_disable_timing sb_4__4_/chany_bottom_in[6]
-set_disable_timing sb_4__4_/chany_bottom_out[6]
set_disable_timing sb_4__4_/chany_bottom_in[7]
set_disable_timing sb_4__4_/chany_bottom_out[7]
set_disable_timing sb_4__4_/chany_bottom_in[8]
@@ -7351,7 +7302,6 @@ set_disable_timing sb_4__4_/chanx_left_in[0]
set_disable_timing sb_4__4_/chanx_left_out[0]
set_disable_timing sb_4__4_/chanx_left_in[1]
set_disable_timing sb_4__4_/chanx_left_out[1]
-set_disable_timing sb_4__4_/chanx_left_in[2]
set_disable_timing sb_4__4_/chanx_left_out[2]
set_disable_timing sb_4__4_/chanx_left_in[3]
set_disable_timing sb_4__4_/chanx_left_out[3]
@@ -7373,7 +7323,6 @@ set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_2__p
set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0]
set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
-set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_4__4_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0]
set_disable_timing sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
@@ -7391,7 +7340,6 @@ set_disable_timing sb_4__4_/mux_bottom_track_5/in[0]
set_disable_timing sb_4__4_/mux_bottom_track_7/in[0]
set_disable_timing sb_4__4_/mux_bottom_track_9/in[0]
set_disable_timing sb_4__4_/mux_bottom_track_11/in[0]
-set_disable_timing sb_4__4_/mux_bottom_track_13/in[0]
set_disable_timing sb_4__4_/mux_bottom_track_15/in[0]
set_disable_timing sb_4__4_/mux_bottom_track_17/in[0]
set_disable_timing sb_4__4_/mux_left_track_1/in[1]
@@ -7943,229 +7891,76 @@ set_disable_timing grid_clb_2__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_
# Disable Timing for grid[2][4]
#######################################
#######################################
-# Disable Timing for unused resources in grid[2][4][0]
+# Disable Timing for unused grid[2][4][0]
#######################################
#######################################
-# Disable unused pins for pb_graph_node clb[0]
+# Disable all the ports for pb_graph_node clb[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_I[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_I[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_I[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_I[5]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_I[6]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_I[7]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_I[8]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_I[9]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_O[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_O[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_O[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/clb_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/*
#######################################
-# Disable unused mux_inputs for pb_graph_node clb[0]
+# Disable all the ports for pb_graph_node fle[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[7]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/*
#######################################
-# Disable unused pins for pb_graph_node fle[0]
+# Disable all the ports for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/*
#######################################
-# Disable unused mux_inputs for pb_graph_node fle[0]
+# Disable all the ports for pb_graph_node lut4[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/*
#######################################
-# Disable unused pins for pb_graph_node ble4[0]
+# Disable all the ports for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/*
#######################################
-# Disable unused mux_inputs for pb_graph_node ble4[0]
+# Disable all the ports for pb_graph_node fle[1]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/*
#######################################
-# Disable unused pins for pb_graph_node lut4[0]
+# Disable all the ports for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/*
#######################################
-# Disable unused pins for pb_graph_node ff[0]
+# Disable all the ports for pb_graph_node lut4[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/*
#######################################
-# Disable unused pins for pb_graph_node fle[1]
+# Disable all the ports for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/*
#######################################
-# Disable unused mux_inputs for pb_graph_node fle[1]
+# Disable all the ports for pb_graph_node fle[2]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/*
#######################################
-# Disable unused pins for pb_graph_node ble4[0]
+# Disable all the ports for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/*
#######################################
-# Disable unused mux_inputs for pb_graph_node ble4[0]
+# Disable all the ports for pb_graph_node lut4[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/*
#######################################
-# Disable unused pins for pb_graph_node lut4[0]
+# Disable all the ports for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/*
#######################################
-# Disable unused pins for pb_graph_node ff[0]
+# Disable all the ports for pb_graph_node fle[3]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/*
#######################################
-# Disable unused pins for pb_graph_node fle[2]
+# Disable all the ports for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/*
#######################################
-# Disable unused mux_inputs for pb_graph_node fle[2]
+# Disable all the ports for pb_graph_node lut4[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/*
#######################################
-# Disable unused pins for pb_graph_node ble4[0]
+# Disable all the ports for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0]
-#######################################
-# Disable unused mux_inputs for pb_graph_node ble4[0]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0]
-#######################################
-# Disable unused pins for pb_graph_node lut4[0]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0]
-#######################################
-# Disable unused pins for pb_graph_node ff[0]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0]
-#######################################
-# Disable unused pins for pb_graph_node fle[3]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0]
-#######################################
-# Disable unused mux_inputs for pb_graph_node fle[3]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_5_/in[0]
-#######################################
-# Disable unused pins for pb_graph_node ble4[0]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0]
-#######################################
-# Disable unused mux_inputs for pb_graph_node ble4[0]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0]
-#######################################
-# Disable unused pins for pb_graph_node lut4[0]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2]
-#######################################
-# Disable unused pins for pb_graph_node ff[0]
-#######################################
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0]
-set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0]
+set_disable_timing grid_clb_2__4_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/*
#######################################
# Disable Timing for grid[3][1]
#######################################
@@ -8614,76 +8409,229 @@ set_disable_timing grid_clb_4__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_
# Disable Timing for grid[4][3]
#######################################
#######################################
-# Disable Timing for unused grid[4][3][0]
+# Disable Timing for unused resources in grid[4][3][0]
#######################################
#######################################
-# Disable all the ports for pb_graph_node clb[0]
+# Disable unused pins for pb_graph_node clb[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[4]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[5]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[6]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[9]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_clk[0]
#######################################
-# Disable all the ports for pb_graph_node fle[0]
+# Disable unused mux_inputs for pb_graph_node clb[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//direct_interc_7_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13]
#######################################
-# Disable all the ports for pb_graph_node ble4[0]
+# Disable unused pins for pb_graph_node fle[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0]
#######################################
-# Disable all the ports for pb_graph_node lut4[0]
+# Disable unused mux_inputs for pb_graph_node fle[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0]
#######################################
-# Disable all the ports for pb_graph_node ff[0]
+# Disable unused pins for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0]
#######################################
-# Disable all the ports for pb_graph_node fle[1]
+# Disable unused mux_inputs for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0]
#######################################
-# Disable all the ports for pb_graph_node ble4[0]
+# Disable unused pins for pb_graph_node lut4[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0]
#######################################
-# Disable all the ports for pb_graph_node lut4[0]
+# Disable unused pins for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0]
#######################################
-# Disable all the ports for pb_graph_node ff[0]
+# Disable unused pins for pb_graph_node fle[1]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0]
#######################################
-# Disable all the ports for pb_graph_node fle[2]
+# Disable unused mux_inputs for pb_graph_node fle[1]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0]
#######################################
-# Disable all the ports for pb_graph_node ble4[0]
+# Disable unused pins for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0]
#######################################
-# Disable all the ports for pb_graph_node lut4[0]
+# Disable unused mux_inputs for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0]
#######################################
-# Disable all the ports for pb_graph_node ff[0]
+# Disable unused pins for pb_graph_node lut4[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0]
#######################################
-# Disable all the ports for pb_graph_node fle[3]
+# Disable unused pins for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0]
#######################################
-# Disable all the ports for pb_graph_node ble4[0]
+# Disable unused pins for pb_graph_node fle[2]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0]
#######################################
-# Disable all the ports for pb_graph_node lut4[0]
+# Disable unused mux_inputs for pb_graph_node fle[2]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0]
#######################################
-# Disable all the ports for pb_graph_node ff[0]
+# Disable unused pins for pb_graph_node ble4[0]
#######################################
-set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/*
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0]
+#######################################
+# Disable unused mux_inputs for pb_graph_node ble4[0]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0]
+#######################################
+# Disable unused pins for pb_graph_node lut4[0]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0]
+#######################################
+# Disable unused pins for pb_graph_node ff[0]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0]
+#######################################
+# Disable unused pins for pb_graph_node fle[3]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0]
+#######################################
+# Disable unused mux_inputs for pb_graph_node fle[3]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_5_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node ble4[0]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0]
+#######################################
+# Disable unused mux_inputs for pb_graph_node ble4[0]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0]
+#######################################
+# Disable unused pins for pb_graph_node lut4[0]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2]
+#######################################
+# Disable unused pins for pb_graph_node ff[0]
+#######################################
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0]
+set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0]
#######################################
# Disable Timing for grid[4][4]
#######################################
@@ -8875,20 +8823,16 @@ set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__1/*
#######################################
set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused resources in grid[2][5][2]
+# Disable Timing for unused grid[2][5][2]
#######################################
#######################################
-# Disable unused pins for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__2/io_inpad[0]
+set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__2/*
#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node iopad[0]
#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__2//direct_interc_0_/in[0]
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
+set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[2][5][3]
#######################################
@@ -8901,35 +8845,27 @@ set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__3/*
#######################################
set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused resources in grid[2][5][4]
+# Disable Timing for unused grid[2][5][4]
#######################################
#######################################
-# Disable unused pins for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__4/io_outpad[0]
+set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__4/*
#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node iopad[0]
#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__4//direct_interc_1_/in[0]
+set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
-#######################################
-# Disable Timing for unused resources in grid[2][5][5]
+# Disable Timing for unused grid[2][5][5]
#######################################
#######################################
-# Disable unused pins for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__5/io_outpad[0]
+set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__5/*
#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node iopad[0]
#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__5//direct_interc_1_/in[0]
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
+set_disable_timing grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[2][5][6]
#######################################
@@ -8967,16 +8903,20 @@ set_disable_timing grid_io_top_3__5_/logical_tile_io_mode_io__0/*
#######################################
set_disable_timing grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused grid[3][5][1]
+# Disable Timing for unused resources in grid[3][5][1]
#######################################
#######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_top_3__5_/logical_tile_io_mode_io__1/*
+set_disable_timing grid_io_top_3__5_/logical_tile_io_mode_io__1/io_inpad[0]
#######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_top_3__5_/logical_tile_io_mode_io__1//direct_interc_0_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
#######################################
# Disable Timing for unused grid[3][5][2]
#######################################
@@ -9204,16 +9144,20 @@ set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__5/*
#######################################
set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused grid[5][4][6]
+# Disable Timing for unused resources in grid[5][4][6]
#######################################
#######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/*
+set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/io_outpad[0]
#######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6//direct_interc_1_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for unused grid[5][4][7]
#######################################
@@ -9433,16 +9377,20 @@ set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__1/*
#######################################
set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused grid[5][1][2]
+# Disable Timing for unused resources in grid[5][1][2]
#######################################
#######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/*
+set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/io_outpad[0]
#######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2//direct_interc_1_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for unused grid[5][1][3]
#######################################
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v
index d37f5c15c..a696e74e4 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v
@@ -42,14 +42,14 @@ wire [0:0] clk_fm;
// ----- End Connect Global ports of FPGA top module -----
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
-// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[13] -----
- assign gfpga_pad_GPIO_PAD_fm[13] = a[0];
+// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[38] -----
+ assign gfpga_pad_GPIO_PAD_fm[38] = a[0];
-// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
- assign gfpga_pad_GPIO_PAD_fm[12] = b[0];
+// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[58] -----
+ assign gfpga_pad_GPIO_PAD_fm[58] = b[0];
-// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[10] -----
- assign c[0] = gfpga_pad_GPIO_PAD_fm[10];
+// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[17] -----
+ assign c[0] = gfpga_pad_GPIO_PAD_fm[17];
// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
@@ -62,11 +62,13 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[19] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[20] = 1'b0;
@@ -87,7 +89,6 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0;
@@ -107,7 +108,6 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[55] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[56] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[57] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[58] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[59] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[60] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[61] = 1'b0;
@@ -529,10 +529,10 @@ initial begin
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
- force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
- force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
- force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
+ force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
+ force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
+ force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
+ force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
@@ -557,14 +557,14 @@ initial begin
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}};
- force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}};
+ force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
+ force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b1101;
- force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b0010;
+ force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
+ force U0_formal_verification.grid_clb_2__4_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
force U0_formal_verification.grid_clb_3__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
@@ -865,10 +865,10 @@ initial begin
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
- force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
- force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
+ force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
+ force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
+ force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
@@ -893,14 +893,14 @@ initial begin
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
- force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
+ force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1110;
+ force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0001;
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
- force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
+ force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0001;
+ force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1110;
force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
@@ -969,8 +969,8 @@ initial begin
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
- force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
- force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
+ force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
+ force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@@ -983,8 +983,8 @@ initial begin
force U0_formal_verification.grid_io_top_2__5_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
- force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
- force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
+ force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
+ force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_3__5_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@@ -1241,8 +1241,8 @@ initial begin
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:3] = 4'b0011;
- force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:3] = 4'b1100;
+ force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
+ force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1337,8 +1337,8 @@ initial begin
force U0_formal_verification.sb_0__4_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__4_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__4_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_out[0:1] = 2'b01;
- force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_outb[0:1] = 2'b10;
+ force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
+ force U0_formal_verification.sb_0__4_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__4_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__4_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__4_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
@@ -1409,8 +1409,8 @@ initial begin
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
- force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
+ force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = 4'b0111;
+ force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = 4'b1000;
force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_1__2_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1457,8 +1457,8 @@ initial begin
force U0_formal_verification.sb_1__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = {4{1'b0}};
- force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}};
+ force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0011;
+ force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1100;
force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_1__4_.mem_right_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1531,8 +1531,8 @@ initial begin
force U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:3] = 4'b0111;
- force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:3] = 4'b1000;
+ force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
+ force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
@@ -1593,8 +1593,8 @@ initial begin
force U0_formal_verification.sb_2__4_.mem_right_track_16.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_2__4_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__4_.mem_bottom_track_1.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_out[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b0}};
+ force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}};
+ force U0_formal_verification.sb_2__4_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__4_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__4_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__4_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
@@ -1613,10 +1613,10 @@ initial begin
force U0_formal_verification.sb_2__4_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__4_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_2__4_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_out[0:3] = 4'b0010;
- force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = 4'b1101;
- force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = 4'b0010;
- force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = 4'b1101;
+ force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
+ force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
+ force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
+ force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
@@ -1641,8 +1641,8 @@ initial begin
force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
- force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
+ force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = 4'b0111;
+ force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = 4'b1000;
force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_3__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1683,8 +1683,8 @@ initial begin
force U0_formal_verification.sb_3__2_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
- force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
+ force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = 4'b0101;
+ force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = 4'b1010;
force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
@@ -1751,8 +1751,8 @@ initial begin
force U0_formal_verification.sb_4__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
@@ -1795,8 +1795,8 @@ initial begin
force U0_formal_verification.sb_4__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = 2'b01;
+ force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = 2'b10;
force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
@@ -1833,8 +1833,8 @@ initial begin
force U0_formal_verification.sb_4__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
@@ -1855,8 +1855,8 @@ initial begin
force U0_formal_verification.sb_4__3_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
- force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
- force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
+ force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = 4'b0101;
+ force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = 4'b1010;
force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__3_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
@@ -1867,8 +1867,8 @@ initial begin
force U0_formal_verification.sb_4__3_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__3_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
@@ -1889,8 +1889,8 @@ initial begin
force U0_formal_verification.sb_4__4_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_4__4_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
@@ -2055,8 +2055,8 @@ initial begin
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_out[0:2] = 3'b001;
- force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_outb[0:2] = 3'b110;
+ force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
+ force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_4.mem_out[0:2] = {3{1'b0}};
@@ -2067,10 +2067,10 @@ initial begin
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_2__4_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_out[0:2] = 3'b010;
- force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_outb[0:2] = 3'b101;
- force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_out[0:2] = 3'b011;
- force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_outb[0:2] = 3'b100;
+ force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
+ force U0_formal_verification.cbx_2__4_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
+ force U0_formal_verification.cbx_2__4_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_2__4_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__4_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_3__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
@@ -2133,8 +2133,8 @@ initial begin
force U0_formal_verification.cbx_3__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
- force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
+ force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b1}};
+ force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_3__4_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
@@ -2209,8 +2209,8 @@ initial begin
force U0_formal_verification.cbx_4__3_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = 2'b01;
+ force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = 2'b10;
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
@@ -2415,8 +2415,8 @@ initial begin
force U0_formal_verification.cby_3__2_.mem_right_ipin_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
- force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_3__3_.mem_right_ipin_1.mem_out[0:1] = {2{1'b0}};
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit
index e6bc11285..fc17891b4 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit
@@ -213,10 +213,7 @@
0
0
0
-1
0
-1
-1
0
0
0
@@ -225,10 +222,6 @@
0
0
0
-1
-1
-1
-1
0
0
0
@@ -277,25 +270,6 @@
0
0
0
-1
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-1
-0
-1
-0
-1
-0
-1
-0
0
0
0
@@ -830,6 +804,7 @@
0
0
0
+1
0
0
0
@@ -853,6 +828,8 @@
0
0
0
+1
+1
0
0
0
@@ -863,7 +840,9 @@
0
0
0
+1
0
+1
0
0
0
@@ -885,6 +864,7 @@
0
0
0
+1
0
0
0
@@ -897,6 +877,9 @@
0
0
0
+1
+1
+1
0
0
0
@@ -945,6 +928,7 @@
0
0
0
+1
0
0
0
@@ -955,9 +939,13 @@
0
0
0
+1
0
+1
0
+1
0
+1
0
0
0
@@ -1069,6 +1057,8 @@
0
0
0
+1
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0
0
0
@@ -1244,6 +1234,8 @@
0
0
0
+1
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0
0
0
@@ -1271,7 +1263,9 @@
0
0
0
+1
0
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0
0
0
@@ -1729,6 +1723,9 @@
0
0
0
+1
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0
0
0
@@ -2111,9 +2108,6 @@
0
0
0
-1
-1
-1
0
0
0
@@ -2365,6 +2359,9 @@
0
0
0
+1
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0
0
0
@@ -2565,6 +2562,7 @@
0
0
0
+1
0
0
0
@@ -2819,6 +2817,8 @@
0
0
0
+1
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0
0
0
@@ -3625,8 +3625,8 @@
0
0
0
-1
-1
+0
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0
0
1
@@ -3805,7 +3805,7 @@
0
0
0
-1
+0
0
0
0
@@ -3899,8 +3899,8 @@
0
0
0
-0
-0
+1
+1
0
0
1
@@ -3908,16 +3908,13 @@
1
1
1
-0
+1
1
1
0
0
-1
-1
0
0
-1
0
0
0
@@ -3934,7 +3931,6 @@
0
0
0
-1
0
0
0
@@ -3944,11 +3940,9 @@
0
0
0
-1
0
0
0
-1
0
0
0
@@ -3971,8 +3965,14 @@
0
0
0
-1
-1
+0
+0
+0
+0
+0
+0
+0
+0
0
0
0
@@ -3993,11 +3993,8 @@
1
1
1
-1
-1
-0
-0
0
+1
0
0
0
@@ -4024,6 +4021,9 @@
0
0
0
+1
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0
0
0
@@ -4133,8 +4133,8 @@
0
0
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-0
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0
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diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml
index 2705e277d..10e19c6be 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml
@@ -430,13 +430,13 @@
-
+
-
+
-
+
@@ -454,13 +454,13 @@
-
+
-
+
-
+
-
+
@@ -558,7 +558,7 @@
-
+
@@ -580,19 +580,19 @@
-
+
-
+
-
+
-
+
@@ -1612,7 +1612,7 @@
-
+
@@ -1660,9 +1660,9 @@
-
+
-
+
@@ -1684,11 +1684,11 @@
-
+
-
+
@@ -1732,7 +1732,7 @@
-
+
@@ -1758,11 +1758,11 @@
-
+
-
+
-
+
@@ -1860,7 +1860,7 @@
-
+
@@ -1882,19 +1882,19 @@
-
+
-
+
-
+
-
+
@@ -2118,9 +2118,9 @@
-
+
-
+
@@ -2472,9 +2472,9 @@
-
+
-
+
@@ -2530,11 +2530,11 @@
-
+
-
+
@@ -3450,11 +3450,11 @@
-
+
-
+
-
+
@@ -4226,11 +4226,11 @@
-
+
-
+
-
+
@@ -4722,11 +4722,11 @@
-
+
-
+
-
+
@@ -5128,7 +5128,7 @@
-
+
@@ -5638,9 +5638,9 @@
-
+
-
+
@@ -7254,9 +7254,9 @@
-
+
-
+
@@ -7614,7 +7614,7 @@
-
+
@@ -7802,9 +7802,9 @@
-
+
-
+
@@ -7820,7 +7820,7 @@
-
+
@@ -7830,15 +7830,15 @@
-
+
-
+
-
+
@@ -7872,7 +7872,7 @@
-
+
@@ -7892,7 +7892,7 @@
-
+
@@ -7900,7 +7900,7 @@
-
+
@@ -7946,9 +7946,9 @@
-
+
-
+
@@ -7990,7 +7990,7 @@
-
+
@@ -8046,11 +8046,11 @@
-
+
-
+
-
+
@@ -8270,9 +8270,9 @@
-
+
-
+
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
index 0308ebd1f..fd78aece6 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
@@ -3565,13 +3565,13 @@
-
+
-
+
-
+
-
+
@@ -3593,16 +3593,12 @@
-
-
-
-
-
+
-
+
-
+
@@ -3818,30 +3814,14 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
-
-
-
+
+
+
+
+
@@ -3885,30 +3865,14 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
-
+
+
+
-
+
@@ -6989,13 +6953,13 @@
-
+
-
+
-
+
-
+
@@ -7017,12 +6981,16 @@
-
+
+
+
+
+
-
+
-
+
@@ -7238,13 +7206,29 @@
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
+
+
+
+
@@ -7289,14 +7273,30 @@
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
-
+
@@ -7959,7 +7959,7 @@
-
+
@@ -8073,7 +8073,7 @@
-
+
@@ -10202,7 +10202,7 @@
-
+
@@ -10210,13 +10210,13 @@
-
+
-
+
-
-
+
+
@@ -10431,7 +10431,7 @@
-
+
@@ -10515,8 +10515,8 @@
-
-
+
+
@@ -10540,7 +10540,7 @@
-
+
@@ -10721,7 +10721,7 @@
-
+
@@ -10744,7 +10744,7 @@
-
+
@@ -10795,7 +10795,7 @@
-
+
@@ -10854,7 +10854,7 @@
-
+
@@ -11014,7 +11014,7 @@
-
+
@@ -11241,14 +11241,14 @@
-
+
-
+
-
+
-
+
@@ -11348,7 +11348,7 @@
-
+
@@ -11792,8 +11792,8 @@
-
-
+
+
@@ -11932,8 +11932,8 @@
-
-
+
+
@@ -11989,7 +11989,7 @@
-
+
@@ -12071,7 +12071,7 @@
-
+
@@ -12083,13 +12083,13 @@
-
+
-
+
-
-
-
+
+
+
@@ -12101,7 +12101,7 @@
-
+
@@ -12239,7 +12239,7 @@
-
+
@@ -12295,7 +12295,7 @@
-
+
@@ -12351,7 +12351,7 @@
-
+
@@ -12380,7 +12380,7 @@
-
+
@@ -12407,8 +12407,8 @@
-
-
+
+
@@ -12520,7 +12520,7 @@
-
+
@@ -12575,7 +12575,7 @@
-
+
@@ -12687,7 +12687,7 @@
-
+
@@ -12741,7 +12741,7 @@
-
+
@@ -12749,13 +12749,13 @@
-
+
-
+
-
-
+
+
@@ -12766,7 +12766,7 @@
-
+
@@ -12793,13 +12793,13 @@
-
+
-
+
@@ -12856,7 +12856,7 @@
-
+
@@ -12893,7 +12893,7 @@
-
+
@@ -12910,7 +12910,7 @@
-
+
@@ -13001,8 +13001,8 @@
-
-
+
+
@@ -13056,7 +13056,7 @@
-
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@@ -13390,7 +13390,7 @@
-
+
@@ -13472,7 +13472,7 @@
-
+
@@ -13584,7 +13584,7 @@
-
+
@@ -13610,7 +13610,7 @@
-
+
@@ -13622,13 +13622,13 @@
-
+
-
+
-
-
-
+
+
+
@@ -13669,7 +13669,7 @@
-
+
@@ -13696,7 +13696,7 @@
-
+
@@ -13750,7 +13750,7 @@
-
+
@@ -13777,7 +13777,7 @@
-
+
@@ -13864,7 +13864,7 @@
-
+
@@ -13890,7 +13890,7 @@
-
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@@ -13916,7 +13916,7 @@
-
+
@@ -13947,7 +13947,7 @@
-
+
@@ -13972,11 +13972,11 @@
-
+
-
+
@@ -14028,7 +14028,7 @@
-
+
@@ -14059,7 +14059,7 @@
-
+
@@ -14168,7 +14168,7 @@
-
+
@@ -14222,7 +14222,7 @@
-
+
@@ -14253,7 +14253,7 @@
-
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@@ -14334,11 +14334,11 @@
-
+
-
+
@@ -14368,7 +14368,7 @@
-
+
@@ -14444,7 +14444,7 @@
-
+
@@ -14461,16 +14461,16 @@
-
+
-
+
-
-
-
+
+
+
@@ -14606,7 +14606,7 @@
-
+
@@ -14658,16 +14658,16 @@
-
+
-
+
-
+
-
+
@@ -14684,16 +14684,16 @@
-
+
-
+
-
+
-
+
@@ -14985,7 +14985,7 @@
-
+
@@ -14997,13 +14997,13 @@
-
+
-
+
-
-
-
+
+
+
@@ -15153,7 +15153,7 @@
-
+
@@ -15265,7 +15265,7 @@
-
+
@@ -15322,7 +15322,7 @@
-
+
@@ -15376,7 +15376,7 @@
-
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@@ -15434,7 +15434,7 @@
-
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@@ -15516,7 +15516,7 @@
-
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@@ -15572,7 +15572,7 @@
-
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@@ -15580,13 +15580,13 @@
-
+
-
+
-
+
-
+
@@ -15601,7 +15601,7 @@
-
+
@@ -15654,7 +15654,7 @@
-
+
@@ -15685,7 +15685,7 @@
-
+
@@ -15739,7 +15739,7 @@
-
+
@@ -15822,7 +15822,7 @@
-
+
@@ -15934,7 +15934,7 @@
-
+
@@ -15963,7 +15963,7 @@
-
+
@@ -16020,7 +16020,7 @@
-
+
@@ -16043,7 +16043,7 @@
-
+
@@ -16067,7 +16067,7 @@
-
+
@@ -16251,7 +16251,7 @@
-
+
@@ -16384,15 +16384,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -16791,7 +16791,7 @@
-
+
@@ -16836,15 +16836,15 @@
-
+
-
+
-
+
-
+
@@ -16963,7 +16963,7 @@
-
+
@@ -17000,7 +17000,7 @@
-
+
@@ -17082,7 +17082,7 @@
-
+
@@ -17234,15 +17234,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -17325,7 +17325,7 @@
-
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@@ -17374,7 +17374,7 @@
-
+
@@ -17478,23 +17478,23 @@
-
+
-
+
-
+
-
+
-
+
-
+
@@ -17596,15 +17596,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -17707,7 +17707,7 @@
-
+
@@ -17796,15 +17796,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -18266,7 +18266,7 @@
-
+
@@ -18406,9 +18406,9 @@
-
+
-
+
@@ -18613,7 +18613,7 @@
-
+
@@ -18633,7 +18633,7 @@
-
+
@@ -18697,7 +18697,7 @@
-
+
@@ -18718,7 +18718,7 @@
-
+
@@ -18738,7 +18738,7 @@
-
+
@@ -18802,7 +18802,7 @@
-
+
@@ -19071,7 +19071,7 @@
-
+
@@ -19131,7 +19131,7 @@
-
+
@@ -19214,7 +19214,7 @@
-
+
@@ -19356,7 +19356,7 @@
-
+
@@ -19436,7 +19436,7 @@
-
+
@@ -19480,16 +19480,16 @@
-
+
-
+
-
+
-
+
@@ -19502,7 +19502,7 @@
-
+
@@ -19521,7 +19521,7 @@
-
+
@@ -19541,7 +19541,7 @@
-
+
@@ -19585,7 +19585,7 @@
-
+
@@ -19607,14 +19607,14 @@
-
+
-
+
-
+
-
+
@@ -19626,17 +19626,17 @@
-
+
-
+
-
+
-
-
+
+
@@ -19646,7 +19646,7 @@
-
+
@@ -19936,7 +19936,7 @@
-
+
@@ -20019,9 +20019,9 @@
-
+
-
+
@@ -20121,7 +20121,7 @@
-
+
@@ -20283,18 +20283,18 @@
-
+
-
+
-
-
-
-
+
+
+
+
@@ -20388,7 +20388,7 @@
-
+
@@ -20744,7 +20744,7 @@
-
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@@ -20926,7 +20926,7 @@
-
+
@@ -20969,7 +20969,7 @@
-
+
@@ -21069,14 +21069,14 @@
-
+
-
+
-
+
-
+
@@ -21130,7 +21130,7 @@
-
+
@@ -21235,7 +21235,7 @@
-
+
@@ -21527,7 +21527,7 @@
-
+
@@ -21629,7 +21629,7 @@
-
+
@@ -21757,7 +21757,7 @@
-
+
@@ -21859,7 +21859,7 @@
-
+
@@ -21984,7 +21984,7 @@
-
+
@@ -22089,7 +22089,7 @@
-
+
@@ -22350,7 +22350,7 @@
-
+
@@ -22469,7 +22469,7 @@
-
+
@@ -22705,7 +22705,7 @@
-
+
@@ -22782,7 +22782,7 @@
-
+
@@ -22862,7 +22862,7 @@
-
+
@@ -23036,7 +23036,7 @@
-
+
@@ -23155,15 +23155,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -23271,7 +23271,7 @@
-
+
@@ -23393,7 +23393,7 @@
-
+
@@ -23498,7 +23498,7 @@
-
+
@@ -23644,7 +23644,7 @@
-
+
@@ -23747,7 +23747,7 @@
-
+
@@ -23829,7 +23829,7 @@
-
+
@@ -23850,7 +23850,7 @@
-
+
@@ -23934,7 +23934,7 @@
-
+
@@ -23955,7 +23955,7 @@
-
+
@@ -24035,7 +24035,7 @@
-
+
@@ -24140,7 +24140,7 @@
-
+
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc
index c6506b0bd..0f5e878af 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc
@@ -14,7 +14,7 @@ set_units -time s
##################################################
# Create clock
##################################################
-create_clock -name clk[0] -period 1.084572876e-09 -waveform {0 5.42286438e-10} [get_ports {clk[0]}]
+create_clock -name clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10} [get_ports {clk[0]}]
##################################################
# Create programmable clock
##################################################
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml
index feb054404..b9d5872be 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml
@@ -3,7 +3,7 @@
-->
-
-
-
+
+
+
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
index 07dbdc35f..c6df32c2a 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
@@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
initial begin
clk[0] <= 1'b0;
while(1) begin
- #0.5561901927
+ #0.4485172927
clk[0] <= !clk[0];
end
end
@@ -109,7 +109,7 @@ initial begin
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
- #7.786663055
+ #6.279242039
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
index f1cbe1373..0ab31beb3 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
@@ -9,14 +9,14 @@
##################################################
# Create clock
##################################################
-create_clock clk[0] -period 1.11238041e-09 -waveform {0 5.56190205e-10}
+create_clock clk[0] -period 8.970345577e-10 -waveform {0 4.485172789e-10}
##################################################
# Create input and output delays for used I/Os
##################################################
-set_input_delay -clock clk[0] -max 1.11238041e-09 gfpga_pad_GPIO_PAD[12]
-set_input_delay -clock clk[0] -max 1.11238041e-09 gfpga_pad_GPIO_PAD[9]
-set_output_delay -clock clk[0] -max 1.11238041e-09 gfpga_pad_GPIO_PAD[11]
+set_input_delay -clock clk[0] -max 8.970345577e-10 gfpga_pad_GPIO_PAD[39]
+set_input_delay -clock clk[0] -max 8.970345577e-10 gfpga_pad_GPIO_PAD[48]
+set_output_delay -clock clk[0] -max 8.970345577e-10 gfpga_pad_GPIO_PAD[34]
##################################################
# Disable timing for unused I/Os
@@ -30,7 +30,10 @@ set_disable_timing gfpga_pad_GPIO_PAD[5]
set_disable_timing gfpga_pad_GPIO_PAD[6]
set_disable_timing gfpga_pad_GPIO_PAD[7]
set_disable_timing gfpga_pad_GPIO_PAD[8]
+set_disable_timing gfpga_pad_GPIO_PAD[9]
set_disable_timing gfpga_pad_GPIO_PAD[10]
+set_disable_timing gfpga_pad_GPIO_PAD[11]
+set_disable_timing gfpga_pad_GPIO_PAD[12]
set_disable_timing gfpga_pad_GPIO_PAD[13]
set_disable_timing gfpga_pad_GPIO_PAD[14]
set_disable_timing gfpga_pad_GPIO_PAD[15]
@@ -52,12 +55,10 @@ set_disable_timing gfpga_pad_GPIO_PAD[30]
set_disable_timing gfpga_pad_GPIO_PAD[31]
set_disable_timing gfpga_pad_GPIO_PAD[32]
set_disable_timing gfpga_pad_GPIO_PAD[33]
-set_disable_timing gfpga_pad_GPIO_PAD[34]
set_disable_timing gfpga_pad_GPIO_PAD[35]
set_disable_timing gfpga_pad_GPIO_PAD[36]
set_disable_timing gfpga_pad_GPIO_PAD[37]
set_disable_timing gfpga_pad_GPIO_PAD[38]
-set_disable_timing gfpga_pad_GPIO_PAD[39]
set_disable_timing gfpga_pad_GPIO_PAD[40]
set_disable_timing gfpga_pad_GPIO_PAD[41]
set_disable_timing gfpga_pad_GPIO_PAD[42]
@@ -66,7 +67,6 @@ set_disable_timing gfpga_pad_GPIO_PAD[44]
set_disable_timing gfpga_pad_GPIO_PAD[45]
set_disable_timing gfpga_pad_GPIO_PAD[46]
set_disable_timing gfpga_pad_GPIO_PAD[47]
-set_disable_timing gfpga_pad_GPIO_PAD[48]
set_disable_timing gfpga_pad_GPIO_PAD[49]
set_disable_timing gfpga_pad_GPIO_PAD[50]
set_disable_timing gfpga_pad_GPIO_PAD[51]
@@ -229,10 +229,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
##################################################
set_disable_timing cbx_1__0_/chanx_left_in[0]
set_disable_timing cbx_1__0_/chanx_right_in[0]
-set_disable_timing cbx_1__0_/chanx_left_in[1]
set_disable_timing cbx_1__0_/chanx_right_in[1]
set_disable_timing cbx_1__0_/chanx_left_in[2]
-set_disable_timing cbx_1__0_/chanx_right_in[2]
set_disable_timing cbx_1__0_/chanx_left_in[3]
set_disable_timing cbx_1__0_/chanx_right_in[3]
set_disable_timing cbx_1__0_/chanx_left_in[4]
@@ -249,10 +247,8 @@ set_disable_timing cbx_1__0_/chanx_left_in[9]
set_disable_timing cbx_1__0_/chanx_right_in[9]
set_disable_timing cbx_1__0_/chanx_left_out[0]
set_disable_timing cbx_1__0_/chanx_right_out[0]
-set_disable_timing cbx_1__0_/chanx_left_out[1]
set_disable_timing cbx_1__0_/chanx_right_out[1]
set_disable_timing cbx_1__0_/chanx_left_out[2]
-set_disable_timing cbx_1__0_/chanx_right_out[2]
set_disable_timing cbx_1__0_/chanx_left_out[3]
set_disable_timing cbx_1__0_/chanx_right_out[3]
set_disable_timing cbx_1__0_/chanx_left_out[4]
@@ -400,6 +396,7 @@ set_disable_timing cbx_1__2_/chanx_right_in[3]
set_disable_timing cbx_1__2_/chanx_left_in[4]
set_disable_timing cbx_1__2_/chanx_right_in[4]
set_disable_timing cbx_1__2_/chanx_left_in[5]
+set_disable_timing cbx_1__2_/chanx_right_in[5]
set_disable_timing cbx_1__2_/chanx_left_in[6]
set_disable_timing cbx_1__2_/chanx_right_in[6]
set_disable_timing cbx_1__2_/chanx_left_in[7]
@@ -419,6 +416,7 @@ set_disable_timing cbx_1__2_/chanx_right_out[3]
set_disable_timing cbx_1__2_/chanx_left_out[4]
set_disable_timing cbx_1__2_/chanx_right_out[4]
set_disable_timing cbx_1__2_/chanx_left_out[5]
+set_disable_timing cbx_1__2_/chanx_right_out[5]
set_disable_timing cbx_1__2_/chanx_left_out[6]
set_disable_timing cbx_1__2_/chanx_right_out[6]
set_disable_timing cbx_1__2_/chanx_left_out[7]
@@ -473,11 +471,8 @@ set_disable_timing cbx_1__2_/mux_bottom_ipin_4/in[2]
set_disable_timing cbx_2__0_/chanx_left_in[0]
set_disable_timing cbx_2__0_/chanx_right_in[0]
set_disable_timing cbx_2__0_/chanx_left_in[1]
-set_disable_timing cbx_2__0_/chanx_right_in[1]
-set_disable_timing cbx_2__0_/chanx_left_in[2]
set_disable_timing cbx_2__0_/chanx_right_in[2]
set_disable_timing cbx_2__0_/chanx_left_in[3]
-set_disable_timing cbx_2__0_/chanx_right_in[3]
set_disable_timing cbx_2__0_/chanx_left_in[4]
set_disable_timing cbx_2__0_/chanx_right_in[4]
set_disable_timing cbx_2__0_/chanx_left_in[5]
@@ -493,11 +488,8 @@ set_disable_timing cbx_2__0_/chanx_right_in[9]
set_disable_timing cbx_2__0_/chanx_left_out[0]
set_disable_timing cbx_2__0_/chanx_right_out[0]
set_disable_timing cbx_2__0_/chanx_left_out[1]
-set_disable_timing cbx_2__0_/chanx_right_out[1]
-set_disable_timing cbx_2__0_/chanx_left_out[2]
set_disable_timing cbx_2__0_/chanx_right_out[2]
set_disable_timing cbx_2__0_/chanx_left_out[3]
-set_disable_timing cbx_2__0_/chanx_right_out[3]
set_disable_timing cbx_2__0_/chanx_left_out[4]
set_disable_timing cbx_2__0_/chanx_right_out[4]
set_disable_timing cbx_2__0_/chanx_left_out[5]
@@ -511,14 +503,11 @@ set_disable_timing cbx_2__0_/chanx_right_out[8]
set_disable_timing cbx_2__0_/chanx_left_out[9]
set_disable_timing cbx_2__0_/chanx_right_out[9]
set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0]
-set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_[0]
-set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_[0]
set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_[0]
set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_[0]
set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_[0]
set_disable_timing cbx_2__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cbx_2__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0]
-set_disable_timing cbx_2__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0]
set_disable_timing cbx_2__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0]
set_disable_timing cbx_2__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0]
set_disable_timing cbx_2__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0]
@@ -531,10 +520,8 @@ set_disable_timing cbx_2__0_/mux_top_ipin_4/in[0]
set_disable_timing cbx_2__0_/mux_bottom_ipin_1/in[1]
set_disable_timing cbx_2__0_/mux_top_ipin_0/in[1]
set_disable_timing cbx_2__0_/mux_top_ipin_5/in[1]
-set_disable_timing cbx_2__0_/mux_bottom_ipin_1/in[0]
set_disable_timing cbx_2__0_/mux_top_ipin_0/in[0]
set_disable_timing cbx_2__0_/mux_top_ipin_5/in[0]
-set_disable_timing cbx_2__0_/mux_bottom_ipin_2/in[1]
set_disable_timing cbx_2__0_/mux_top_ipin_1/in[1]
set_disable_timing cbx_2__0_/mux_top_ipin_6/in[1]
set_disable_timing cbx_2__0_/mux_bottom_ipin_2/in[0]
@@ -544,7 +531,6 @@ set_disable_timing cbx_2__0_/mux_bottom_ipin_3/in[1]
set_disable_timing cbx_2__0_/mux_top_ipin_2/in[1]
set_disable_timing cbx_2__0_/mux_top_ipin_7/in[1]
set_disable_timing cbx_2__0_/mux_bottom_ipin_3/in[0]
-set_disable_timing cbx_2__0_/mux_top_ipin_2/in[0]
set_disable_timing cbx_2__0_/mux_top_ipin_7/in[0]
set_disable_timing cbx_2__0_/mux_bottom_ipin_4/in[1]
set_disable_timing cbx_2__0_/mux_top_ipin_3/in[1]
@@ -578,6 +564,8 @@ set_disable_timing cbx_2__1_/chanx_right_in[1]
set_disable_timing cbx_2__1_/chanx_left_in[2]
set_disable_timing cbx_2__1_/chanx_right_in[2]
set_disable_timing cbx_2__1_/chanx_left_in[3]
+set_disable_timing cbx_2__1_/chanx_right_in[3]
+set_disable_timing cbx_2__1_/chanx_left_in[4]
set_disable_timing cbx_2__1_/chanx_right_in[4]
set_disable_timing cbx_2__1_/chanx_left_in[5]
set_disable_timing cbx_2__1_/chanx_right_in[5]
@@ -596,6 +584,8 @@ set_disable_timing cbx_2__1_/chanx_right_out[1]
set_disable_timing cbx_2__1_/chanx_left_out[2]
set_disable_timing cbx_2__1_/chanx_right_out[2]
set_disable_timing cbx_2__1_/chanx_left_out[3]
+set_disable_timing cbx_2__1_/chanx_right_out[3]
+set_disable_timing cbx_2__1_/chanx_left_out[4]
set_disable_timing cbx_2__1_/chanx_right_out[4]
set_disable_timing cbx_2__1_/chanx_left_out[5]
set_disable_timing cbx_2__1_/chanx_right_out[5]
@@ -611,6 +601,7 @@ set_disable_timing cbx_2__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6
set_disable_timing cbx_2__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_[0]
set_disable_timing cbx_2__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_[0]
set_disable_timing cbx_2__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_[0]
+set_disable_timing cbx_2__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_[0]
set_disable_timing cbx_2__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_[0]
set_disable_timing cbx_2__1_/mux_bottom_ipin_0/in[1]
set_disable_timing cbx_2__1_/mux_bottom_ipin_0/in[0]
@@ -620,6 +611,7 @@ set_disable_timing cbx_2__1_/mux_bottom_ipin_2/in[1]
set_disable_timing cbx_2__1_/mux_bottom_ipin_2/in[0]
set_disable_timing cbx_2__1_/mux_bottom_ipin_3/in[1]
set_disable_timing cbx_2__1_/mux_bottom_ipin_3/in[0]
+set_disable_timing cbx_2__1_/mux_bottom_ipin_4/in[1]
set_disable_timing cbx_2__1_/mux_bottom_ipin_4/in[0]
set_disable_timing cbx_2__1_/mux_bottom_ipin_5/in[1]
set_disable_timing cbx_2__1_/mux_bottom_ipin_5/in[0]
@@ -634,12 +626,15 @@ set_disable_timing cbx_2__2_/chanx_left_in[2]
set_disable_timing cbx_2__2_/chanx_right_in[2]
set_disable_timing cbx_2__2_/chanx_left_in[3]
set_disable_timing cbx_2__2_/chanx_right_in[3]
+set_disable_timing cbx_2__2_/chanx_left_in[4]
+set_disable_timing cbx_2__2_/chanx_right_in[4]
set_disable_timing cbx_2__2_/chanx_left_in[5]
set_disable_timing cbx_2__2_/chanx_right_in[5]
set_disable_timing cbx_2__2_/chanx_left_in[6]
set_disable_timing cbx_2__2_/chanx_right_in[6]
set_disable_timing cbx_2__2_/chanx_left_in[7]
set_disable_timing cbx_2__2_/chanx_right_in[7]
+set_disable_timing cbx_2__2_/chanx_left_in[8]
set_disable_timing cbx_2__2_/chanx_right_in[8]
set_disable_timing cbx_2__2_/chanx_left_in[9]
set_disable_timing cbx_2__2_/chanx_right_in[9]
@@ -651,18 +646,22 @@ set_disable_timing cbx_2__2_/chanx_left_out[2]
set_disable_timing cbx_2__2_/chanx_right_out[2]
set_disable_timing cbx_2__2_/chanx_left_out[3]
set_disable_timing cbx_2__2_/chanx_right_out[3]
+set_disable_timing cbx_2__2_/chanx_left_out[4]
+set_disable_timing cbx_2__2_/chanx_right_out[4]
set_disable_timing cbx_2__2_/chanx_left_out[5]
set_disable_timing cbx_2__2_/chanx_right_out[5]
set_disable_timing cbx_2__2_/chanx_left_out[6]
set_disable_timing cbx_2__2_/chanx_right_out[6]
set_disable_timing cbx_2__2_/chanx_left_out[7]
set_disable_timing cbx_2__2_/chanx_right_out[7]
+set_disable_timing cbx_2__2_/chanx_left_out[8]
set_disable_timing cbx_2__2_/chanx_right_out[8]
set_disable_timing cbx_2__2_/chanx_left_out[9]
set_disable_timing cbx_2__2_/chanx_right_out[9]
set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0]
+set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0]
set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0]
set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0]
@@ -695,6 +694,7 @@ set_disable_timing cbx_2__2_/mux_bottom_ipin_2/in[3]
set_disable_timing cbx_2__2_/mux_bottom_ipin_7/in[3]
set_disable_timing cbx_2__2_/mux_bottom_ipin_2/in[2]
set_disable_timing cbx_2__2_/mux_bottom_ipin_7/in[2]
+set_disable_timing cbx_2__2_/mux_bottom_ipin_3/in[3]
set_disable_timing cbx_2__2_/mux_bottom_ipin_3/in[2]
set_disable_timing cbx_2__2_/mux_bottom_ipin_4/in[3]
set_disable_timing cbx_2__2_/mux_bottom_ipin_4/in[2]
@@ -702,7 +702,6 @@ set_disable_timing cbx_2__2_/mux_bottom_ipin_4/in[2]
# Disable timing for Connection block cby_0__1_
##################################################
set_disable_timing cby_0__1_/chany_bottom_in[0]
-set_disable_timing cby_0__1_/chany_top_in[0]
set_disable_timing cby_0__1_/chany_bottom_in[1]
set_disable_timing cby_0__1_/chany_top_in[1]
set_disable_timing cby_0__1_/chany_bottom_in[2]
@@ -722,7 +721,6 @@ set_disable_timing cby_0__1_/chany_top_in[8]
set_disable_timing cby_0__1_/chany_bottom_in[9]
set_disable_timing cby_0__1_/chany_top_in[9]
set_disable_timing cby_0__1_/chany_bottom_out[0]
-set_disable_timing cby_0__1_/chany_top_out[0]
set_disable_timing cby_0__1_/chany_bottom_out[1]
set_disable_timing cby_0__1_/chany_top_out[1]
set_disable_timing cby_0__1_/chany_bottom_out[2]
@@ -962,6 +960,7 @@ set_disable_timing cby_1__2_/chany_top_in[1]
set_disable_timing cby_1__2_/chany_bottom_in[2]
set_disable_timing cby_1__2_/chany_top_in[2]
set_disable_timing cby_1__2_/chany_bottom_in[3]
+set_disable_timing cby_1__2_/chany_top_in[3]
set_disable_timing cby_1__2_/chany_bottom_in[4]
set_disable_timing cby_1__2_/chany_top_in[4]
set_disable_timing cby_1__2_/chany_bottom_in[5]
@@ -970,6 +969,7 @@ set_disable_timing cby_1__2_/chany_bottom_in[6]
set_disable_timing cby_1__2_/chany_top_in[6]
set_disable_timing cby_1__2_/chany_bottom_in[7]
set_disable_timing cby_1__2_/chany_top_in[7]
+set_disable_timing cby_1__2_/chany_bottom_in[8]
set_disable_timing cby_1__2_/chany_top_in[8]
set_disable_timing cby_1__2_/chany_bottom_in[9]
set_disable_timing cby_1__2_/chany_top_in[9]
@@ -980,6 +980,7 @@ set_disable_timing cby_1__2_/chany_top_out[1]
set_disable_timing cby_1__2_/chany_bottom_out[2]
set_disable_timing cby_1__2_/chany_top_out[2]
set_disable_timing cby_1__2_/chany_bottom_out[3]
+set_disable_timing cby_1__2_/chany_top_out[3]
set_disable_timing cby_1__2_/chany_bottom_out[4]
set_disable_timing cby_1__2_/chany_top_out[4]
set_disable_timing cby_1__2_/chany_bottom_out[5]
@@ -988,6 +989,7 @@ set_disable_timing cby_1__2_/chany_bottom_out[6]
set_disable_timing cby_1__2_/chany_top_out[6]
set_disable_timing cby_1__2_/chany_bottom_out[7]
set_disable_timing cby_1__2_/chany_top_out[7]
+set_disable_timing cby_1__2_/chany_bottom_out[8]
set_disable_timing cby_1__2_/chany_top_out[8]
set_disable_timing cby_1__2_/chany_bottom_out[9]
set_disable_timing cby_1__2_/chany_top_out[9]
@@ -1149,6 +1151,7 @@ set_disable_timing cby_2__2_/chany_top_in[1]
set_disable_timing cby_2__2_/chany_bottom_in[2]
set_disable_timing cby_2__2_/chany_top_in[2]
set_disable_timing cby_2__2_/chany_bottom_in[3]
+set_disable_timing cby_2__2_/chany_top_in[3]
set_disable_timing cby_2__2_/chany_bottom_in[4]
set_disable_timing cby_2__2_/chany_top_in[4]
set_disable_timing cby_2__2_/chany_bottom_in[5]
@@ -1168,6 +1171,7 @@ set_disable_timing cby_2__2_/chany_top_out[1]
set_disable_timing cby_2__2_/chany_bottom_out[2]
set_disable_timing cby_2__2_/chany_top_out[2]
set_disable_timing cby_2__2_/chany_bottom_out[3]
+set_disable_timing cby_2__2_/chany_top_out[3]
set_disable_timing cby_2__2_/chany_bottom_out[4]
set_disable_timing cby_2__2_/chany_top_out[4]
set_disable_timing cby_2__2_/chany_bottom_out[5]
@@ -1188,6 +1192,7 @@ set_disable_timing cby_2__2_/right_grid_left_width_0_height_0_subtile_4__pin_out
set_disable_timing cby_2__2_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cby_2__2_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cby_2__2_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0]
+set_disable_timing cby_2__2_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0]
set_disable_timing cby_2__2_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0]
set_disable_timing cby_2__2_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0]
set_disable_timing cby_2__2_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0]
@@ -1215,6 +1220,7 @@ set_disable_timing cby_2__2_/mux_left_ipin_3/in[1]
set_disable_timing cby_2__2_/mux_right_ipin_0/in[1]
set_disable_timing cby_2__2_/mux_right_ipin_5/in[1]
set_disable_timing cby_2__2_/mux_left_ipin_3/in[0]
+set_disable_timing cby_2__2_/mux_right_ipin_0/in[0]
set_disable_timing cby_2__2_/mux_right_ipin_5/in[0]
set_disable_timing cby_2__2_/mux_left_ipin_4/in[1]
set_disable_timing cby_2__2_/mux_right_ipin_1/in[1]
@@ -1252,7 +1258,6 @@ set_disable_timing cby_2__2_/mux_right_ipin_1/in[2]
# Disable timing for Switch block sb_0__0_
##################################################
set_disable_timing sb_0__0_/chany_top_out[0]
-set_disable_timing sb_0__0_/chany_top_in[0]
set_disable_timing sb_0__0_/chany_top_out[1]
set_disable_timing sb_0__0_/chany_top_in[1]
set_disable_timing sb_0__0_/chany_top_out[2]
@@ -1273,10 +1278,8 @@ set_disable_timing sb_0__0_/chany_top_out[9]
set_disable_timing sb_0__0_/chany_top_in[9]
set_disable_timing sb_0__0_/chanx_right_out[0]
set_disable_timing sb_0__0_/chanx_right_in[0]
-set_disable_timing sb_0__0_/chanx_right_out[1]
set_disable_timing sb_0__0_/chanx_right_in[1]
set_disable_timing sb_0__0_/chanx_right_out[2]
-set_disable_timing sb_0__0_/chanx_right_in[2]
set_disable_timing sb_0__0_/chanx_right_out[3]
set_disable_timing sb_0__0_/chanx_right_in[3]
set_disable_timing sb_0__0_/chanx_right_out[4]
@@ -1291,7 +1294,6 @@ set_disable_timing sb_0__0_/chanx_right_out[8]
set_disable_timing sb_0__0_/chanx_right_in[8]
set_disable_timing sb_0__0_/chanx_right_out[9]
set_disable_timing sb_0__0_/chanx_right_in[9]
-set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
@@ -1331,7 +1333,6 @@ set_disable_timing sb_0__0_/mux_right_track_16/in[1]
set_disable_timing sb_0__0_/mux_right_track_18/in[1]
set_disable_timing sb_0__0_/mux_right_track_0/in[2]
set_disable_timing sb_0__0_/mux_right_track_2/in[2]
-set_disable_timing sb_0__0_/mux_right_track_2/in[0]
set_disable_timing sb_0__0_/mux_right_track_4/in[0]
set_disable_timing sb_0__0_/mux_right_track_6/in[0]
set_disable_timing sb_0__0_/mux_right_track_8/in[0]
@@ -1393,7 +1394,6 @@ set_disable_timing sb_0__1_/chanx_right_in[8]
set_disable_timing sb_0__1_/chanx_right_out[9]
set_disable_timing sb_0__1_/chanx_right_in[9]
set_disable_timing sb_0__1_/chany_bottom_in[0]
-set_disable_timing sb_0__1_/chany_bottom_out[0]
set_disable_timing sb_0__1_/chany_bottom_in[1]
set_disable_timing sb_0__1_/chany_bottom_out[1]
set_disable_timing sb_0__1_/chany_bottom_in[2]
@@ -1424,7 +1424,6 @@ set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pi
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_[0]
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_[0]
set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_[0]
-set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
@@ -1444,7 +1443,6 @@ set_disable_timing sb_0__1_/mux_right_track_0/in[1]
set_disable_timing sb_0__1_/mux_right_track_2/in[2]
set_disable_timing sb_0__1_/mux_right_track_4/in[2]
set_disable_timing sb_0__1_/mux_right_track_6/in[2]
-set_disable_timing sb_0__1_/mux_bottom_track_1/in[6]
set_disable_timing sb_0__1_/mux_bottom_track_9/in[6]
set_disable_timing sb_0__1_/mux_bottom_track_17/in[5]
set_disable_timing sb_0__1_/mux_bottom_track_1/in[7]
@@ -1518,6 +1516,7 @@ set_disable_timing sb_0__2_/chanx_right_in[3]
set_disable_timing sb_0__2_/chanx_right_out[4]
set_disable_timing sb_0__2_/chanx_right_in[4]
set_disable_timing sb_0__2_/chanx_right_out[5]
+set_disable_timing sb_0__2_/chanx_right_in[5]
set_disable_timing sb_0__2_/chanx_right_out[6]
set_disable_timing sb_0__2_/chanx_right_in[6]
set_disable_timing sb_0__2_/chanx_right_out[7]
@@ -1620,11 +1619,8 @@ set_disable_timing sb_1__0_/chany_top_in[9]
set_disable_timing sb_1__0_/chanx_right_out[0]
set_disable_timing sb_1__0_/chanx_right_in[0]
set_disable_timing sb_1__0_/chanx_right_out[1]
-set_disable_timing sb_1__0_/chanx_right_in[1]
-set_disable_timing sb_1__0_/chanx_right_out[2]
set_disable_timing sb_1__0_/chanx_right_in[2]
set_disable_timing sb_1__0_/chanx_right_out[3]
-set_disable_timing sb_1__0_/chanx_right_in[3]
set_disable_timing sb_1__0_/chanx_right_out[4]
set_disable_timing sb_1__0_/chanx_right_in[4]
set_disable_timing sb_1__0_/chanx_right_out[5]
@@ -1639,10 +1635,8 @@ set_disable_timing sb_1__0_/chanx_right_out[9]
set_disable_timing sb_1__0_/chanx_right_in[9]
set_disable_timing sb_1__0_/chanx_left_in[0]
set_disable_timing sb_1__0_/chanx_left_out[0]
-set_disable_timing sb_1__0_/chanx_left_in[1]
set_disable_timing sb_1__0_/chanx_left_out[1]
set_disable_timing sb_1__0_/chanx_left_in[2]
-set_disable_timing sb_1__0_/chanx_left_out[2]
set_disable_timing sb_1__0_/chanx_left_in[3]
set_disable_timing sb_1__0_/chanx_left_out[3]
set_disable_timing sb_1__0_/chanx_left_in[4]
@@ -1664,7 +1658,6 @@ set_disable_timing sb_1__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_
set_disable_timing sb_1__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_[0]
set_disable_timing sb_1__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_[0]
set_disable_timing sb_1__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_[0]
-set_disable_timing sb_1__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_[0]
set_disable_timing sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0]
@@ -1672,7 +1665,6 @@ set_disable_timing sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pi
set_disable_timing sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0]
-set_disable_timing sb_1__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_[0]
set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_[0]
set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_[0]
@@ -1776,6 +1768,7 @@ set_disable_timing sb_1__1_/chany_top_in[1]
set_disable_timing sb_1__1_/chany_top_out[2]
set_disable_timing sb_1__1_/chany_top_in[2]
set_disable_timing sb_1__1_/chany_top_out[3]
+set_disable_timing sb_1__1_/chany_top_in[3]
set_disable_timing sb_1__1_/chany_top_out[4]
set_disable_timing sb_1__1_/chany_top_in[4]
set_disable_timing sb_1__1_/chany_top_out[5]
@@ -1784,6 +1777,7 @@ set_disable_timing sb_1__1_/chany_top_out[6]
set_disable_timing sb_1__1_/chany_top_in[6]
set_disable_timing sb_1__1_/chany_top_out[7]
set_disable_timing sb_1__1_/chany_top_in[7]
+set_disable_timing sb_1__1_/chany_top_out[8]
set_disable_timing sb_1__1_/chany_top_in[8]
set_disable_timing sb_1__1_/chany_top_out[9]
set_disable_timing sb_1__1_/chany_top_in[9]
@@ -1794,6 +1788,8 @@ set_disable_timing sb_1__1_/chanx_right_in[1]
set_disable_timing sb_1__1_/chanx_right_out[2]
set_disable_timing sb_1__1_/chanx_right_in[2]
set_disable_timing sb_1__1_/chanx_right_out[3]
+set_disable_timing sb_1__1_/chanx_right_in[3]
+set_disable_timing sb_1__1_/chanx_right_out[4]
set_disable_timing sb_1__1_/chanx_right_in[4]
set_disable_timing sb_1__1_/chanx_right_out[5]
set_disable_timing sb_1__1_/chanx_right_in[5]
@@ -1852,6 +1848,7 @@ set_disable_timing sb_1__1_/top_left_grid_right_width_0_height_0_subtile_0__pin_
set_disable_timing sb_1__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_[0]
set_disable_timing sb_1__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_[0]
set_disable_timing sb_1__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_[0]
+set_disable_timing sb_1__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_[0]
set_disable_timing sb_1__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_[0]
set_disable_timing sb_1__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_[0]
set_disable_timing sb_1__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_[0]
@@ -1885,6 +1882,7 @@ set_disable_timing sb_1__1_/mux_left_track_9/in[0]
set_disable_timing sb_1__1_/mux_right_track_16/in[0]
set_disable_timing sb_1__1_/mux_bottom_track_17/in[0]
set_disable_timing sb_1__1_/mux_left_track_17/in[0]
+set_disable_timing sb_1__1_/mux_right_track_8/in[1]
set_disable_timing sb_1__1_/mux_left_track_1/in[1]
set_disable_timing sb_1__1_/mux_right_track_0/in[1]
set_disable_timing sb_1__1_/mux_bottom_track_1/in[1]
@@ -1911,6 +1909,7 @@ set_disable_timing sb_1__1_/mux_left_track_9/in[3]
set_disable_timing sb_1__1_/mux_top_track_16/in[1]
set_disable_timing sb_1__1_/mux_bottom_track_17/in[2]
set_disable_timing sb_1__1_/mux_left_track_17/in[3]
+set_disable_timing sb_1__1_/mux_top_track_16/in[2]
set_disable_timing sb_1__1_/mux_bottom_track_9/in[3]
set_disable_timing sb_1__1_/mux_top_track_0/in[3]
set_disable_timing sb_1__1_/mux_bottom_track_1/in[4]
@@ -1993,12 +1992,15 @@ set_disable_timing sb_1__2_/chanx_right_out[2]
set_disable_timing sb_1__2_/chanx_right_in[2]
set_disable_timing sb_1__2_/chanx_right_out[3]
set_disable_timing sb_1__2_/chanx_right_in[3]
+set_disable_timing sb_1__2_/chanx_right_out[4]
+set_disable_timing sb_1__2_/chanx_right_in[4]
set_disable_timing sb_1__2_/chanx_right_out[5]
set_disable_timing sb_1__2_/chanx_right_in[5]
set_disable_timing sb_1__2_/chanx_right_out[6]
set_disable_timing sb_1__2_/chanx_right_in[6]
set_disable_timing sb_1__2_/chanx_right_out[7]
set_disable_timing sb_1__2_/chanx_right_in[7]
+set_disable_timing sb_1__2_/chanx_right_out[8]
set_disable_timing sb_1__2_/chanx_right_in[8]
set_disable_timing sb_1__2_/chanx_right_out[9]
set_disable_timing sb_1__2_/chanx_right_in[9]
@@ -2009,6 +2011,7 @@ set_disable_timing sb_1__2_/chany_bottom_out[1]
set_disable_timing sb_1__2_/chany_bottom_in[2]
set_disable_timing sb_1__2_/chany_bottom_out[2]
set_disable_timing sb_1__2_/chany_bottom_in[3]
+set_disable_timing sb_1__2_/chany_bottom_out[3]
set_disable_timing sb_1__2_/chany_bottom_in[4]
set_disable_timing sb_1__2_/chany_bottom_out[4]
set_disable_timing sb_1__2_/chany_bottom_in[5]
@@ -2017,6 +2020,7 @@ set_disable_timing sb_1__2_/chany_bottom_in[6]
set_disable_timing sb_1__2_/chany_bottom_out[6]
set_disable_timing sb_1__2_/chany_bottom_in[7]
set_disable_timing sb_1__2_/chany_bottom_out[7]
+set_disable_timing sb_1__2_/chany_bottom_in[8]
set_disable_timing sb_1__2_/chany_bottom_out[8]
set_disable_timing sb_1__2_/chany_bottom_in[9]
set_disable_timing sb_1__2_/chany_bottom_out[9]
@@ -2031,6 +2035,7 @@ set_disable_timing sb_1__2_/chanx_left_out[3]
set_disable_timing sb_1__2_/chanx_left_in[4]
set_disable_timing sb_1__2_/chanx_left_out[4]
set_disable_timing sb_1__2_/chanx_left_in[5]
+set_disable_timing sb_1__2_/chanx_left_out[5]
set_disable_timing sb_1__2_/chanx_left_in[6]
set_disable_timing sb_1__2_/chanx_left_out[6]
set_disable_timing sb_1__2_/chanx_left_in[7]
@@ -2040,8 +2045,10 @@ set_disable_timing sb_1__2_/chanx_left_out[8]
set_disable_timing sb_1__2_/chanx_left_in[9]
set_disable_timing sb_1__2_/chanx_left_out[9]
set_disable_timing sb_1__2_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
+set_disable_timing sb_1__2_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_1__2_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_1__2_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0]
+set_disable_timing sb_1__2_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_1__2_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__2_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_1__2_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0]
@@ -2058,6 +2065,7 @@ set_disable_timing sb_1__2_/left_top_grid_bottom_width_0_height_0_subtile_5__pin
set_disable_timing sb_1__2_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_1__2_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__2_/mux_right_track_0/in[0]
+set_disable_timing sb_1__2_/mux_right_track_8/in[0]
set_disable_timing sb_1__2_/mux_right_track_16/in[0]
set_disable_timing sb_1__2_/mux_right_track_0/in[1]
set_disable_timing sb_1__2_/mux_right_track_8/in[1]
@@ -2082,6 +2090,7 @@ set_disable_timing sb_1__2_/mux_bottom_track_3/in[0]
set_disable_timing sb_1__2_/mux_left_track_9/in[0]
set_disable_timing sb_1__2_/mux_bottom_track_5/in[0]
set_disable_timing sb_1__2_/mux_left_track_17/in[0]
+set_disable_timing sb_1__2_/mux_bottom_track_7/in[0]
set_disable_timing sb_1__2_/mux_left_track_1/in[1]
set_disable_timing sb_1__2_/mux_bottom_track_9/in[0]
set_disable_timing sb_1__2_/mux_left_track_9/in[1]
@@ -2106,6 +2115,7 @@ set_disable_timing sb_1__2_/mux_right_track_8/in[5]
set_disable_timing sb_1__2_/mux_left_track_9/in[4]
set_disable_timing sb_1__2_/mux_right_track_0/in[5]
set_disable_timing sb_1__2_/mux_left_track_17/in[4]
+set_disable_timing sb_1__2_/mux_right_track_16/in[4]
set_disable_timing sb_1__2_/mux_left_track_1/in[5]
set_disable_timing sb_1__2_/mux_right_track_8/in[6]
set_disable_timing sb_1__2_/mux_left_track_9/in[5]
@@ -2151,11 +2161,8 @@ set_disable_timing sb_2__0_/chany_top_in[9]
set_disable_timing sb_2__0_/chanx_left_in[0]
set_disable_timing sb_2__0_/chanx_left_out[0]
set_disable_timing sb_2__0_/chanx_left_in[1]
-set_disable_timing sb_2__0_/chanx_left_out[1]
-set_disable_timing sb_2__0_/chanx_left_in[2]
set_disable_timing sb_2__0_/chanx_left_out[2]
set_disable_timing sb_2__0_/chanx_left_in[3]
-set_disable_timing sb_2__0_/chanx_left_out[3]
set_disable_timing sb_2__0_/chanx_left_in[4]
set_disable_timing sb_2__0_/chanx_left_out[4]
set_disable_timing sb_2__0_/chanx_left_in[5]
@@ -2183,7 +2190,6 @@ set_disable_timing sb_2__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_
set_disable_timing sb_2__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_[0]
set_disable_timing sb_2__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_[0]
set_disable_timing sb_2__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_[0]
-set_disable_timing sb_2__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_[0]
set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0]
@@ -2191,7 +2197,6 @@ set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin
set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0]
-set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_2__0_/mux_top_track_0/in[0]
set_disable_timing sb_2__0_/mux_top_track_2/in[0]
set_disable_timing sb_2__0_/mux_top_track_4/in[0]
@@ -2207,7 +2212,6 @@ set_disable_timing sb_2__0_/mux_top_track_2/in[1]
set_disable_timing sb_2__0_/mux_left_track_1/in[1]
set_disable_timing sb_2__0_/mux_left_track_3/in[1]
set_disable_timing sb_2__0_/mux_left_track_5/in[1]
-set_disable_timing sb_2__0_/mux_left_track_7/in[1]
set_disable_timing sb_2__0_/mux_left_track_9/in[1]
set_disable_timing sb_2__0_/mux_left_track_11/in[1]
set_disable_timing sb_2__0_/mux_left_track_13/in[1]
@@ -2215,7 +2219,6 @@ set_disable_timing sb_2__0_/mux_left_track_15/in[1]
set_disable_timing sb_2__0_/mux_left_track_17/in[1]
set_disable_timing sb_2__0_/mux_left_track_19/in[1]
set_disable_timing sb_2__0_/mux_left_track_1/in[2]
-set_disable_timing sb_2__0_/mux_left_track_3/in[2]
set_disable_timing sb_2__0_/mux_left_track_1/in[0]
set_disable_timing sb_2__0_/mux_left_track_19/in[0]
set_disable_timing sb_2__0_/mux_left_track_17/in[0]
@@ -2246,6 +2249,7 @@ set_disable_timing sb_2__1_/chany_top_in[1]
set_disable_timing sb_2__1_/chany_top_out[2]
set_disable_timing sb_2__1_/chany_top_in[2]
set_disable_timing sb_2__1_/chany_top_out[3]
+set_disable_timing sb_2__1_/chany_top_in[3]
set_disable_timing sb_2__1_/chany_top_out[4]
set_disable_timing sb_2__1_/chany_top_in[4]
set_disable_timing sb_2__1_/chany_top_out[5]
@@ -2285,6 +2289,8 @@ set_disable_timing sb_2__1_/chanx_left_out[1]
set_disable_timing sb_2__1_/chanx_left_in[2]
set_disable_timing sb_2__1_/chanx_left_out[2]
set_disable_timing sb_2__1_/chanx_left_in[3]
+set_disable_timing sb_2__1_/chanx_left_out[3]
+set_disable_timing sb_2__1_/chanx_left_in[4]
set_disable_timing sb_2__1_/chanx_left_out[4]
set_disable_timing sb_2__1_/chanx_left_in[5]
set_disable_timing sb_2__1_/chanx_left_out[5]
@@ -2323,6 +2329,7 @@ set_disable_timing sb_2__1_/bottom_left_grid_right_width_0_height_0_subtile_0__p
set_disable_timing sb_2__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_[0]
set_disable_timing sb_2__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_[0]
set_disable_timing sb_2__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_[0]
+set_disable_timing sb_2__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_[0]
set_disable_timing sb_2__1_/mux_top_track_0/in[0]
set_disable_timing sb_2__1_/mux_top_track_8/in[0]
set_disable_timing sb_2__1_/mux_top_track_16/in[0]
@@ -2350,6 +2357,7 @@ set_disable_timing sb_2__1_/mux_bottom_track_17/in[5]
set_disable_timing sb_2__1_/mux_left_track_1/in[3]
set_disable_timing sb_2__1_/mux_left_track_3/in[3]
set_disable_timing sb_2__1_/mux_left_track_5/in[3]
+set_disable_timing sb_2__1_/mux_left_track_7/in[3]
set_disable_timing sb_2__1_/mux_bottom_track_1/in[0]
set_disable_timing sb_2__1_/mux_left_track_1/in[0]
set_disable_timing sb_2__1_/mux_bottom_track_9/in[0]
@@ -2412,6 +2420,7 @@ set_disable_timing sb_2__2_/chany_bottom_out[1]
set_disable_timing sb_2__2_/chany_bottom_in[2]
set_disable_timing sb_2__2_/chany_bottom_out[2]
set_disable_timing sb_2__2_/chany_bottom_in[3]
+set_disable_timing sb_2__2_/chany_bottom_out[3]
set_disable_timing sb_2__2_/chany_bottom_in[4]
set_disable_timing sb_2__2_/chany_bottom_out[4]
set_disable_timing sb_2__2_/chany_bottom_in[5]
@@ -2432,12 +2441,15 @@ set_disable_timing sb_2__2_/chanx_left_in[2]
set_disable_timing sb_2__2_/chanx_left_out[2]
set_disable_timing sb_2__2_/chanx_left_in[3]
set_disable_timing sb_2__2_/chanx_left_out[3]
+set_disable_timing sb_2__2_/chanx_left_in[4]
+set_disable_timing sb_2__2_/chanx_left_out[4]
set_disable_timing sb_2__2_/chanx_left_in[5]
set_disable_timing sb_2__2_/chanx_left_out[5]
set_disable_timing sb_2__2_/chanx_left_in[6]
set_disable_timing sb_2__2_/chanx_left_out[6]
set_disable_timing sb_2__2_/chanx_left_in[7]
set_disable_timing sb_2__2_/chanx_left_out[7]
+set_disable_timing sb_2__2_/chanx_left_in[8]
set_disable_timing sb_2__2_/chanx_left_out[8]
set_disable_timing sb_2__2_/chanx_left_in[9]
set_disable_timing sb_2__2_/chanx_left_out[9]
@@ -2454,8 +2466,10 @@ set_disable_timing sb_2__2_/bottom_left_grid_right_width_0_height_0_subtile_0__p
set_disable_timing sb_2__2_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_[0]
set_disable_timing sb_2__2_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0]
set_disable_timing sb_2__2_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
+set_disable_timing sb_2__2_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_2__2_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_2__2_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0]
+set_disable_timing sb_2__2_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_2__2_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_2__2_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_2__2_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0]
@@ -2475,6 +2489,7 @@ set_disable_timing sb_2__2_/mux_left_track_1/in[1]
set_disable_timing sb_2__2_/mux_left_track_3/in[1]
set_disable_timing sb_2__2_/mux_left_track_5/in[1]
set_disable_timing sb_2__2_/mux_left_track_7/in[1]
+set_disable_timing sb_2__2_/mux_left_track_9/in[1]
set_disable_timing sb_2__2_/mux_left_track_11/in[1]
set_disable_timing sb_2__2_/mux_left_track_13/in[1]
set_disable_timing sb_2__2_/mux_left_track_15/in[1]
@@ -2490,6 +2505,7 @@ set_disable_timing sb_2__2_/mux_bottom_track_19/in[1]
set_disable_timing sb_2__2_/mux_bottom_track_1/in[2]
set_disable_timing sb_2__2_/mux_bottom_track_3/in[2]
set_disable_timing sb_2__2_/mux_bottom_track_5/in[1]
+set_disable_timing sb_2__2_/mux_bottom_track_7/in[1]
set_disable_timing sb_2__2_/mux_bottom_track_9/in[1]
set_disable_timing sb_2__2_/mux_bottom_track_11/in[1]
set_disable_timing sb_2__2_/mux_bottom_track_13/in[1]
@@ -2743,561 +2759,561 @@ set_disable_timing grid_clb_1__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_
# Disable Timing for grid[2][1]
#######################################
#######################################
-# Disable Timing for unused grid[2][1][0]
-#######################################
-#######################################
-# Disable all the ports for pb_graph_node clb[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/*
-#######################################
-# Disable all the ports for pb_graph_node fle[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/*
-#######################################
-# Disable all the ports for pb_graph_node fabric[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/*
-#######################################
-# Disable all the ports for pb_graph_node frac_logic[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/*
-#######################################
-# Disable all the ports for pb_graph_node frac_lut4[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/*
-#######################################
-# Disable all the ports for pb_graph_node ff[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/*
-#######################################
-# Disable all the ports for pb_graph_node ff[1]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/*
-#######################################
-# Disable all the ports for pb_graph_node adder[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/*
-#######################################
-# Disable all the ports for pb_graph_node fle[1]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/*
-#######################################
-# Disable all the ports for pb_graph_node fabric[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/*
-#######################################
-# Disable all the ports for pb_graph_node frac_logic[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/*
-#######################################
-# Disable all the ports for pb_graph_node frac_lut4[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/*
-#######################################
-# Disable all the ports for pb_graph_node ff[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/*
-#######################################
-# Disable all the ports for pb_graph_node ff[1]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/*
-#######################################
-# Disable all the ports for pb_graph_node adder[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/*
-#######################################
-# Disable all the ports for pb_graph_node fle[2]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/*
-#######################################
-# Disable all the ports for pb_graph_node fabric[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/*
-#######################################
-# Disable all the ports for pb_graph_node frac_logic[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/*
-#######################################
-# Disable all the ports for pb_graph_node frac_lut4[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/*
-#######################################
-# Disable all the ports for pb_graph_node ff[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/*
-#######################################
-# Disable all the ports for pb_graph_node ff[1]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/*
-#######################################
-# Disable all the ports for pb_graph_node adder[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/*
-#######################################
-# Disable all the ports for pb_graph_node fle[3]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/*
-#######################################
-# Disable all the ports for pb_graph_node fabric[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/*
-#######################################
-# Disable all the ports for pb_graph_node frac_logic[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/*
-#######################################
-# Disable all the ports for pb_graph_node frac_lut4[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/*
-#######################################
-# Disable all the ports for pb_graph_node ff[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/*
-#######################################
-# Disable all the ports for pb_graph_node ff[1]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/*
-#######################################
-# Disable all the ports for pb_graph_node adder[0]
-#######################################
-set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/*
-#######################################
-# Disable Timing for grid[2][2]
-#######################################
-#######################################
-# Disable Timing for unused resources in grid[2][2][0]
+# Disable Timing for unused resources in grid[2][1][0]
#######################################
#######################################
# Disable unused pins for pb_graph_node clb[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[4]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[5]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[6]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[7]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[8]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[9]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_I[11]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_O[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_O[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_O[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_O[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_O[4]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_O[5]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_O[6]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/clb_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[4]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[5]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[6]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[9]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[10]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_I[11]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_O[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_O[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_O[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_O[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_O[4]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_O[5]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_O[6]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/clb_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node clb[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[7]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//direct_interc_9_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//direct_interc_16_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//direct_interc_11_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[14]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[15]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//direct_interc_13_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[16]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[17]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//direct_interc_15_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[18]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[19]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0//direct_interc_8_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[7]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//direct_interc_9_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//direct_interc_16_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//direct_interc_11_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[14]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[15]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//direct_interc_13_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[16]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[17]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//direct_interc_15_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[18]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[19]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0//direct_interc_8_/in[0]
#######################################
# Disable unused pins for pb_graph_node fle[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node fle[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_6_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_8_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_6_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_7_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_8_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0]
#######################################
# Disable unused pins for pb_graph_node fabric[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node fabric[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_9_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_6_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_8_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_1/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_0_D_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_1_D_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_9_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_6_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_7_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_8_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_1/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_0_D_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_1_D_0/in[1]
#######################################
# Disable unused pins for pb_graph_node frac_logic[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1]
#######################################
# Disable unused mux_inputs for pb_graph_node frac_logic[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[0]
#######################################
# Disable unused pins for pb_graph_node frac_lut4[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut4_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut4_out[0]
#######################################
# Disable unused pins for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_clk[0]
#######################################
# Disable unused pins for pb_graph_node ff[1]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_clk[0]
#######################################
# Disable unused pins for pb_graph_node adder[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_a[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_b[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_a[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_b[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0]
#######################################
# Disable unused pins for pb_graph_node fle[1]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node fle[1]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_6_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_8_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_6_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_7_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_8_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0]
#######################################
# Disable unused pins for pb_graph_node fabric[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node fabric[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_9_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_6_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_8_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_1/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_0_D_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_1_D_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_9_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_6_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_7_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_8_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_1/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_0_D_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_1_D_0/in[1]
#######################################
# Disable unused pins for pb_graph_node frac_logic[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1]
#######################################
# Disable unused mux_inputs for pb_graph_node frac_logic[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[0]
#######################################
# Disable unused pins for pb_graph_node frac_lut4[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut4_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut4_out[0]
#######################################
# Disable unused pins for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_clk[0]
#######################################
# Disable unused pins for pb_graph_node ff[1]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_clk[0]
#######################################
# Disable unused pins for pb_graph_node adder[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_a[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_b[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_a[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_b[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0]
#######################################
# Disable unused pins for pb_graph_node fle[2]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node fle[2]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_6_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_8_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_6_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_7_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_8_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0]
#######################################
# Disable unused pins for pb_graph_node fabric[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node fabric[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_9_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_6_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_8_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_1/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_0_D_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_1_D_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_9_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_6_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_7_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_8_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_1/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_0_D_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_1_D_0/in[1]
#######################################
# Disable unused pins for pb_graph_node frac_logic[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1]
#######################################
# Disable unused mux_inputs for pb_graph_node frac_logic[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_2_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[0]
#######################################
# Disable unused pins for pb_graph_node frac_lut4[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[2]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut4_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[2]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut4_out[0]
#######################################
# Disable unused pins for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_clk[0]
#######################################
# Disable unused pins for pb_graph_node ff[1]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_clk[0]
#######################################
# Disable unused pins for pb_graph_node adder[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_a[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_b[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_a[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_b[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0]
#######################################
# Disable unused pins for pb_graph_node fle[3]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node fle[3]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_6_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_8_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_0_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_6_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_7_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_8_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_0_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0]
#######################################
# Disable unused pins for pb_graph_node fabric[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_clk[0]
#######################################
# Disable unused mux_inputs for pb_graph_node fabric[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_9_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_6_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_7_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_1/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_0_D_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_1_D_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_9_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_6_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//direct_interc_7_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_fabric_out_1/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_0_D_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0//mux_ff_1_D_0/in[1]
#######################################
# Disable unused pins for pb_graph_node frac_logic[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]
#######################################
# Disable unused mux_inputs for pb_graph_node frac_logic[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_1_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_4_/in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[1]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_1_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//direct_interc_4_/in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[1]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0//mux_frac_logic_out_0/in[0]
#######################################
# Disable unused pins for pb_graph_node frac_lut4[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[3]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut4_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_in[3]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut3_out[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_lut4_out[0]
#######################################
# Disable unused pins for pb_graph_node ff[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_clk[0]
#######################################
# Disable unused pins for pb_graph_node ff[1]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_clk[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_clk[0]
#######################################
# Disable unused pins for pb_graph_node adder[0]
#######################################
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_a[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_b[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cin[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0]
-set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_a[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_b[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cin[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0]
+set_disable_timing grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0]
+#######################################
+# Disable Timing for grid[2][2]
+#######################################
+#######################################
+# Disable Timing for unused grid[2][2][0]
+#######################################
+#######################################
+# Disable all the ports for pb_graph_node clb[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/*
+#######################################
+# Disable all the ports for pb_graph_node fle[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/*
+#######################################
+# Disable all the ports for pb_graph_node fabric[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/*
+#######################################
+# Disable all the ports for pb_graph_node frac_logic[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/*
+#######################################
+# Disable all the ports for pb_graph_node frac_lut4[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/*
+#######################################
+# Disable all the ports for pb_graph_node ff[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/*
+#######################################
+# Disable all the ports for pb_graph_node ff[1]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/*
+#######################################
+# Disable all the ports for pb_graph_node adder[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/*
+#######################################
+# Disable all the ports for pb_graph_node fle[1]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/*
+#######################################
+# Disable all the ports for pb_graph_node fabric[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/*
+#######################################
+# Disable all the ports for pb_graph_node frac_logic[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/*
+#######################################
+# Disable all the ports for pb_graph_node frac_lut4[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/*
+#######################################
+# Disable all the ports for pb_graph_node ff[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/*
+#######################################
+# Disable all the ports for pb_graph_node ff[1]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/*
+#######################################
+# Disable all the ports for pb_graph_node adder[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/*
+#######################################
+# Disable all the ports for pb_graph_node fle[2]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/*
+#######################################
+# Disable all the ports for pb_graph_node fabric[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/*
+#######################################
+# Disable all the ports for pb_graph_node frac_logic[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/*
+#######################################
+# Disable all the ports for pb_graph_node frac_lut4[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/*
+#######################################
+# Disable all the ports for pb_graph_node ff[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/*
+#######################################
+# Disable all the ports for pb_graph_node ff[1]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/*
+#######################################
+# Disable all the ports for pb_graph_node adder[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/*
+#######################################
+# Disable all the ports for pb_graph_node fle[3]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/*
+#######################################
+# Disable all the ports for pb_graph_node fabric[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/*
+#######################################
+# Disable all the ports for pb_graph_node frac_logic[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/*
+#######################################
+# Disable all the ports for pb_graph_node frac_lut4[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/*
+#######################################
+# Disable all the ports for pb_graph_node ff[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/*
+#######################################
+# Disable all the ports for pb_graph_node ff[1]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/*
+#######################################
+# Disable all the ports for pb_graph_node adder[0]
+#######################################
+set_disable_timing grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/*
#######################################
# Disable Timing for grid[1][3]
#######################################
@@ -3404,20 +3420,16 @@ set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__0/*
#######################################
set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused resources in grid[2][3][1]
+# Disable Timing for unused grid[2][3][1]
#######################################
#######################################
-# Disable unused pins for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__1/io_outpad[0]
+set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__1/*
#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node iopad[0]
#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__1//direct_interc_1_/in[0]
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
+set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[2][3][2]
#######################################
@@ -3430,35 +3442,27 @@ set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__2/*
#######################################
set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused resources in grid[2][3][3]
+# Disable Timing for unused grid[2][3][3]
#######################################
#######################################
-# Disable unused pins for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__3/io_inpad[0]
+set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__3/*
#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node iopad[0]
#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__3//direct_interc_0_/in[0]
+set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
-#######################################
-# Disable Timing for unused resources in grid[2][3][4]
+# Disable Timing for unused grid[2][3][4]
#######################################
#######################################
-# Disable unused pins for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__4/io_outpad[0]
+set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__4/*
#######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node iopad[0]
#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__4//direct_interc_1_/in[0]
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
+set_disable_timing grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[2][3][5]
#######################################
@@ -3700,16 +3704,20 @@ set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__1/*
#######################################
set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused grid[2][0][2]
+# Disable Timing for unused resources in grid[2][0][2]
#######################################
#######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__2/*
+set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__2/io_inpad[0]
#######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__2//direct_interc_0_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
#######################################
# Disable Timing for unused grid[2][0][3]
#######################################
@@ -3755,16 +3763,20 @@ set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__6/*
#######################################
set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/*
#######################################
-# Disable Timing for unused grid[2][0][7]
+# Disable Timing for unused resources in grid[2][0][7]
#######################################
#######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__7/*
+set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__7/io_outpad[0]
#######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__7//direct_interc_1_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for grid[1][0]
#######################################
@@ -3860,16 +3872,20 @@ set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_
# Disable Timing for grid[0][1]
#######################################
#######################################
-# Disable Timing for unused grid[0][1][0]
+# Disable Timing for unused resources in grid[0][1][0]
#######################################
#######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/*
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/io_outpad[0]
#######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
-set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0//direct_interc_1_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for unused grid[0][1][1]
#######################################
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v
index bf7a3377b..6f261adc1 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v
@@ -45,14 +45,14 @@ wire [0:0] clk_fm;
// ----- End Connect Global ports of FPGA top module -----
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
-// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
- assign gfpga_pad_GPIO_PAD_fm[12] = a[0];
+// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[39] -----
+ assign gfpga_pad_GPIO_PAD_fm[39] = a[0];
-// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[9] -----
- assign gfpga_pad_GPIO_PAD_fm[9] = b[0];
+// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[48] -----
+ assign gfpga_pad_GPIO_PAD_fm[48] = b[0];
-// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] -----
- assign c[0] = gfpga_pad_GPIO_PAD_fm[11];
+// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[34] -----
+ assign c[0] = gfpga_pad_GPIO_PAD_fm[34];
// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
@@ -64,7 +64,10 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[6] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
+ assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
@@ -86,12 +89,10 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[31] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[32] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[33] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[34] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[42] = 1'b0;
@@ -100,7 +101,6 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[45] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[46] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[47] = 1'b0;
- assign gfpga_pad_GPIO_PAD_fm[48] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[49] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[50] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[51] = 1'b0;
@@ -316,14 +316,14 @@ initial begin
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_outb[0:2] = 3'b110;
- force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
- force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = {17{1'b1}};
+ force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = 17'b00000000110000001;
+ force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = 17'b11111111001111110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:3] = 4'b0001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:3] = 4'b1110;
- force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0001;
- force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1110;
+ force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0010;
+ force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1101;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
@@ -354,10 +354,10 @@ initial begin
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:9] = 10'b1111111110;
- force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000000001;
- force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111111110;
- force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0000000001;
- force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1111111110;
+ force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0001001000;
+ force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1110110111;
+ force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0010001000;
+ force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1101110111;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
@@ -396,14 +396,14 @@ initial begin
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_outb[0:2] = 3'b110;
- force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = 17'b00000000110000001;
- force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = 17'b11111111001111110;
+ force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
+ force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = {17{1'b1}};
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:3] = 4'b0001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:3] = 4'b1110;
- force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0010;
- force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1101;
+ force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0001;
+ force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
@@ -434,10 +434,10 @@ initial begin
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:9] = 10'b1111111110;
- force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b1000010000;
- force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b0111101111;
- force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b1000000100;
- force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b0111111011;
+ force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000000001;
+ force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111111110;
+ force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0000000001;
+ force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
@@ -462,8 +462,8 @@ initial begin
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
- force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b0;
- force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b1;
+ force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
+ force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
@@ -508,8 +508,8 @@ initial begin
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
- force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
- force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
+ force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b0;
+ force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
@@ -586,8 +586,8 @@ initial begin
force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
@@ -624,8 +624,8 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00000001;
- force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:7] = 8'b11111110;
+ force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00100100;
+ force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:7] = 8'b11011011;
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:5] = 6'b010001;
@@ -694,12 +694,12 @@ initial begin
force U0_formal_verification.sb_1__1_.mem_top_track_0.mem_outb[0:7] = 8'b10111110;
force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_outb[0:7] = 8'b11111110;
- force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:7] = 8'b00101000;
- force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:7] = 8'b11010111;
+ force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:7] = 8'b00000001;
+ force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:7] = 8'b01000001;
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:7] = 8'b10111110;
- force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:7] = 8'b01001000;
- force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:7] = 8'b10110111;
+ force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:7] = 8'b00000001;
+ force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:7] = 8'b01000001;
@@ -716,18 +716,18 @@ initial begin
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:7] = 8'b11111110;
- force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:7] = 8'b10001000;
- force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:7] = 8'b01110111;
- force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:5] = 6'b010010;
- force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:5] = 6'b101101;
+ force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:7] = 8'b00000001;
+ force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:7] = 8'b11111110;
+ force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:5] = 6'b010001;
+ force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:5] = 6'b101110;
force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:5] = 6'b000001;
force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:5] = 6'b000001;
force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b0}};
+ force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
+ force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
@@ -762,12 +762,12 @@ initial begin
force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:1] = 2'b10;
+ force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:1] = 2'b01;
+ force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:1] = 2'b10;
force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
@@ -798,8 +798,8 @@ initial begin
force U0_formal_verification.sb_2__1_.mem_left_track_3.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.sb_2__1_.mem_left_track_5.mem_out[0:5] = 6'b000001;
force U0_formal_verification.sb_2__1_.mem_left_track_5.mem_outb[0:5] = 6'b111110;
- force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:5] = 6'b000010;
- force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:5] = 6'b111101;
+ force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:5] = 6'b000001;
+ force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
@@ -812,8 +812,8 @@ initial begin
force U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:1] = 2'b01;
- force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:1] = 2'b10;
+ force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
+ force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
@@ -834,8 +834,8 @@ initial begin
force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = 2'b01;
- force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = 2'b10;
+ force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
+ force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
@@ -900,10 +900,10 @@ initial begin
force U0_formal_verification.cbx_1__2_.mem_bottom_ipin_7.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:1] = {2{1'b0}};
- force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b1}};
+ force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:1] = 2'b01;
+ force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:1] = 2'b10;
+ force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:1] = {2{1'b1}};
+ force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b0}};
@@ -914,8 +914,8 @@ initial begin
force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:5] = 6'b111110;
- force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:5] = 6'b000001;
- force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:5] = 6'b111110;
+ force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:5] = 6'b010100;
+ force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:5] = 6'b101011;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:5] = 6'b000001;
@@ -934,8 +934,8 @@ initial begin
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:1] = {2{1'b1}};
- force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b1}};
- force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:1] = {2{1'b0}};
+ force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b0}};
+ force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:5] = 6'b000001;
@@ -944,8 +944,8 @@ initial begin
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_1.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_2.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_2.mem_outb[0:5] = 6'b111110;
- force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_out[0:5] = 6'b001100;
- force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_outb[0:5] = 6'b110011;
+ force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_out[0:5] = 6'b000001;
+ force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_4.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_4.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_5.mem_out[0:5] = 6'b000001;
@@ -1062,8 +1062,8 @@ initial begin
force U0_formal_verification.cby_2__2_.mem_left_ipin_6.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_left_ipin_7.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cby_2__2_.mem_left_ipin_7.mem_outb[0:5] = 6'b111110;
- force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:5] = 6'b010100;
- force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:5] = 6'b101011;
+ force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:5] = 6'b000001;
+ force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:5] = 6'b000001;
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit
index e712fb015..a665d29db 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit
@@ -407,13 +407,13 @@
0
0
0
+1
+0
0
0
0
-1
0
0
-1
0
1
0
@@ -423,12 +423,12 @@
0
1
0
+1
+0
0
0
0
-1
0
-1
0
0
1
@@ -457,9 +457,10 @@
0
0
0
+1
+0
0
0
-1
0
0
0
@@ -471,12 +472,11 @@
0
0
0
-1
0
0
0
0
-1
+0
1
0
0
@@ -613,10 +613,10 @@
1
0
0
-0
1
0
0
+0
1
0
0
@@ -624,15 +624,15 @@
1
0
0
-1
0
0
0
0
0
0
-1
-1
+0
+0
+0
0
0
0
@@ -773,11 +773,11 @@
0
0
0
+1
+0
0
0
-1
0
-1
0
1
0
@@ -829,8 +829,7 @@
0
0
0
-1
-1
+0
0
0
0
@@ -851,6 +850,7 @@
0
0
0
+0
1
0
0
@@ -927,13 +927,10 @@
0
0
0
-1
-0
-0
-0
0
0
0
+1
0
0
0
@@ -943,7 +940,10 @@
0
0
0
+1
+0
0
+1
0
0
0
@@ -1083,26 +1083,26 @@
1
0
0
-1
-0
-0
0
1
0
0
-0
1
0
0
0
+1
0
0
+1
0
0
0
0
0
0
+1
+1
0
0
0
@@ -1327,17 +1327,11 @@
0
0
0
-1
-0
-0
-0
0
0
1
0
-0
-0
-0
+1
0
1
0
@@ -1345,6 +1339,7 @@
0
0
0
+1
0
0
0
@@ -1356,6 +1351,9 @@
0
0
0
+1
+1
+1
0
0
0
@@ -1371,10 +1369,12 @@
0
0
0
+1
0
0
0
0
+1
0
0
0
@@ -1945,8 +1945,8 @@
0
0
0
-0
-0
+1
+1
0
0
0
@@ -2041,12 +2041,12 @@
0
0
0
-1
-0
0
0
+1
0
0
+1
0
0
0
@@ -2211,8 +2211,8 @@
0
0
0
-1
-1
+0
+0
0
0
1
@@ -2227,20 +2227,20 @@
0
0
0
-0
1
0
0
+0
+1
+0
1
0
0
0
0
-1
0
0
0
-1
1
0
0
@@ -2253,7 +2253,7 @@
1
1
1
-0
+1
1
1
1
@@ -2281,10 +2281,10 @@
0
0
0
+1
+0
0
0
-1
-1
0
0
1
@@ -2311,7 +2311,6 @@
0
0
0
-1
0
0
0
@@ -2333,7 +2332,8 @@
0
0
0
-1
+0
+0
0
0
0
@@ -2362,7 +2362,7 @@
1
1
1
-1
+0
1
1
1
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml
index 2c4fda047..5004ccc7b 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml
@@ -818,19 +818,19 @@
-
+
-
+
-
+
@@ -850,17 +850,17 @@
-
+
-
+
-
+
@@ -918,11 +918,11 @@
-
+
-
+
@@ -936,9 +936,9 @@
-
+
-
+
@@ -946,7 +946,7 @@
-
+
@@ -956,7 +956,7 @@
-
+
@@ -1230,9 +1230,9 @@
-
+
-
+
@@ -1252,7 +1252,7 @@
-
+
@@ -1266,9 +1266,9 @@
-
+
-
+
@@ -1550,15 +1550,15 @@
-
+
-
+
-
+
@@ -1662,9 +1662,9 @@
-
+
-
+
@@ -1694,9 +1694,9 @@
-
+
-
+
@@ -1858,13 +1858,13 @@
-
+
-
+
@@ -1872,25 +1872,25 @@
-
+
-
+
-
+
-
+
@@ -2170,9 +2170,9 @@
-
+
-
+
@@ -2192,7 +2192,7 @@
-
+
@@ -2206,9 +2206,9 @@
-
+
-
+
@@ -2658,15 +2658,15 @@
-
+
-
+
-
+
@@ -2706,11 +2706,11 @@
-
+
-
+
-
+
@@ -2742,7 +2742,7 @@
-
+
@@ -2752,7 +2752,7 @@
-
+
@@ -3894,9 +3894,9 @@
-
+
-
+
@@ -4086,17 +4086,17 @@
-
+
-
+
-
+
@@ -4426,9 +4426,9 @@
-
+
-
+
@@ -4458,9 +4458,9 @@
-
+
-
+
@@ -4470,13 +4470,13 @@
-
+
-
+
@@ -4484,7 +4484,7 @@
-
+
@@ -4510,7 +4510,7 @@
-
+
@@ -4566,13 +4566,13 @@
-
+
-
+
-
+
@@ -4626,7 +4626,7 @@
-
+
@@ -4670,7 +4670,7 @@
-
+
@@ -4728,7 +4728,7 @@
-
+
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
index 4e14bc93e..8e51c806a 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
@@ -2227,15 +2227,15 @@
-
-
+
+
-
+
@@ -2287,14 +2287,19 @@
-
+
+
+
+
+
+
-
+
-
-
+
+
@@ -2641,20 +2646,42 @@
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
-
+
-
+
-
+
@@ -2664,20 +2691,42 @@
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
-
+
-
+
-
+
@@ -3127,15 +3176,15 @@
-
-
+
+
-
+
@@ -3187,19 +3236,14 @@
-
-
-
-
-
-
+
-
+
-
-
+
+
@@ -3546,42 +3590,20 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
+
+
-
+
-
+
@@ -3591,42 +3613,20 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
+
+
-
+
-
+
@@ -3844,7 +3844,7 @@
-
+
@@ -4218,7 +4218,7 @@
-
+
@@ -4702,7 +4702,7 @@
-
+
@@ -4721,7 +4721,7 @@
-
+
@@ -4865,16 +4865,16 @@
-
+
-
+
-
-
-
+
+
+
@@ -5269,22 +5269,22 @@
-
+
-
+
-
+
-
+
-
+
-
+
@@ -5552,7 +5552,7 @@
-
+
@@ -5670,9 +5670,9 @@
-
+
-
+
@@ -5785,7 +5785,7 @@
-
+
@@ -5807,7 +5807,7 @@
-
+
@@ -5843,7 +5843,7 @@
-
+
@@ -5873,7 +5873,7 @@
-
+
@@ -5934,7 +5934,7 @@
-
+
@@ -6063,7 +6063,7 @@
-
+
@@ -6072,17 +6072,17 @@
-
+
-
+
-
+
-
+
-
+
@@ -6097,7 +6097,7 @@
-
+
@@ -6128,7 +6128,7 @@
-
+
@@ -6138,17 +6138,17 @@
-
+
-
+
-
+
-
+
-
+
@@ -6227,7 +6227,7 @@
-
+
@@ -6287,7 +6287,7 @@
-
+
@@ -6416,8 +6416,8 @@
-
-
+
+
@@ -6427,17 +6427,17 @@
-
+
-
-
+
+
-
+
-
+
@@ -6451,20 +6451,20 @@
-
+
-
+
-
+
-
-
+
+
@@ -6541,16 +6541,16 @@
-
+
-
+
-
-
-
+
+
+
@@ -6616,11 +6616,11 @@
-
+
-
+
@@ -6853,7 +6853,7 @@
-
+
@@ -6909,13 +6909,13 @@
-
+
-
+
-
-
+
+
@@ -6945,14 +6945,14 @@
-
+
-
+
-
+
-
+
@@ -7143,7 +7143,7 @@
-
+
@@ -7175,7 +7175,7 @@
-
+
@@ -7263,7 +7263,7 @@
-
+
@@ -7337,18 +7337,18 @@
-
+
-
+
-
+
-
-
+
+
@@ -7471,14 +7471,14 @@
-
+
-
+
-
+
-
+
@@ -7543,7 +7543,7 @@
-
+
@@ -7615,7 +7615,7 @@
-
+
@@ -7669,14 +7669,14 @@
-
+
-
+
-
+
-
+
@@ -7760,7 +7760,7 @@
-
+
@@ -7779,7 +7779,7 @@
-
+
@@ -7850,7 +7850,7 @@
-
+
@@ -7875,7 +7875,7 @@
-
+
@@ -7970,7 +7970,7 @@
-
+
@@ -7995,7 +7995,7 @@
-
+
@@ -8157,7 +8157,7 @@
-
+
@@ -8277,7 +8277,7 @@
-
+
@@ -8367,14 +8367,14 @@
-
+
-
+
-
+
-
+
@@ -8384,15 +8384,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -8403,7 +8403,7 @@
-
+
@@ -8457,7 +8457,7 @@
-
+
@@ -8480,7 +8480,7 @@
-
+
@@ -8505,20 +8505,20 @@
-
+
-
+
-
+
-
+
-
+
-
+
@@ -8577,7 +8577,7 @@
-
+
@@ -8600,7 +8600,7 @@
-
+
@@ -8625,7 +8625,7 @@
-
+
@@ -8705,7 +8705,7 @@
-
+
@@ -8722,15 +8722,15 @@
-
+
-
+
-
-
-
+
+
+
@@ -8834,19 +8834,19 @@
-
+
-
+
-
+
-
-
+
+
-
+
@@ -8856,8 +8856,8 @@
-
-
+
+
@@ -8955,7 +8955,7 @@
-
+
@@ -9075,7 +9075,7 @@
-
+
@@ -9633,8 +9633,8 @@
-
-
+
+
@@ -10141,7 +10141,7 @@
-
+
@@ -10261,20 +10261,20 @@
-
+
-
+
-
+
-
+
-
+
-
+
@@ -10381,7 +10381,7 @@
-
+
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc
index be1715a73..8070cff56 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc
@@ -14,7 +14,7 @@ set_units -time s
##################################################
# Create clock
##################################################
-create_clock -name clk[0] -period 1.11238041e-09 -waveform {0 5.56190205e-10} [get_ports {clk[0]}]
+create_clock -name clk[0] -period 8.970345577e-10 -waveform {0 4.485172789e-10} [get_ports {clk[0]}]
##################################################
# Create programmable clock
##################################################
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/pin_mapping.xml
index 54035bd3a..c107f9429 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/pin_mapping.xml
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/pin_mapping.xml
@@ -3,7 +3,7 @@
-->
-
-
-
+
+
+
diff --git a/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf
index 777613ba3..c706286a5 100644
--- a/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf
+++ b/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf
@@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
# VPR parameters
# # Use a fixed routing channel width to save runtime
-vpr_route_chan_width=60
+vpr_route_chan_width=80
openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
[ARCHITECTURES]
diff --git a/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf
index 0764beeb3..839bd3e09 100644
--- a/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf
@@ -16,10 +16,10 @@ timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-external_fabric_key_file=
+openfpga_vpr_device_layout=2x2
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing
index ff83963de..4834fd012 160000
--- a/vtr-verilog-to-routing
+++ b/vtr-verilog-to-routing
@@ -1 +1 @@
-Subproject commit ff83963de3e4c12f372d4d80fd039305b8344440
+Subproject commit 4834fd012621fe50736ec4f194f0dc459ddee794