[core] split a big function to 4 sub functions so that we can efficiently reuse for mock wrapper

openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp

@@ -330,19 +330,29 @@ int print_verilog_mock_fpga_wrapper(
   std::vector<std::string> benchmark_clock_port_names =
     find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
 
+  /* Print local wires */
+  print_verilog_testbench_shared_input_ports(
+    fp, module_manager, global_ports, pin_constraints, atom_ctx,
+    netlist_annotation, benchmark_clock_port_names,
+    std::string(APPINST_PORT_POSTFIX), false);
+
+  print_verilog_testbench_shared_benchmark_output_ports(
+    fp, atom_ctx, netlist_annotation, std::string(APPINST_PORT_POSTFIX));
+
   /* Instanciate application HDL module */
   print_verilog_testbench_benchmark_instance(
     fp, circuit_name, std::string(APP_INSTANCE_NAME), std::string(),
-    std::string(), std::string(APPINST_PORT_POSTFIX), std::string(APPINST_PORT_POSTFIX),
+    std::string(), std::string(APPINST_PORT_POSTFIX),
-    benchmark_clock_port_names, atom_ctx, netlist_annotation, pin_constraints,
+    std::string(APPINST_PORT_POSTFIX), benchmark_clock_port_names, atom_ctx,
-    bus_group, options.explicit_port_mapping());
+    netlist_annotation, pin_constraints, bus_group,
+    options.explicit_port_mapping());
 
   /* Connect I/Os to benchmark I/Os or constant driver */
   print_verilog_mock_fpga_wrapper_connect_ios(
     fp, module_manager, top_module, atom_ctx, place_ctx, io_location_map,
     netlist_annotation, bus_group, std::string(),
-    std::string(APPINST_PORT_POSTFIX), std::string(APPINST_PORT_POSTFIX), std::vector<std::string>(),
+    std::string(APPINST_PORT_POSTFIX), std::string(APPINST_PORT_POSTFIX),
-    (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
+    std::vector<std::string>(), (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
 
   /* Testbench ends*/
   print_verilog_module_end(fp, title);

openfpga/src/fpga_verilog/verilog_testbench_utils.cpp

@@ -914,20 +914,15 @@ void print_verilog_testbench_random_stimuli(
  * which are
  * 1. the shared input ports (registers) to drive both
  *    FPGA fabric and benchmark instance
- * 2. the output ports (wires) for both FPGA fabric and benchmark instance
- * 3. the checking flag ports to evaluate if outputs matches under the
  *    same input vectors
  *******************************************************************/
-void print_verilog_testbench_shared_ports(
+void print_verilog_testbench_shared_input_ports(
   std::fstream& fp, const ModuleManager& module_manager,
   const FabricGlobalPortInfo& global_ports,
   const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
   const VprNetlistAnnotation& netlist_annotation,
   const std::vector<std::string>& clock_port_names,
-  const std::string& shared_input_port_postfix,
+  const std::string& shared_input_port_postfix, const bool& use_reg_port) {
-  const std::string& benchmark_output_port_postfix,
-  const std::string& fpga_output_port_postfix,
-  const std::string& check_flag_port_postfix, const bool& no_self_checking) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -959,8 +954,13 @@ void print_verilog_testbench_shared_ports(
     if (false ==
         port_is_fabric_global_reset_port(global_ports, module_manager,
                                          pin_constraints.net_pin(block_name))) {
-      fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";"
+      if (use_reg_port) {
-         << std::endl;
+        fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";"
+           << std::endl;
+      } else {
+        fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, input_port)
+           << ";" << std::endl;
+      }
     } else {
       fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, input_port) << ";"
          << std::endl;
@@ -969,6 +969,19 @@ void print_verilog_testbench_shared_ports(
 
   /* Add an empty line as splitter */
   fp << std::endl;
+}
+
+/********************************************************************
+ * Print Verilog declaration of shared ports appear in testbenches
+ * which are
+ * 2. the output ports (wires) for FPGA fabric
+ *******************************************************************/
+void print_verilog_testbench_shared_fpga_output_ports(
+  std::fstream& fp, const AtomContext& atom_ctx,
+  const VprNetlistAnnotation& netlist_annotation,
+  const std::string& fpga_output_port_postfix) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
 
   /* Instantiate wires for FPGA fabric outputs */
   print_verilog_comment(fp, std::string("----- FPGA fabric outputs -------"));
@@ -996,10 +1009,19 @@ void print_verilog_testbench_shared_ports(
 
   /* Add an empty line as splitter */
   fp << std::endl;
+}
 
-  if (no_self_checking) {
+/********************************************************************
-    return;
+ * Print Verilog declaration of shared ports appear in testbenches
-  }
+ * which are
+ * 2. the output ports (wires) for benchmark instance
+ *******************************************************************/
+void print_verilog_testbench_shared_benchmark_output_ports(
+  std::fstream& fp, const AtomContext& atom_ctx,
+  const VprNetlistAnnotation& netlist_annotation,
+  const std::string& benchmark_output_port_postfix) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
 
   /* Instantiate wire for benchmark output */
   print_verilog_comment(fp, std::string("----- Benchmark outputs -------"));
@@ -1026,6 +1048,23 @@ void print_verilog_testbench_shared_ports(
 
   /* Add an empty line as splitter */
   fp << std::endl;
+}
+
+/********************************************************************
+ * Print Verilog declaration of shared ports appear in testbenches
+ * which are
+ * 1. the shared input ports (registers) to drive both
+ *    FPGA fabric and benchmark instance
+ * 2. the output ports (wires) for both FPGA fabric and benchmark instance
+ * 3. the checking flag ports to evaluate if outputs matches under the
+ *    same input vectors
+ *******************************************************************/
+void print_verilog_testbench_shared_check_flags(
+  std::fstream& fp, const AtomContext& atom_ctx,
+  const VprNetlistAnnotation& netlist_annotation,
+  const std::string& check_flag_port_postfix) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
 
   /* Instantiate register for output comparison */
   print_verilog_comment(
@@ -1054,6 +1093,43 @@ void print_verilog_testbench_shared_ports(
   fp << std::endl;
 }
 
+/********************************************************************
+ * Print Verilog declaration of shared ports appear in testbenches
+ * which are
+ * 1. the shared input ports (registers) to drive both
+ *    FPGA fabric and benchmark instance
+ * 2. the output ports (wires) for both FPGA fabric and benchmark instance
+ * 3. the checking flag ports to evaluate if outputs matches under the
+ *    same input vectors
+ *******************************************************************/
+void print_verilog_testbench_shared_ports(
+  std::fstream& fp, const ModuleManager& module_manager,
+  const FabricGlobalPortInfo& global_ports,
+  const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
+  const VprNetlistAnnotation& netlist_annotation,
+  const std::vector<std::string>& clock_port_names,
+  const std::string& shared_input_port_postfix,
+  const std::string& benchmark_output_port_postfix,
+  const std::string& fpga_output_port_postfix,
+  const std::string& check_flag_port_postfix, const bool& no_self_checking) {
+  print_verilog_testbench_shared_input_ports(
+    fp, module_manager, global_ports, pin_constraints, atom_ctx,
+    netlist_annotation, clock_port_names, shared_input_port_postfix, true);
+
+  print_verilog_testbench_shared_fpga_output_ports(
+    fp, atom_ctx, netlist_annotation, fpga_output_port_postfix);
+
+  if (no_self_checking) {
+    return;
+  }
+
+  print_verilog_testbench_shared_benchmark_output_ports(
+    fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix);
+
+  print_verilog_testbench_shared_check_flags(fp, atom_ctx, netlist_annotation,
+                                             check_flag_port_postfix);
+}
+
 /********************************************************************
  * Print signal initialization which
  * deposit initial values for the input ports of primitive circuit models

openfpga/src/fpga_verilog/verilog_testbench_utils.h

@@ -90,6 +90,29 @@ void print_verilog_testbench_random_stimuli(
   const std::string& check_flag_port_postfix,
   const std::vector<BasicPort>& clock_ports, const bool& no_self_checking);
 
+void print_verilog_testbench_shared_input_ports(
+  std::fstream& fp, const ModuleManager& module_manager,
+  const FabricGlobalPortInfo& global_ports,
+  const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
+  const VprNetlistAnnotation& netlist_annotation,
+  const std::vector<std::string>& clock_port_names,
+  const std::string& shared_input_port_postfix, const bool& use_reg_port);
+
+void print_verilog_testbench_shared_fpga_output_ports(
+  std::fstream& fp, const AtomContext& atom_ctx,
+  const VprNetlistAnnotation& netlist_annotation,
+  const std::string& fpga_output_port_postfix);
+
+void print_verilog_testbench_shared_benchmark_output_ports(
+  std::fstream& fp, const AtomContext& atom_ctx,
+  const VprNetlistAnnotation& netlist_annotation,
+  const std::string& benchmark_output_port_postfix);
+
+void print_verilog_testbench_shared_check_flags(
+  std::fstream& fp, const AtomContext& atom_ctx,
+  const VprNetlistAnnotation& netlist_annotation,
+  const std::string& check_flag_port_postfix);
+
 void print_verilog_testbench_shared_ports(
   std::fstream& fp, const ModuleManager& module_manager,
   const FabricGlobalPortInfo& global_ports,