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[Script] Rename yosys script supporting bram and restructure techlib files

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tangxifan 2021-03-16 16:16:53 -06:00
parent 74785f328c
commit 76837e02e6
5 changed files with 0 additions and 41 deletions
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openfpga_flow/misc/yosys_bram_adder_template.ys
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# Yosys synthesis script for alu4
# read Verilog
read_verilog /full_path/design.v #can be repeated if project has many files
read_verilog -lib /full_path/cells_sim.v # file we provide
hierarchy -check -top top_module
proc
flatten
tribuf -logic
synth -run coarse
opt -fast
memory -nomap
opt_clean
memory_bram -rules /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams.txt
techmap -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams_map.v
opt -fast -mux_undef -undriven -fine
memory_map
# Technology mapping
#proc
techmap -D NO_LUT -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v -map +/adff2dff.v
# Synthesis
synth -top top_module -flatten -run fine
clean
# LUT mapping
abc -lut 6
# Check
synth -run check
# Clean and output blif
opt_clean -purge
write_blif design.blif
write_verilog design.v

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openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v → openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v
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openfpga_flow/misc/OpenFPGA_lib/brams.txt → openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt
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openfpga_flow/misc/OpenFPGA_lib/brams_map.v → openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v
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openfpga_flow/misc/OpenFPGA_lib/cells_sim.v → openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
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