From 76837e02e6dff68aa0c62430e6049f25347d0a0a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Mar 2021 16:16:53 -0600 Subject: [PATCH] [Script] Rename yosys script supporting bram and restructure techlib files --- .../misc/yosys_bram_adder_template.ys | 41 ------------------- .../openfpga_arith_map.v} | 0 .../openfpga_brams.txt} | 0 .../openfpga_brams_map.v} | 0 .../openfpga_brams_sim.v} | 0 5 files changed, 41 deletions(-) delete mode 100644 openfpga_flow/misc/yosys_bram_adder_template.ys rename openfpga_flow/{misc/OpenFPGA_lib/fpga_techmap.v => openfpga_yosys_techlib/openfpga_arith_map.v} (100%) rename openfpga_flow/{misc/OpenFPGA_lib/brams.txt => openfpga_yosys_techlib/openfpga_brams.txt} (100%) rename openfpga_flow/{misc/OpenFPGA_lib/brams_map.v => openfpga_yosys_techlib/openfpga_brams_map.v} (100%) rename openfpga_flow/{misc/OpenFPGA_lib/cells_sim.v => openfpga_yosys_techlib/openfpga_brams_sim.v} (100%) diff --git a/openfpga_flow/misc/yosys_bram_adder_template.ys b/openfpga_flow/misc/yosys_bram_adder_template.ys deleted file mode 100644 index fe82173f4..000000000 --- a/openfpga_flow/misc/yosys_bram_adder_template.ys +++ /dev/null @@ -1,41 +0,0 @@ -# Yosys synthesis script for alu4 -# read Verilog -read_verilog /full_path/design.v #can be repeated if project has many files -read_verilog -lib /full_path/cells_sim.v # file we provide - -hierarchy -check -top top_module -proc - -flatten -tribuf -logic - -synth -run coarse -opt -fast - -memory -nomap -opt_clean - - -memory_bram -rules /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams.txt -techmap -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams_map.v -opt -fast -mux_undef -undriven -fine -memory_map - -# Technology mapping -#proc -techmap -D NO_LUT -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v -map +/adff2dff.v - -# Synthesis -synth -top top_module -flatten -run fine -clean - -# LUT mapping -abc -lut 6 - -# Check -synth -run check - -# Clean and output blif -opt_clean -purge -write_blif design.blif -write_verilog design.v diff --git a/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v diff --git a/openfpga_flow/misc/OpenFPGA_lib/brams.txt b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/brams.txt rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt diff --git a/openfpga_flow/misc/OpenFPGA_lib/brams_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/brams_map.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v diff --git a/openfpga_flow/misc/OpenFPGA_lib/cells_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/cells_sim.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v