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[Test] Update bug group examples on the big endian support

This commit is contained in:
tangxifan 2022-02-18 23:09:03 -08:00
parent b78e58d9bf
commit 7645d5332d
4 changed files with 36 additions and 36 deletions
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18
openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/counter8_bus_group.xml
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@ -1,12 +1,12 @@
<bus_group> <bus_group>
<bus name="result[0:7]"> <bus name="result[7:0]" big_endian="false">
<pin id="0" name="result_7_"/> <pin id="0" name="result_0_"/>
<pin id="1" name="result_6_"/> <pin id="1" name="result_1_"/>
<pin id="2" name="result_5_"/> <pin id="2" name="result_2_"/>
<pin id="3" name="result_4_"/> <pin id="3" name="result_3_"/>
<pin id="4" name="result_3_"/> <pin id="4" name="result_4_"/>
<pin id="5" name="result_2_"/> <pin id="5" name="result_5_"/>
<pin id="6" name="result_1_"/> <pin id="6" name="result_6_"/>
<pin id="7" name="result_0_"/> <pin id="7" name="result_7_"/>
</bus> </bus>
</bus_group> </bus_group>

18
openfpga_flow/tasks/basic_tests/bus_group/full_testbench_implicit_mapping/config/counter8_bus_group.xml
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@ -1,12 +1,12 @@
<bus_group> <bus_group>
<bus name="result[0:7]"> <bus name="result[7:0]" big_endian="false">
<pin id="0" name="result_7_"/> <pin id="0" name="result_0_"/>
<pin id="1" name="result_6_"/> <pin id="1" name="result_1_"/>
<pin id="2" name="result_5_"/> <pin id="2" name="result_2_"/>
<pin id="3" name="result_4_"/> <pin id="3" name="result_3_"/>
<pin id="4" name="result_3_"/> <pin id="4" name="result_4_"/>
<pin id="5" name="result_2_"/> <pin id="5" name="result_5_"/>
<pin id="6" name="result_1_"/> <pin id="6" name="result_6_"/>
<pin id="7" name="result_0_"/> <pin id="7" name="result_7_"/>
</bus> </bus>
</bus_group> </bus_group>

18
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/counter8_bus_group.xml
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@ -1,12 +1,12 @@
<bus_group> <bus_group>
<bus name="result[0:7]"> <bus name="result[7:0]" big_endian="false">
<pin id="0" name="result_7_"/> <pin id="0" name="result_0_"/>
<pin id="1" name="result_6_"/> <pin id="1" name="result_1_"/>
<pin id="2" name="result_5_"/> <pin id="2" name="result_2_"/>
<pin id="3" name="result_4_"/> <pin id="3" name="result_3_"/>
<pin id="4" name="result_3_"/> <pin id="4" name="result_4_"/>
<pin id="5" name="result_2_"/> <pin id="5" name="result_5_"/>
<pin id="6" name="result_1_"/> <pin id="6" name="result_6_"/>
<pin id="7" name="result_0_"/> <pin id="7" name="result_7_"/>
</bus> </bus>
</bus_group> </bus_group>

18
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_implicit_mapping/config/counter8_bus_group.xml
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@ -1,12 +1,12 @@
<bus_group> <bus_group>
<bus name="result[0:7]"> <bus name="result[7:0]" big_endian="false">
<pin id="0" name="result_7_"/> <pin id="0" name="result_0_"/>
<pin id="1" name="result_6_"/> <pin id="1" name="result_1_"/>
<pin id="2" name="result_5_"/> <pin id="2" name="result_2_"/>
<pin id="3" name="result_4_"/> <pin id="3" name="result_3_"/>
<pin id="4" name="result_3_"/> <pin id="4" name="result_4_"/>
<pin id="5" name="result_2_"/> <pin id="5" name="result_5_"/>
<pin id="6" name="result_1_"/> <pin id="6" name="result_6_"/>
<pin id="7" name="result_0_"/> <pin id="7" name="result_7_"/>
</bus> </bus>
</bus_group> </bus_group>