diff --git a/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/counter8_bus_group.xml b/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/counter8_bus_group.xml
index 51dccca71..a0fd22f77 100644
--- a/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/counter8_bus_group.xml
+++ b/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/counter8_bus_group.xml
@@ -1,12 +1,12 @@
 <bus_group>
-  <bus name="result[0:7]">
-    <pin id="0" name="result_7_"/>
-    <pin id="1" name="result_6_"/>
-    <pin id="2" name="result_5_"/>
-    <pin id="3" name="result_4_"/>
-    <pin id="4" name="result_3_"/>
-    <pin id="5" name="result_2_"/>
-    <pin id="6" name="result_1_"/>
-    <pin id="7" name="result_0_"/>
+  <bus name="result[7:0]" big_endian="false">
+    <pin id="0" name="result_0_"/>
+    <pin id="1" name="result_1_"/>
+    <pin id="2" name="result_2_"/>
+    <pin id="3" name="result_3_"/>
+    <pin id="4" name="result_4_"/>
+    <pin id="5" name="result_5_"/>
+    <pin id="6" name="result_6_"/>
+    <pin id="7" name="result_7_"/>
   </bus>
 </bus_group>
diff --git a/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_implicit_mapping/config/counter8_bus_group.xml b/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_implicit_mapping/config/counter8_bus_group.xml
index 51dccca71..a0fd22f77 100644
--- a/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_implicit_mapping/config/counter8_bus_group.xml
+++ b/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_implicit_mapping/config/counter8_bus_group.xml
@@ -1,12 +1,12 @@
 <bus_group>
-  <bus name="result[0:7]">
-    <pin id="0" name="result_7_"/>
-    <pin id="1" name="result_6_"/>
-    <pin id="2" name="result_5_"/>
-    <pin id="3" name="result_4_"/>
-    <pin id="4" name="result_3_"/>
-    <pin id="5" name="result_2_"/>
-    <pin id="6" name="result_1_"/>
-    <pin id="7" name="result_0_"/>
+  <bus name="result[7:0]" big_endian="false">
+    <pin id="0" name="result_0_"/>
+    <pin id="1" name="result_1_"/>
+    <pin id="2" name="result_2_"/>
+    <pin id="3" name="result_3_"/>
+    <pin id="4" name="result_4_"/>
+    <pin id="5" name="result_5_"/>
+    <pin id="6" name="result_6_"/>
+    <pin id="7" name="result_7_"/>
   </bus>
 </bus_group>
diff --git a/openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/counter8_bus_group.xml b/openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/counter8_bus_group.xml
index 51dccca71..a0fd22f77 100644
--- a/openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/counter8_bus_group.xml
+++ b/openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/counter8_bus_group.xml
@@ -1,12 +1,12 @@
 <bus_group>
-  <bus name="result[0:7]">
-    <pin id="0" name="result_7_"/>
-    <pin id="1" name="result_6_"/>
-    <pin id="2" name="result_5_"/>
-    <pin id="3" name="result_4_"/>
-    <pin id="4" name="result_3_"/>
-    <pin id="5" name="result_2_"/>
-    <pin id="6" name="result_1_"/>
-    <pin id="7" name="result_0_"/>
+  <bus name="result[7:0]" big_endian="false">
+    <pin id="0" name="result_0_"/>
+    <pin id="1" name="result_1_"/>
+    <pin id="2" name="result_2_"/>
+    <pin id="3" name="result_3_"/>
+    <pin id="4" name="result_4_"/>
+    <pin id="5" name="result_5_"/>
+    <pin id="6" name="result_6_"/>
+    <pin id="7" name="result_7_"/>
   </bus>
 </bus_group>
diff --git a/openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_implicit_mapping/config/counter8_bus_group.xml b/openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_implicit_mapping/config/counter8_bus_group.xml
index 51dccca71..a0fd22f77 100644
--- a/openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_implicit_mapping/config/counter8_bus_group.xml
+++ b/openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_implicit_mapping/config/counter8_bus_group.xml
@@ -1,12 +1,12 @@
 <bus_group>
-  <bus name="result[0:7]">
-    <pin id="0" name="result_7_"/>
-    <pin id="1" name="result_6_"/>
-    <pin id="2" name="result_5_"/>
-    <pin id="3" name="result_4_"/>
-    <pin id="4" name="result_3_"/>
-    <pin id="5" name="result_2_"/>
-    <pin id="6" name="result_1_"/>
-    <pin id="7" name="result_0_"/>
+  <bus name="result[7:0]" big_endian="false">
+    <pin id="0" name="result_0_"/>
+    <pin id="1" name="result_1_"/>
+    <pin id="2" name="result_2_"/>
+    <pin id="3" name="result_3_"/>
+    <pin id="4" name="result_4_"/>
+    <pin id="5" name="result_5_"/>
+    <pin id="6" name="result_6_"/>
+    <pin id="7" name="result_7_"/>
   </bus>
 </bus_group>