[HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes

openfpga_flow/openfpga_cell_library/verilog/dff.v

@@ -20,12 +20,7 @@ always @ (posedge CK) begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
+assign Q = q_reg;
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-`else
-  assign Q = 1'bZ;
-`endif
 
 endmodule //End Of Module
 
@@ -46,14 +41,8 @@ always @ (posedge CK) begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
+assign Q = q_reg;
-`ifndef ENABLE_FORMAL_VERIFICATION
+assign QN = ~q_reg;
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -79,12 +68,7 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
+assign Q = q_reg;
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-`else
-  assign Q = 1'bZ;
-`endif
 
 endmodule //End Of Module
 
@@ -111,14 +95,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
+assign Q = q_reg;
-`ifndef ENABLE_FORMAL_VERIFICATION
+assign QN = ~q_reg;
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -144,14 +122,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
+assign Q = q_reg;
-`ifndef ENABLE_FORMAL_VERIFICATION
+assign QN = ~q_reg;
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -178,14 +150,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
+assign Q = q_reg;
-`ifndef ENABLE_FORMAL_VERIFICATION
+assign QN = ~q_reg;
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -211,14 +177,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
+assign Q = q_reg;
-`ifndef ENABLE_FORMAL_VERIFICATION
+assign QN = ~q_reg;
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -249,14 +209,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
+assign Q = q_reg;
-`ifndef ENABLE_FORMAL_VERIFICATION
+assign QN = ~q_reg;
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -349,14 +303,8 @@ end else begin
   q_reg <= D;
 end
 
-`ifndef ENABLE_FORMAL_VERIFICATION
+assign Q = q_reg;
-// Wire q_reg to Q
+assign QN = !Q;
-  assign Q = q_reg;
-  assign QN = !Q;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -462,13 +410,7 @@ end
 assign CFGQ = CFGE ? Q : 1'b0;
 assign CFGQN = CFGE ? QN : 1'b1;
 
-`ifndef ENABLE_FORMAL_VERIFICATION
+assign Q = q_reg;
-// Wire q_reg to Q
+assign QN = !Q;
-  assign Q = q_reg;
-  assign QN = !Q;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module