From 75a12e55de609550b47274e0434c1f8e4e2d7234 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 29 Jun 2021 11:40:22 -0600
Subject: [PATCH] [HDL] Remove the instrusive signal initialization in the
 configuration flip-flop HDL codes

---
 .../openfpga_cell_library/verilog/dff.v       | 94 ++++---------------
 1 file changed, 18 insertions(+), 76 deletions(-)

diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v
index a1d3e2407..c3a5e538e 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dff.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v
@@ -20,12 +20,7 @@ always @ (posedge CK) begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-`else
-  assign Q = 1'bZ;
-`endif
+assign Q = q_reg;
 
 endmodule //End Of Module
 
@@ -46,14 +41,8 @@ always @ (posedge CK) begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
+assign Q = q_reg;
+assign QN = ~q_reg;
 
 endmodule //End Of Module
 
@@ -79,12 +68,7 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-`else
-  assign Q = 1'bZ;
-`endif
+assign Q = q_reg;
 
 endmodule //End Of Module
 
@@ -111,14 +95,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
+assign Q = q_reg;
+assign QN = ~q_reg;
 
 endmodule //End Of Module
 
@@ -144,14 +122,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
+assign Q = q_reg;
+assign QN = ~q_reg;
 
 endmodule //End Of Module
 
@@ -178,14 +150,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
+assign Q = q_reg;
+assign QN = ~q_reg;
 
 endmodule //End Of Module
 
@@ -211,14 +177,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
+assign Q = q_reg;
+assign QN = ~q_reg;
 
 endmodule //End Of Module
 
@@ -249,14 +209,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
-  assign Q = q_reg;
-  assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
+assign Q = q_reg;
+assign QN = ~q_reg;
 
 endmodule //End Of Module
 
@@ -349,14 +303,8 @@ end else begin
   q_reg <= D;
 end
 
-`ifndef ENABLE_FORMAL_VERIFICATION
-// Wire q_reg to Q
-  assign Q = q_reg;
-  assign QN = !Q;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
+assign Q = q_reg;
+assign QN = !Q;
 
 endmodule //End Of Module
 
@@ -462,13 +410,7 @@ end
 assign CFGQ = CFGE ? Q : 1'b0;
 assign CFGQN = CFGE ? QN : 1'b1;
 
-`ifndef ENABLE_FORMAL_VERIFICATION
-// Wire q_reg to Q
-  assign Q = q_reg;
-  assign QN = !Q;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
+assign Q = q_reg;
+assign QN = !Q;
 
 endmodule //End Of Module