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[FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers

This commit is contained in:
tangxifan 2021-10-03 12:11:20 -07:00
parent 3eb601531a
commit 756b4c7dc8
1 changed files with 1 additions and 1 deletions
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2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -874,7 +874,7 @@ size_t calculate_num_config_clock_cycles(const ConfigProtocol& config_protocol,
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) { } else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip).size(); num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip).size();
} else if (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()) { } else if (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()) {
/* TODO */ num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip).size();
} }
break; break;
} }