From 756b4c7dc8b574416b884c18fd0bb53f887b3a5c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 3 Oct 2021 12:11:20 -0700 Subject: [PATCH] [FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index f3832fdc3..f8477df5f 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -874,7 +874,7 @@ size_t calculate_num_config_clock_cycles(const ConfigProtocol& config_protocol, } else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) { num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip).size(); } else if (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()) { - /* TODO */ + num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip).size(); } break; }