start creating the class for circuit models
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tangxifan
parent
f57495feba
commit
74da4ed51a
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@ -35,11 +35,12 @@ set_target_properties(libarchfpga PROPERTIES PREFIX "") #Avoid extra 'lib' prefi
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# Specify dependency
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# Specify dependency
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target_link_libraries(libarchfpga
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target_link_libraries(libarchfpga
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libvtrutil
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libpcre
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libpcre
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libprinthandler)
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libprinthandler)
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add_executable(read_arch ${EXEC_SOURCES})
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add_executable(read_arch ${EXEC_SOURCES})
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target_link_libraries(read_arch libarchfpga)
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target_link_libraries(read_arch libarchfpga libvtrutil)
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# install: TO BE TESTED
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# install: TO BE TESTED
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@ -0,0 +1,58 @@
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/**********************************************************
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* MIT License
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*
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* Copyright (c) 2018 LNIS - The University of Utah
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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***********************************************************************/
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/************************************************************************
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* Filename: circuit_library.cpp
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* Created by: Xifan Tang
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* Change history:
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* +-------------------------------------+
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* | Date | Author | Notes
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* +-------------------------------------+
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* | 2019/08/07 | Xifan Tang | Created
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* +-------------------------------------+
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***********************************************************************/
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#include "circuit_library.h"
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/************************************************************************
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* Member functions for class CircuitLibrary
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***********************************************************************/
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/************************************************************************
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* Constructors
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***********************************************************************/
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/************************************************************************
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* Accessors
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***********************************************************************/
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/* Aggregates */
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CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const {
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return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end());
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}
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/************************************************************************
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* End of file : circuit_library.cpp
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***********************************************************************/
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@ -0,0 +1,316 @@
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/**********************************************************
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* MIT License
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*
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* Copyright (c) 2018 LNIS - The University of Utah
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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***********************************************************************/
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/************************************************************************
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* Filename: circuit_library.h
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* Created by: Xifan Tang
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* Change history:
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* +-------------------------------------+
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* | Date | Author | Notes
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* +-------------------------------------+
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* | 2019/08/06 | Xifan Tang | Created
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* +-------------------------------------+
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***********************************************************************/
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/* IMPORTANT:
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* The following preprocessing flags are added to
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* avoid compilation error when this headers are included in more than 1 times
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*/
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#ifndef CIRCUIT_LIBRARY_H
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#define CIRCUIT_LIBRARY_H
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/*
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* Notes in include header files in a head file
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* Only include the neccessary header files
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* that is required by the data types in the function/class declarations!
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*/
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/* Header files should be included in a sequence */
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/* Standard header files required go first */
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#include "vtr_strong_id.h"
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#include "vtr_vector.h"
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#include "vtr_range.h"
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#include "spice_types.h"
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/************************************************************************
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* Create strong id for Circuit Models/Ports to avoid illegal type casting
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***********************************************************************/
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struct circuit_model_id_tag;
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struct circuit_port_id_tag;
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struct circuit_edge_id_tag;
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typedef vtr::StrongId<circuit_model_id_tag> CircuitModelId;
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typedef vtr::StrongId<circuit_port_id_tag> CircuitPortId;
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typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
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/************************************************************************
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* The class CircuitLibrary is a critical data structure for OpenFPGA
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* It stores all the circuit-level details from XML architecture file
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*
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* It includes the following data:
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*
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* ------ Fundamental Information -----
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* 1. circuit_model_ids_ : unique identifier to find a circuit model
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* Use a strong id for search, to avoid illegal type casting
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* 2. circuit_model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type
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* 3. circuit_model_names_: unique names for each circuit models.
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* It should be the same as user-defined Verilog modules, if it is not auto-generated
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* 4. circuit_model_prefix_: the prefix of a circuit model when it is instanciated
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* 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated
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* 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated
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* 7. is_default_: indicate if the circuit model is the default one among all those in the same type
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*
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* ------ Verilog generation options -----
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* 1. dump_structural_verilog_: if Verilog generator will output structural Verilog syntax for the circuit model
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* 2. dump_explicit_port_map_: if Verilog generator will use explicit port mapping when instanciate the circuit model
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*
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* ------ Design technology information -----
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* 1. design_tech_: the design technology [cmos|rram] for each circuit model
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* 2. power_gated_: specify if the circuit model is power-gated (contain a input to turn on/off VDD and GND)
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*
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* ------ Buffer existence -----
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* Use vectors to simplify the defition of buffer existence:
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* index (low=0 to high) represents INPUT, OUTPUT, LUT_INPUT_BUF, LUT_INPUT_INV, LUT_INTER_BUFFER
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* 1. buffer_existence_: specify if this circuit model has an buffer
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* 2. buffer_circuit_model_name_: specify the name of circuit model for the buffer
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* 3. buffer_circuit_model_id_: specify the id of circuit model for the buffer
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*
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* ------ Pass-gate-related parameters ------
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* 1. pass_gate_logic_circuit_model_name_: specify the name of circuit model for the pass gate logic
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* 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic
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*
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* ------ Port information ------
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* 1. port_types_: types of ports belonging to a circuit model
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* 2. port_sizes_: width of ports belonging to a circuit model
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* 3. port_prefix_: prefix of a port when instance of a circuit model
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* 4. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled
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* 5. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port
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* 6. port_is_mode_select: specify if this port is used to select operating modes of the circuit model
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* 7. port_is_global: specify if this port is a global signal shared by other circuit model
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* 8. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches
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* 9. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches
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* 10. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches
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* 11. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches
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* 12. port_circuit_model_name: the name of circuit model linked to the port
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* 13. port_circuit_model_ids_: the Id of circuit model linked to the port
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* 14. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port
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* 15. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port
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* 16. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port
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* 17. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used
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* 18. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used
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* 19. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains
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*
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* ------ Delay information ------
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* 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge
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* 2. delay_in_port_names_: name of input ports that the pin-to-pin delay is linked to
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* 3. delay_in_port_names_: name of output ports that the pin-to-pin delay is linked to
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* 4. delay_values_: delay values of the pin-to-pin delay
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*
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* ------ Timing graph information: TODO: consider using tatum? ------
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* Timing graph is allocated when delay information is made
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* 1. edge_ids_ : ids of edges in the timing graph
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* 2. port_in_edge_ids_: ids of input edges for each pin of a circuit port
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* 3. port_out_edge_ids_: ids of output edges for each pin of a circuit port
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* 4. edge_src_port_ids_: ids of source ports that each edge is connected to
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* 5. edge_src_pin_ids_: ids of source pin that each edge is connected to
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* 6. edge_sink_port_ids_: ids of sink ports that each edge is connected to
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* 7. edge_sink_pin_ids_: ids of sink pin that each edge is connected to
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* 8. edge_trise_: rising delay of the edge
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* 9. edge_tfall_: falling delay of the edge
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*
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* ------ Buffer/Inverter-related parameters ------
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* Note: only applicable to circuit models whose type is buffer or inverter
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* 1. buffer_types_: type of the buffer, either buffer or inverter
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* 2. buffer_location_maps_: location of the buffer, only applicable to LUTs
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* 3. buffer_sizes_: size of buffer (transistor size for the first stage)
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* 4. buffer_is_tapered_: specify if this buffer has multiple stages
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* 5. buffer_num_levels: specify the number of levels of this buffer (if this is defined as multi-level buffer)
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* 6. buffer_f_per_stage: specify the driving strength of the buffer by stage
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*
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* ------ Pass-gate-logic-related parameters ------
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* Note: only applicable to circuit models whose type is pass-gate-logic
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* 1. pass_gate_logic_types_: types of the pass-gate-logic, either transmission-gate or pass-transistor
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* 2. pass_gate_logic_nmos_sizes_: size of NMOS transistor in the pass-gate-logic
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* 3. pass_gate_logic_pmos_sizes_: size of PMOS transistor in the pass-gate-logic, only applicable for transmission-gates
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*
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* ------ Multiplexer-related parameters ------
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* Note: only applicable to circuit models whose type is MUX
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* 1. mux_structure_: specify the structure of a multiplexer, one-level, multi-level or tree-like
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* 2. mux_num_levels_: specify the number of levels for a multiplexer
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* 3. mux_add_const_input_: specify if this multiplexer has a constant input
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* 4. mux_const_input_values_: specify the value of the constant input for this multiplexer (valid only when mux_add_const_input is true)
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* 5. mux_use_local_encoder_: specify if the mux as a local encoder between SRAMs and multiplexing structure
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* 6. mux_advanced_rram_design_: specify if the multiplexer will use advanced RRAM circuit design topology
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*
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* ------ LUT-related parameters ------
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* Note: only applicable to circuit models whose type is LUT
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* 1. lut_is_fracturable_: specify if this LUT is built with fracturable structure
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*
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* ------ RRAM-related parameters ------
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* Note: only applicable to circuit models whose design technology is RRAM
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* 1. rlrs: RRAM resistance in Low-Resistance State (LRS)
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* 2. rhrs: RRAM resistance in High-Resistance State (HRS)
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* The following transistor sizes are applicable for 4T1R programming structures
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* 3. wprog_set_nmos: size of n-type programming transistor used to set a RRAM
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* 4. wprog_set_pmos: size of p-type programming transistor used to set a RRAM
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* 5. wprog_reset_nmos: size of n-type programming transistor used to reset a RRAM
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* 6. wprog_reset_pmos: size of p-type programming transistor used to reset a RRAM
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*
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* ------ Metal wire-related parameters ------
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* Note: only applicable to circuit models whose type is wires or channel wires
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* 1. wire_types_: types of the metal wire for the circuit_model
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* 2. wire_res_val_: resistance value of the metal wire for the circuit model
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* 3. wire_cap_val_: capacitance value of the metal wire for the circuit model
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* 4. wire_num_levels_: number of levels of the metal wire model for the circuit model
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***********************************************************************/
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class CircuitLibrary {
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public: /* Types */
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typedef vtr::vector<CircuitModelId, CircuitModelId>::const_iterator circuit_model_iterator;
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typedef vtr::vector<CircuitPortId, CircuitPortId>::const_iterator circuit_port_iterator;
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typedef vtr::vector<CircuitEdgeId, CircuitEdgeId>::const_iterator circuit_edge_iterator;
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/* Create range */
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typedef vtr::Range<circuit_model_iterator> circuit_model_range;
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typedef vtr::Range<circuit_port_iterator> circuit_port_range;
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typedef vtr::Range<circuit_edge_iterator> circuit_edge_range;
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/* local enumeration for buffer existence */
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enum e_buffer_type: unsigned char{
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INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INV, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */
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};
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public: /* Constructors */
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public: /* Accessors */
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/* Aggregates */
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circuit_model_range circuit_models() const;
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public: /* Mutators */
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private: /* Internal functions */
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private: /* Internal data */
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/* Fundamental information */
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vtr::vector<CircuitModelId, CircuitModelId> circuit_model_ids_;
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vtr::vector<CircuitModelId, enum e_spice_model_type> circuit_model_types_;
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vtr::vector<CircuitModelId, std::string> circuit_model_names_;
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vtr::vector<CircuitModelId, std::string> circuit_model_prefix_;
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vtr::vector<CircuitModelId, std::string> verilog_netlists_;
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vtr::vector<CircuitModelId, std::string> spice_netlists_;
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vtr::vector<CircuitModelId, bool> is_default_;
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/* Verilog generator options */
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vtr::vector<CircuitModelId, bool> dump_structural_verilog_;
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vtr::vector<CircuitModelId, bool> dump_explicit_port_map_;
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/* Design technology information */
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vtr::vector<CircuitModelId, enum e_spice_model_design_tech> design_tech_;
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vtr::vector<CircuitModelId, bool> power_gated_;
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/* Buffer existence */
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vtr::vector<CircuitModelId, std::vector<bool>> buffer_existence_;
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vtr::vector<CircuitModelId, std::vector<std::string>> buffer_circuit_model_name_;
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vtr::vector<CircuitModelId, std::vector<CircuitModelId>> buffer_circuit_model_id_;
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/* Pass-gate-related parameters */
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vtr::vector<CircuitModelId, std::string> pass_gate_logic_circuit_model_name_;
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vtr::vector<CircuitModelId, CircuitModelId> pass_gate_logic_circuit_model_id_;
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/* Port information */
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, enum e_spice_model_port_type>> port_types_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, size_t>> port_sizes_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_prefix_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_lib_names_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_inv_prefix_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_mode_select_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_global_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_reset_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_set_;
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_config_enable_;
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||||||
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_prog_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_circuit_model_names_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitModelId>> port_circuit_model_ids_;
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||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_inv_circuit_model_names_;
|
||||||
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitModelId>> port_inv_circuit_model_ids_;
|
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_tri_state_map_;
|
||||||
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vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, size_t>> port_lut_frac_level_;
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||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::vector<size_t>>> port_lut_output_mask_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, enum e_sram_orgz>> port_sram_orgz_;
|
||||||
|
|
||||||
|
/* Timing graphs */
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitEdgeId, CircuitEdgeId>> edge_ids_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::vector<size_t>>> port_in_edge_ids_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::vector<size_t>>> port_out_edge_ids_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitEdgeId, CircuitPortId>> edge_src_ports_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitEdgeId, size_t>> edge_src_pin_ids_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitEdgeId, CircuitPortId>> edge_sink_ports_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitEdgeId, size_t>> edge_sink_pin_ids_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitEdgeId, float>> edge_trise_;
|
||||||
|
vtr::vector<CircuitModelId, vtr::vector<CircuitEdgeId, float>> edge_tfall_;
|
||||||
|
|
||||||
|
/* Delay information */
|
||||||
|
vtr::vector<CircuitModelId, std::vector<enum spice_model_delay_type>> delay_types_;
|
||||||
|
vtr::vector<CircuitModelId, std::vector<std::string>> delay_in_port_names_;
|
||||||
|
vtr::vector<CircuitModelId, std::vector<std::string>> delay_out_port_names_;
|
||||||
|
vtr::vector<CircuitModelId, std::vector<std::string>> delay_values_;
|
||||||
|
|
||||||
|
/* Buffer/Inverter-related parameters */
|
||||||
|
vtr::vector<CircuitModelId, enum e_spice_model_buffer_type> buffer_types_;
|
||||||
|
vtr::vector<CircuitModelId, std::string> buffer_location_maps_;
|
||||||
|
vtr::vector<CircuitModelId, size_t> buffer_sizes_;
|
||||||
|
vtr::vector<CircuitModelId, bool> buffer_is_tapered_;
|
||||||
|
vtr::vector<CircuitModelId, size_t> buffer_num_levels_;
|
||||||
|
vtr::vector<CircuitModelId, size_t> buffer_f_per_stage_;
|
||||||
|
|
||||||
|
/* Pass-gate-related parameters */
|
||||||
|
vtr::vector<CircuitModelId, enum e_spice_model_pass_gate_logic_type> pass_gate_logic_types_;
|
||||||
|
vtr::vector<CircuitModelId, float> pass_gate_logic_nmos_sizes_;
|
||||||
|
vtr::vector<CircuitModelId, float> pass_gate_logic_pmos_sizes_;
|
||||||
|
|
||||||
|
/* Multiplexer-related parameters */
|
||||||
|
vtr::vector<CircuitModelId, enum e_spice_model_structure> mux_structure_;
|
||||||
|
vtr::vector<CircuitModelId, size_t> mux_num_levels_;
|
||||||
|
vtr::vector<CircuitModelId, bool> mux_add_const_input_;
|
||||||
|
vtr::vector<CircuitModelId, size_t> mux_const_input_values_;
|
||||||
|
vtr::vector<CircuitModelId, bool> mux_use_local_encoder_;
|
||||||
|
vtr::vector<CircuitModelId, bool> mux_advanced_rram_design_;
|
||||||
|
|
||||||
|
/* LUT-related parameters */
|
||||||
|
vtr::vector<CircuitModelId, bool> lut_is_fracturable_;
|
||||||
|
|
||||||
|
/* RRAM-related design technology information */
|
||||||
|
vtr::vector<CircuitModelId, float> rlrs_;
|
||||||
|
vtr::vector<CircuitModelId, float> rhrs_;
|
||||||
|
vtr::vector<CircuitModelId, float> wprog_set_nmos_;
|
||||||
|
vtr::vector<CircuitModelId, float> wprog_set_pmos_;
|
||||||
|
vtr::vector<CircuitModelId, float> wprog_reset_nmos_;
|
||||||
|
vtr::vector<CircuitModelId, float> wprog_reset_pmos_;
|
||||||
|
|
||||||
|
/* Wire parameters */
|
||||||
|
vtr::vector<CircuitModelId, enum e_wire_model_type> wire_types_;
|
||||||
|
vtr::vector<CircuitModelId, float> wire_res_val_;
|
||||||
|
vtr::vector<CircuitModelId, float> wire_cap_val_;
|
||||||
|
vtr::vector<CircuitModelId, size_t> wire_num_levels_;
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/************************************************************************
|
||||||
|
* End of file : circuit_library.cpp
|
||||||
|
***********************************************************************/
|
||||||
|
|
@ -411,3 +411,7 @@ class DeviceRRGSB {
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/************************************************************************
|
||||||
|
* End of file : rr_blocks.h
|
||||||
|
***********************************************************************/
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue