From 74da4ed51adf702fe2713611b7655aa7a42bb212 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Aug 2019 11:38:45 -0600 Subject: [PATCH] start creating the class for circuit models --- vpr7_x2p/libarchfpga/CMakeLists.txt | 3 +- .../fpga_spice_include/circuit_library.cpp | 58 ++++ .../SRC/fpga_spice_include/circuit_library.h | 316 ++++++++++++++++++ vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 4 + 4 files changed, 380 insertions(+), 1 deletion(-) create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h diff --git a/vpr7_x2p/libarchfpga/CMakeLists.txt b/vpr7_x2p/libarchfpga/CMakeLists.txt index 714349130..528310c1d 100644 --- a/vpr7_x2p/libarchfpga/CMakeLists.txt +++ b/vpr7_x2p/libarchfpga/CMakeLists.txt @@ -35,11 +35,12 @@ set_target_properties(libarchfpga PROPERTIES PREFIX "") #Avoid extra 'lib' prefi # Specify dependency target_link_libraries(libarchfpga + libvtrutil libpcre libprinthandler) add_executable(read_arch ${EXEC_SOURCES}) -target_link_libraries(read_arch libarchfpga) +target_link_libraries(read_arch libarchfpga libvtrutil) # install: TO BE TESTED diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp new file mode 100644 index 000000000..d873d716a --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -0,0 +1,58 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: circuit_library.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/07 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +#include "circuit_library.h" + +/************************************************************************ + * Member functions for class CircuitLibrary + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ + +/************************************************************************ + * Accessors + ***********************************************************************/ + +/* Aggregates */ +CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { + return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end()); +} + + +/************************************************************************ + * End of file : circuit_library.cpp + ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h new file mode 100644 index 000000000..3c4a5aebb --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -0,0 +1,316 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: circuit_library.h + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/06 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* IMPORTANT: + * The following preprocessing flags are added to + * avoid compilation error when this headers are included in more than 1 times + */ +#ifndef CIRCUIT_LIBRARY_H +#define CIRCUIT_LIBRARY_H + +/* + * Notes in include header files in a head file + * Only include the neccessary header files + * that is required by the data types in the function/class declarations! + */ +/* Header files should be included in a sequence */ +/* Standard header files required go first */ +#include "vtr_strong_id.h" + +#include "vtr_vector.h" +#include "vtr_range.h" + +#include "spice_types.h" + +/************************************************************************ + * Create strong id for Circuit Models/Ports to avoid illegal type casting + ***********************************************************************/ +struct circuit_model_id_tag; +struct circuit_port_id_tag; +struct circuit_edge_id_tag; + +typedef vtr::StrongId CircuitModelId; +typedef vtr::StrongId CircuitPortId; +typedef vtr::StrongId CircuitEdgeId; + +/************************************************************************ + * The class CircuitLibrary is a critical data structure for OpenFPGA + * It stores all the circuit-level details from XML architecture file + * + * It includes the following data: + * + * ------ Fundamental Information ----- + * 1. circuit_model_ids_ : unique identifier to find a circuit model + * Use a strong id for search, to avoid illegal type casting + * 2. circuit_model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type + * 3. circuit_model_names_: unique names for each circuit models. + * It should be the same as user-defined Verilog modules, if it is not auto-generated + * 4. circuit_model_prefix_: the prefix of a circuit model when it is instanciated + * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated + * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated + * 7. is_default_: indicate if the circuit model is the default one among all those in the same type + * + * ------ Verilog generation options ----- + * 1. dump_structural_verilog_: if Verilog generator will output structural Verilog syntax for the circuit model + * 2. dump_explicit_port_map_: if Verilog generator will use explicit port mapping when instanciate the circuit model + * + * ------ Design technology information ----- + * 1. design_tech_: the design technology [cmos|rram] for each circuit model + * 2. power_gated_: specify if the circuit model is power-gated (contain a input to turn on/off VDD and GND) + * + * ------ Buffer existence ----- + * Use vectors to simplify the defition of buffer existence: + * index (low=0 to high) represents INPUT, OUTPUT, LUT_INPUT_BUF, LUT_INPUT_INV, LUT_INTER_BUFFER + * 1. buffer_existence_: specify if this circuit model has an buffer + * 2. buffer_circuit_model_name_: specify the name of circuit model for the buffer + * 3. buffer_circuit_model_id_: specify the id of circuit model for the buffer + * + * ------ Pass-gate-related parameters ------ + * 1. pass_gate_logic_circuit_model_name_: specify the name of circuit model for the pass gate logic + * 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic + * + * ------ Port information ------ + * 1. port_types_: types of ports belonging to a circuit model + * 2. port_sizes_: width of ports belonging to a circuit model + * 3. port_prefix_: prefix of a port when instance of a circuit model + * 4. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled + * 5. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port + * 6. port_is_mode_select: specify if this port is used to select operating modes of the circuit model + * 7. port_is_global: specify if this port is a global signal shared by other circuit model + * 8. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches + * 9. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches + * 10. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches + * 11. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 12. port_circuit_model_name: the name of circuit model linked to the port + * 13. port_circuit_model_ids_: the Id of circuit model linked to the port + * 14. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port + * 15. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port + * 16. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 17. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 18. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 19. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * + * ------ Delay information ------ + * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge + * 2. delay_in_port_names_: name of input ports that the pin-to-pin delay is linked to + * 3. delay_in_port_names_: name of output ports that the pin-to-pin delay is linked to + * 4. delay_values_: delay values of the pin-to-pin delay + * + * ------ Timing graph information: TODO: consider using tatum? ------ + * Timing graph is allocated when delay information is made + * 1. edge_ids_ : ids of edges in the timing graph + * 2. port_in_edge_ids_: ids of input edges for each pin of a circuit port + * 3. port_out_edge_ids_: ids of output edges for each pin of a circuit port + * 4. edge_src_port_ids_: ids of source ports that each edge is connected to + * 5. edge_src_pin_ids_: ids of source pin that each edge is connected to + * 6. edge_sink_port_ids_: ids of sink ports that each edge is connected to + * 7. edge_sink_pin_ids_: ids of sink pin that each edge is connected to + * 8. edge_trise_: rising delay of the edge + * 9. edge_tfall_: falling delay of the edge + * + * ------ Buffer/Inverter-related parameters ------ + * Note: only applicable to circuit models whose type is buffer or inverter + * 1. buffer_types_: type of the buffer, either buffer or inverter + * 2. buffer_location_maps_: location of the buffer, only applicable to LUTs + * 3. buffer_sizes_: size of buffer (transistor size for the first stage) + * 4. buffer_is_tapered_: specify if this buffer has multiple stages + * 5. buffer_num_levels: specify the number of levels of this buffer (if this is defined as multi-level buffer) + * 6. buffer_f_per_stage: specify the driving strength of the buffer by stage + * + * ------ Pass-gate-logic-related parameters ------ + * Note: only applicable to circuit models whose type is pass-gate-logic + * 1. pass_gate_logic_types_: types of the pass-gate-logic, either transmission-gate or pass-transistor + * 2. pass_gate_logic_nmos_sizes_: size of NMOS transistor in the pass-gate-logic + * 3. pass_gate_logic_pmos_sizes_: size of PMOS transistor in the pass-gate-logic, only applicable for transmission-gates + * + * ------ Multiplexer-related parameters ------ + * Note: only applicable to circuit models whose type is MUX + * 1. mux_structure_: specify the structure of a multiplexer, one-level, multi-level or tree-like + * 2. mux_num_levels_: specify the number of levels for a multiplexer + * 3. mux_add_const_input_: specify if this multiplexer has a constant input + * 4. mux_const_input_values_: specify the value of the constant input for this multiplexer (valid only when mux_add_const_input is true) + * 5. mux_use_local_encoder_: specify if the mux as a local encoder between SRAMs and multiplexing structure + * 6. mux_advanced_rram_design_: specify if the multiplexer will use advanced RRAM circuit design topology + * + * ------ LUT-related parameters ------ + * Note: only applicable to circuit models whose type is LUT + * 1. lut_is_fracturable_: specify if this LUT is built with fracturable structure + * + * ------ RRAM-related parameters ------ + * Note: only applicable to circuit models whose design technology is RRAM + * 1. rlrs: RRAM resistance in Low-Resistance State (LRS) + * 2. rhrs: RRAM resistance in High-Resistance State (HRS) + * The following transistor sizes are applicable for 4T1R programming structures + * 3. wprog_set_nmos: size of n-type programming transistor used to set a RRAM + * 4. wprog_set_pmos: size of p-type programming transistor used to set a RRAM + * 5. wprog_reset_nmos: size of n-type programming transistor used to reset a RRAM + * 6. wprog_reset_pmos: size of p-type programming transistor used to reset a RRAM + * + * ------ Metal wire-related parameters ------ + * Note: only applicable to circuit models whose type is wires or channel wires + * 1. wire_types_: types of the metal wire for the circuit_model + * 2. wire_res_val_: resistance value of the metal wire for the circuit model + * 3. wire_cap_val_: capacitance value of the metal wire for the circuit model + * 4. wire_num_levels_: number of levels of the metal wire model for the circuit model + ***********************************************************************/ +class CircuitLibrary { + public: /* Types */ + typedef vtr::vector::const_iterator circuit_model_iterator; + typedef vtr::vector::const_iterator circuit_port_iterator; + typedef vtr::vector::const_iterator circuit_edge_iterator; + /* Create range */ + typedef vtr::Range circuit_model_range; + typedef vtr::Range circuit_port_range; + typedef vtr::Range circuit_edge_range; + /* local enumeration for buffer existence */ + enum e_buffer_type: unsigned char{ + INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INV, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */ + }; + public: /* Constructors */ + public: /* Accessors */ + /* Aggregates */ + circuit_model_range circuit_models() const; + public: /* Mutators */ + private: /* Internal functions */ + private: /* Internal data */ + /* Fundamental information */ + vtr::vector circuit_model_ids_; + vtr::vector circuit_model_types_; + vtr::vector circuit_model_names_; + vtr::vector circuit_model_prefix_; + vtr::vector verilog_netlists_; + vtr::vector spice_netlists_; + vtr::vector is_default_; + + /* Verilog generator options */ + vtr::vector dump_structural_verilog_; + vtr::vector dump_explicit_port_map_; + + /* Design technology information */ + vtr::vector design_tech_; + vtr::vector power_gated_; + + /* Buffer existence */ + vtr::vector> buffer_existence_; + vtr::vector> buffer_circuit_model_name_; + vtr::vector> buffer_circuit_model_id_; + + /* Pass-gate-related parameters */ + vtr::vector pass_gate_logic_circuit_model_name_; + vtr::vector pass_gate_logic_circuit_model_id_; + + /* Port information */ + vtr::vector> port_types_; + vtr::vector> port_sizes_; + vtr::vector> port_prefix_; + vtr::vector> port_lib_names_; + vtr::vector> port_inv_prefix_; + vtr::vector> port_is_mode_select_; + vtr::vector> port_is_global_; + vtr::vector> port_is_reset_; + vtr::vector> port_is_set_; + vtr::vector> port_is_config_enable_; + vtr::vector> port_is_prog_; + vtr::vector> port_circuit_model_names_; + vtr::vector> port_circuit_model_ids_; + vtr::vector> port_inv_circuit_model_names_; + vtr::vector> port_inv_circuit_model_ids_; + vtr::vector> port_tri_state_map_; + vtr::vector> port_lut_frac_level_; + vtr::vector>> port_lut_output_mask_; + vtr::vector> port_sram_orgz_; + + /* Timing graphs */ + vtr::vector> edge_ids_; + vtr::vector>> port_in_edge_ids_; + vtr::vector>> port_out_edge_ids_; + vtr::vector> edge_src_ports_; + vtr::vector> edge_src_pin_ids_; + vtr::vector> edge_sink_ports_; + vtr::vector> edge_sink_pin_ids_; + vtr::vector> edge_trise_; + vtr::vector> edge_tfall_; + + /* Delay information */ + vtr::vector> delay_types_; + vtr::vector> delay_in_port_names_; + vtr::vector> delay_out_port_names_; + vtr::vector> delay_values_; + + /* Buffer/Inverter-related parameters */ + vtr::vector buffer_types_; + vtr::vector buffer_location_maps_; + vtr::vector buffer_sizes_; + vtr::vector buffer_is_tapered_; + vtr::vector buffer_num_levels_; + vtr::vector buffer_f_per_stage_; + + /* Pass-gate-related parameters */ + vtr::vector pass_gate_logic_types_; + vtr::vector pass_gate_logic_nmos_sizes_; + vtr::vector pass_gate_logic_pmos_sizes_; + + /* Multiplexer-related parameters */ + vtr::vector mux_structure_; + vtr::vector mux_num_levels_; + vtr::vector mux_add_const_input_; + vtr::vector mux_const_input_values_; + vtr::vector mux_use_local_encoder_; + vtr::vector mux_advanced_rram_design_; + + /* LUT-related parameters */ + vtr::vector lut_is_fracturable_; + + /* RRAM-related design technology information */ + vtr::vector rlrs_; + vtr::vector rhrs_; + vtr::vector wprog_set_nmos_; + vtr::vector wprog_set_pmos_; + vtr::vector wprog_reset_nmos_; + vtr::vector wprog_reset_pmos_; + + /* Wire parameters */ + vtr::vector wire_types_; + vtr::vector wire_res_val_; + vtr::vector wire_cap_val_; + vtr::vector wire_num_levels_; + +}; + +#endif + +/************************************************************************ + * End of file : circuit_library.cpp + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index 49c1d78f4..6dd2437fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -411,3 +411,7 @@ class DeviceRRGSB { #endif +/************************************************************************ + * End of file : rr_blocks.h + ***********************************************************************/ +