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Update dpram1k.v

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Yunus Emre ERYILMAZ 2022-10-26 16:32:14 +03:00 committed by GitHub
parent 64b5b5c31c
commit 74568b13a2
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1 changed files with 2 additions and 2 deletions
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openfpga_flow/openfpga_cell_library/verilog/dpram1k.v
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@ -14,7 +14,7 @@ module dpram_128x8 (
input[0:7] d_in, input[0:7] d_in,
output[0:7] d_out ); output[0:7] d_out );
dual_port_sram memory_0 ( dpram_128x8_core memory_0 (
.wclk (clk), .wclk (clk),
.wen (wen), .wen (wen),
.waddr (waddr), .waddr (waddr),
@ -26,7 +26,7 @@ module dpram_128x8 (
endmodule endmodule
module dual_port_sram ( module dpram_128x8_core (
input wclk, input wclk,
input wen, input wen,
input[0:6] waddr, input[0:6] waddr,