Merge pull request #69 from LNIS-Projects/dev
Bug fix in yosys-vpr flow using OpenFPGA shell;
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS)
GitHub
commit
734b8ea1d0
|
|
@ -31,7 +31,7 @@ write_verilog_testbench
|
||||||
|
|
||||||
- ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
|
- ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
|
||||||
|
|
||||||
- ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to memory bank and frame-based configuration protocols. When enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.
|
- ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.
|
||||||
|
|
||||||
- ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
- ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -39,7 +39,7 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx,
|
||||||
int status = CMD_EXEC_SUCCESS;
|
int status = CMD_EXEC_SUCCESS;
|
||||||
status = fpga_fabric_spice(openfpga_ctx.module_graph(),
|
status = fpga_fabric_spice(openfpga_ctx.module_graph(),
|
||||||
openfpga_ctx.mutable_spice_netlists(),
|
openfpga_ctx.mutable_spice_netlists(),
|
||||||
openfpga_ctx.arch().tech_lib,
|
openfpga_ctx.arch(),
|
||||||
options);
|
options);
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
|
|
|
||||||
|
|
@ -39,7 +39,7 @@ namespace openfpga {
|
||||||
********************************************************************/
|
********************************************************************/
|
||||||
int fpga_fabric_spice(const ModuleManager& module_manager,
|
int fpga_fabric_spice(const ModuleManager& module_manager,
|
||||||
NetlistManager& netlist_manager,
|
NetlistManager& netlist_manager,
|
||||||
const TechnologyLibrary& tech_lib,
|
const Arch& openfpga_arch,
|
||||||
const FabricSpiceOption& options) {
|
const FabricSpiceOption& options) {
|
||||||
|
|
||||||
vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n");
|
vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n");
|
||||||
|
|
@ -71,7 +71,8 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
|
||||||
int status = CMD_EXEC_SUCCESS;
|
int status = CMD_EXEC_SUCCESS;
|
||||||
|
|
||||||
status = print_spice_submodule(netlist_manager,
|
status = print_spice_submodule(netlist_manager,
|
||||||
tech_lib,
|
module_manager,
|
||||||
|
openfpga_arch,
|
||||||
submodule_dir_path);
|
submodule_dir_path);
|
||||||
|
|
||||||
if (CMD_EXEC_SUCCESS != status) {
|
if (CMD_EXEC_SUCCESS != status) {
|
||||||
|
|
|
||||||
|
|
@ -9,7 +9,7 @@
|
||||||
#include <vector>
|
#include <vector>
|
||||||
#include "netlist_manager.h"
|
#include "netlist_manager.h"
|
||||||
#include "module_manager.h"
|
#include "module_manager.h"
|
||||||
#include "technology_library.h"
|
#include "openfpga_arch.h"
|
||||||
#include "fabric_spice_options.h"
|
#include "fabric_spice_options.h"
|
||||||
|
|
||||||
/********************************************************************
|
/********************************************************************
|
||||||
|
|
@ -21,7 +21,7 @@ namespace openfpga {
|
||||||
|
|
||||||
int fpga_fabric_spice(const ModuleManager& module_manager,
|
int fpga_fabric_spice(const ModuleManager& module_manager,
|
||||||
NetlistManager& netlist_manager,
|
NetlistManager& netlist_manager,
|
||||||
const TechnologyLibrary& tech_lib,
|
const Arch& openfpga_arch,
|
||||||
const FabricSpiceOption& options);
|
const FabricSpiceOption& options);
|
||||||
|
|
||||||
} /* end namespace openfpga */
|
} /* end namespace openfpga */
|
||||||
|
|
|
||||||
|
|
@ -18,6 +18,7 @@
|
||||||
#include "openfpga_digest.h"
|
#include "openfpga_digest.h"
|
||||||
|
|
||||||
#include "spice_constants.h"
|
#include "spice_constants.h"
|
||||||
|
#include "spice_writer_utils.h"
|
||||||
#include "spice_essential_gates.h"
|
#include "spice_essential_gates.h"
|
||||||
|
|
||||||
/* begin namespace openfpga */
|
/* begin namespace openfpga */
|
||||||
|
|
@ -82,7 +83,7 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
|
||||||
check_file_stream(spice_fname.c_str(), fp);
|
check_file_stream(spice_fname.c_str(), fp);
|
||||||
|
|
||||||
/* Create file */
|
/* Create file */
|
||||||
VTR_LOG("Generating SPICE netlist '%s' for transistor wrappers...",
|
VTR_LOG("Generating SPICE netlist '%s' for essential gates...",
|
||||||
spice_fname.c_str());
|
spice_fname.c_str());
|
||||||
|
|
||||||
/* Iterate over the transistor models */
|
/* Iterate over the transistor models */
|
||||||
|
|
@ -110,4 +111,165 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
|
||||||
return CMD_EXEC_SUCCESS;
|
return CMD_EXEC_SUCCESS;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/************************************************
|
||||||
|
* Generate the SPICE subckt for an inverter
|
||||||
|
* Schematic
|
||||||
|
* LVDD
|
||||||
|
* |
|
||||||
|
* -
|
||||||
|
* +-o||
|
||||||
|
* | -
|
||||||
|
* | |
|
||||||
|
* in-->+ +--> OUT
|
||||||
|
* | |
|
||||||
|
* | -
|
||||||
|
* +--||
|
||||||
|
* -
|
||||||
|
* |
|
||||||
|
* LGND
|
||||||
|
*
|
||||||
|
***********************************************/
|
||||||
|
static
|
||||||
|
int print_spice_inverter_subckt(std::fstream& fp,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const ModuleId& module_id,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const CircuitModelId& circuit_model,
|
||||||
|
const TechnologyLibrary& tech_lib,
|
||||||
|
const TechnologyModelId& tech_model) {
|
||||||
|
if (false == valid_file_stream(fp)) {
|
||||||
|
return CMD_EXEC_FATAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Print the inverter subckt definition */
|
||||||
|
print_spice_subckt_definition(fp, module_manager, module_id);
|
||||||
|
|
||||||
|
/* Find the input and output ports:
|
||||||
|
* we do NOT support global ports here,
|
||||||
|
* it should be handled in another type of inverter subckt (power-gated)
|
||||||
|
*/
|
||||||
|
std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
|
||||||
|
std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
|
||||||
|
|
||||||
|
/* Make sure:
|
||||||
|
* There is only 1 input port and 1 output port,
|
||||||
|
* each size of which is 1
|
||||||
|
*/
|
||||||
|
VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
|
||||||
|
VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
|
||||||
|
|
||||||
|
/* TODO: may consider use size/bin to compact layout etc. */
|
||||||
|
for (size_t i = 0; i < circuit_lib.buffer_size(circuit_model); ++i) {
|
||||||
|
/* Write transistor pairs using the technology model */
|
||||||
|
fp << "Xpmos_" << i << " ";
|
||||||
|
fp << circuit_lib.port_prefix(output_ports[0]) << " ";
|
||||||
|
fp << circuit_lib.port_prefix(input_ports[0]) << " ";
|
||||||
|
fp << "LVDD ";
|
||||||
|
fp << "LVDD ";
|
||||||
|
fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX;
|
||||||
|
|
||||||
|
fp << "Xnmos_" << i << " ";
|
||||||
|
fp << circuit_lib.port_prefix(output_ports[0]) << " ";
|
||||||
|
fp << circuit_lib.port_prefix(input_ports[0]) << " ";
|
||||||
|
fp << "LGND ";
|
||||||
|
fp << "LGND ";
|
||||||
|
fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX;
|
||||||
|
}
|
||||||
|
|
||||||
|
print_spice_subckt_end(fp, module_manager.module_name(module_id));
|
||||||
|
|
||||||
|
return CMD_EXEC_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************
|
||||||
|
* Generate the SPICE netlist for essential gates:
|
||||||
|
* - inverters and their templates
|
||||||
|
* - buffers and their templates
|
||||||
|
* - pass-transistor or transmission gates
|
||||||
|
* - logic gates
|
||||||
|
***********************************************/
|
||||||
|
int print_spice_essential_gates(NetlistManager& netlist_manager,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const TechnologyLibrary& tech_lib,
|
||||||
|
const std::map<CircuitModelId, TechnologyModelId>& circuit_tech_binding,
|
||||||
|
const std::string& submodule_dir) {
|
||||||
|
std::string spice_fname = submodule_dir + std::string(ESSENTIALS_SPICE_FILE_NAME);
|
||||||
|
|
||||||
|
std::fstream fp;
|
||||||
|
|
||||||
|
/* Create the file stream */
|
||||||
|
fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
|
||||||
|
/* Check if the file stream if valid or not */
|
||||||
|
check_file_stream(spice_fname.c_str(), fp);
|
||||||
|
|
||||||
|
/* Create file */
|
||||||
|
VTR_LOG("Generating SPICE netlist '%s' for transistor wrappers...",
|
||||||
|
spice_fname.c_str());
|
||||||
|
|
||||||
|
int status = CMD_EXEC_SUCCESS;
|
||||||
|
|
||||||
|
/* Iterate over the circuit models */
|
||||||
|
for (const CircuitModelId& circuit_model : circuit_lib.models()) {
|
||||||
|
/* Bypass models require extern netlists */
|
||||||
|
if (true == circuit_lib.model_circuit_netlist(circuit_model).empty()) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Spot module id */
|
||||||
|
const ModuleId& module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
|
||||||
|
|
||||||
|
TechnologyModelId tech_model;
|
||||||
|
/* Focus on inverter/buffer/pass-gate/logic gates only */
|
||||||
|
if ( (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model))
|
||||||
|
|| (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model))
|
||||||
|
|| (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model))) {
|
||||||
|
auto result = circuit_tech_binding.find(circuit_model);
|
||||||
|
if (result == circuit_tech_binding.end()) {
|
||||||
|
VTR_LOGF_ERROR(__FILE__, __LINE__,
|
||||||
|
"Unable to find technology binding for circuit model '%s'!\n",
|
||||||
|
circuit_lib.model_name(circuit_model).c_str());
|
||||||
|
return CMD_EXEC_FATAL_ERROR;
|
||||||
|
}
|
||||||
|
/* Valid technology binding. Assign techology model */
|
||||||
|
tech_model = result->second;
|
||||||
|
/* Ensure we have a valid technology model */
|
||||||
|
VTR_ASSERT(true == tech_lib.valid_model_id(tech_model));
|
||||||
|
VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == tech_lib.model_type(tech_model));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Now branch on netlist writing */
|
||||||
|
if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
|
||||||
|
if (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) {
|
||||||
|
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
|
||||||
|
status = print_spice_inverter_subckt(fp,
|
||||||
|
module_manager, module_id,
|
||||||
|
circuit_lib, circuit_model,
|
||||||
|
tech_lib, tech_model);
|
||||||
|
} else {
|
||||||
|
VTR_ASSERT(CIRCUIT_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model));
|
||||||
|
}
|
||||||
|
|
||||||
|
if (CMD_EXEC_FATAL_ERROR == status) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Finish, go to the next */
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Close file handler*/
|
||||||
|
fp.close();
|
||||||
|
|
||||||
|
/* Add fname to the netlist name list */
|
||||||
|
NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
|
||||||
|
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
|
||||||
|
netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
|
||||||
|
|
||||||
|
VTR_LOG("Done\n");
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
} /* end namespace openfpga */
|
} /* end namespace openfpga */
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,10 @@
|
||||||
* Include header files that are required by function declaration
|
* Include header files that are required by function declaration
|
||||||
*******************************************************************/
|
*******************************************************************/
|
||||||
#include <string>
|
#include <string>
|
||||||
|
#include <map>
|
||||||
#include "netlist_manager.h"
|
#include "netlist_manager.h"
|
||||||
|
#include "module_manager.h"
|
||||||
|
#include "circuit_library.h"
|
||||||
#include "technology_library.h"
|
#include "technology_library.h"
|
||||||
|
|
||||||
/********************************************************************
|
/********************************************************************
|
||||||
|
|
@ -19,6 +22,13 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
|
||||||
const TechnologyLibrary& tech_lib,
|
const TechnologyLibrary& tech_lib,
|
||||||
const std::string& submodule_dir);
|
const std::string& submodule_dir);
|
||||||
|
|
||||||
|
int print_spice_essential_gates(NetlistManager& netlist_manager,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const TechnologyLibrary& tech_lib,
|
||||||
|
const std::map<CircuitModelId, TechnologyModelId>& circuit_tech_binding,
|
||||||
|
const std::string& submodule_dir);
|
||||||
|
|
||||||
} /* end namespace openfpga */
|
} /* end namespace openfpga */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -28,15 +28,23 @@ namespace openfpga {
|
||||||
* 6. TODO: Configuration memory blocks
|
* 6. TODO: Configuration memory blocks
|
||||||
********************************************************************/
|
********************************************************************/
|
||||||
int print_spice_submodule(NetlistManager& netlist_manager,
|
int print_spice_submodule(NetlistManager& netlist_manager,
|
||||||
const TechnologyLibrary& tech_lib,
|
const ModuleManager& module_manager,
|
||||||
|
const Arch& openfpga_arch,
|
||||||
const std::string& submodule_dir) {
|
const std::string& submodule_dir) {
|
||||||
|
|
||||||
int status = CMD_EXEC_SUCCESS;
|
int status = CMD_EXEC_SUCCESS;
|
||||||
|
|
||||||
status = print_spice_transistor_wrapper(netlist_manager,
|
status = print_spice_transistor_wrapper(netlist_manager,
|
||||||
tech_lib,
|
openfpga_arch.tech_lib,
|
||||||
submodule_dir);
|
submodule_dir);
|
||||||
|
|
||||||
|
status = print_spice_essential_gates(netlist_manager,
|
||||||
|
module_manager,
|
||||||
|
openfpga_arch.circuit_lib,
|
||||||
|
openfpga_arch.tech_lib,
|
||||||
|
openfpga_arch.circuit_tech_binding,
|
||||||
|
submodule_dir);
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,8 @@
|
||||||
* Include header files that are required by function declaration
|
* Include header files that are required by function declaration
|
||||||
*******************************************************************/
|
*******************************************************************/
|
||||||
#include "netlist_manager.h"
|
#include "netlist_manager.h"
|
||||||
#include "technology_library.h"
|
#include "module_manager.h"
|
||||||
|
#include "openfpga_arch.h"
|
||||||
|
|
||||||
/********************************************************************
|
/********************************************************************
|
||||||
* Function declaration
|
* Function declaration
|
||||||
|
|
@ -15,7 +16,8 @@
|
||||||
namespace openfpga {
|
namespace openfpga {
|
||||||
|
|
||||||
int print_spice_submodule(NetlistManager& netlist_manager,
|
int print_spice_submodule(NetlistManager& netlist_manager,
|
||||||
const TechnologyLibrary& tech_lib,
|
const ModuleManager& module_manager,
|
||||||
|
const Arch& openfpga_arch,
|
||||||
const std::string& submodule_dir);
|
const std::string& submodule_dir);
|
||||||
|
|
||||||
} /* end namespace openfpga */
|
} /* end namespace openfpga */
|
||||||
|
|
|
||||||
|
|
@ -1154,17 +1154,18 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
|
||||||
/* Attention: when the fast configuration is enabled, we will start from the first bit '1'
|
/* Attention: when the fast configuration is enabled, we will start from the first bit '1'
|
||||||
* This requires a reset signal (as we forced in the first clock cycle)
|
* This requires a reset signal (as we forced in the first clock cycle)
|
||||||
*/
|
*/
|
||||||
bool first_bit_one = false;
|
bool start_config = false;
|
||||||
for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
|
for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
|
||||||
if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
|
if ( (false == start_config)
|
||||||
first_bit_one = true;
|
&& (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) {
|
||||||
|
start_config = true;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* In fast configuration mode, we do not output anything
|
/* In fast configuration mode, we do not output anything
|
||||||
* until we have to (the first bit '1' detected)
|
* until we have to (the first bit '1' detected)
|
||||||
*/
|
*/
|
||||||
if ( (true == fast_configuration)
|
if ( (true == fast_configuration)
|
||||||
&& (false == first_bit_one)) {
|
&& (false == start_config)) {
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,81 @@
|
||||||
|
module FSM_hour(
|
||||||
|
input wire rst,
|
||||||
|
input wire clk,
|
||||||
|
input wire [5:0] hour_in,
|
||||||
|
input wire hour_in_load,
|
||||||
|
input wire [5:0] min_count,
|
||||||
|
input wire [5:0] sec_count,
|
||||||
|
output reg [5:0] hour_out);
|
||||||
|
|
||||||
|
reg [2:0] ps, ns;
|
||||||
|
wire [5:0] hour_data_add;
|
||||||
|
reg [5:0] hour_data;
|
||||||
|
reg [5:0] hour_ps, hour_ns;
|
||||||
|
reg [1:0] hour_sel;
|
||||||
|
wire hour_count;
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst) ps <= 3'd0;
|
||||||
|
else ps <= ns;
|
||||||
|
end
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst) hour_ps <= 6'd0;
|
||||||
|
else hour_ps <= hour_ns;
|
||||||
|
end
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
hour_sel = 2'd0;
|
||||||
|
case(ps)
|
||||||
|
3'd0: begin
|
||||||
|
ns = 3'd1;
|
||||||
|
end
|
||||||
|
3'd1: begin
|
||||||
|
if(hour_in_load) begin
|
||||||
|
hour_sel = 2'd1;
|
||||||
|
hour_out = hour_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
hour_ns = hour_data;
|
||||||
|
end
|
||||||
|
else ns = 3'd1;
|
||||||
|
end
|
||||||
|
3'd2: begin
|
||||||
|
if(hour_count == 1'd1) begin
|
||||||
|
if(hour_data == 6'd59) begin
|
||||||
|
hour_out = hour_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
hour_ns = 6'd0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
hour_out = hour_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
hour_ns = hour_data_add;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
hour_out = hour_data;
|
||||||
|
hour_ns = hour_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
ns = 3'd0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
assign hour_data_add = hour_data + 1;
|
||||||
|
assign hour_count = ((sec_count == 6'd59)&&(min_count == 6'd59)) ? 1'd1 : 1'd0;
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
case(hour_sel)
|
||||||
|
2'd0: hour_data = hour_ps;
|
||||||
|
2'd1: hour_data = hour_in;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,80 @@
|
||||||
|
module FSM_minute(
|
||||||
|
input wire rst,
|
||||||
|
input wire clk,
|
||||||
|
input wire [5:0] min_in,
|
||||||
|
input wire min_in_load,
|
||||||
|
input wire [5:0] sec_count,
|
||||||
|
output reg [5:0] min_out);
|
||||||
|
|
||||||
|
reg [2:0] ps, ns;
|
||||||
|
wire [5:0] min_data_add;
|
||||||
|
reg [5:0] min_data;
|
||||||
|
reg [5:0] min_ps, min_ns;
|
||||||
|
reg [1:0] min_sel;
|
||||||
|
wire min_count;
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst) ps <= 3'd0;
|
||||||
|
else ps <= ns;
|
||||||
|
end
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst) min_ps <= 6'd0;
|
||||||
|
else min_ps <= min_ns;
|
||||||
|
end
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
min_sel = 2'd0;
|
||||||
|
case(ps)
|
||||||
|
3'd0: begin
|
||||||
|
ns = 3'd1;
|
||||||
|
end
|
||||||
|
3'd1: begin
|
||||||
|
if(min_in_load) begin
|
||||||
|
min_sel = 2'd1;
|
||||||
|
min_out = min_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
min_ns = min_data;
|
||||||
|
end
|
||||||
|
else ns = 3'd1;
|
||||||
|
end
|
||||||
|
3'd2: begin
|
||||||
|
if(min_count == 1'd1) begin
|
||||||
|
if(min_data == 6'd59) begin
|
||||||
|
min_out = min_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
min_ns = 6'd0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
min_out = min_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
min_ns = min_data_add;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
min_out = min_data;
|
||||||
|
min_ns = min_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
ns = 3'd0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
assign min_data_add = min_data + 1;
|
||||||
|
assign min_count = (sec_count == 6'd59) ? 1'd1 : 1'd0;
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
case(min_sel)
|
||||||
|
2'd0: min_data = min_ps;
|
||||||
|
2'd1: min_data = min_in;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,70 @@
|
||||||
|
module FSM_second(
|
||||||
|
input wire rst,
|
||||||
|
input wire clk,
|
||||||
|
input wire [5:0] sec_in,
|
||||||
|
input wire sec_in_load,
|
||||||
|
output reg [5:0] sec_out);
|
||||||
|
|
||||||
|
reg [2:0] ps, ns;
|
||||||
|
wire [5:0] sec_data_add;
|
||||||
|
reg [5:0] sec_data;
|
||||||
|
reg [5:0] sec_ps, sec_ns;
|
||||||
|
reg [1:0] sec_sel;
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst) ps <= 3'd0;
|
||||||
|
else ps <= ns;
|
||||||
|
end
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst) sec_ps <= 6'd0;
|
||||||
|
else sec_ps <= sec_ns;
|
||||||
|
end
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
sec_sel = 2'd0;
|
||||||
|
case(ps)
|
||||||
|
3'd0: begin
|
||||||
|
ns = 3'd1;
|
||||||
|
end
|
||||||
|
3'd1: begin
|
||||||
|
if(sec_in_load) begin
|
||||||
|
sec_sel = 2'd1;
|
||||||
|
sec_out = sec_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
sec_ns = sec_data_add;
|
||||||
|
end
|
||||||
|
else ns = 3'd1;
|
||||||
|
end
|
||||||
|
3'd2: begin
|
||||||
|
if(sec_data == 6'd59) begin
|
||||||
|
sec_out = sec_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
sec_ns = 6'd0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
sec_out = sec_data;
|
||||||
|
ns = 3'd2;
|
||||||
|
sec_ns = sec_data_add;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
ns = 3'd0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
assign sec_data_add = sec_data + 1;
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
case(sec_sel)
|
||||||
|
2'd0: sec_data = sec_ps;
|
||||||
|
2'd1: sec_data = sec_in;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
module FSM_three_tb;
|
||||||
|
|
||||||
|
reg rst;
|
||||||
|
reg clk;
|
||||||
|
reg [5:0] sec_in, min_in, hour_in;
|
||||||
|
reg load_in;
|
||||||
|
wire [5:0] sec_out, min_out, hour_out;
|
||||||
|
|
||||||
|
FSM_top FSM_1(
|
||||||
|
.rst(rst),
|
||||||
|
.clk(clk),
|
||||||
|
.sec_in(sec_in),
|
||||||
|
.load_in(load_in),
|
||||||
|
.sec_out(sec_out),
|
||||||
|
.min_in(min_in),
|
||||||
|
.min_out(min_out),
|
||||||
|
.hour_in(hour_in),
|
||||||
|
.hour_out(hour_out));
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
#0 rst = 1'd1; clk = 1'd0; load_in = 1'd1; sec_in = 6'd33; min_in = 6'd14; hour_in = 6'd5;
|
||||||
|
#100 rst = 1'd0;
|
||||||
|
#50 load_in = 1'd0;
|
||||||
|
end
|
||||||
|
|
||||||
|
always begin
|
||||||
|
#10 clk = ~clk;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
#100000 $stop;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,37 @@
|
||||||
|
module FSM_top(
|
||||||
|
input wire rst,
|
||||||
|
input wire clk,
|
||||||
|
input wire load_in,
|
||||||
|
input wire [5:0] sec_in,
|
||||||
|
input wire [5:0] min_in,
|
||||||
|
input wire [5:0] hour_in,
|
||||||
|
output wire [5:0] sec_out,
|
||||||
|
output wire [5:0] min_out,
|
||||||
|
output wire [5:0] hour_out
|
||||||
|
);
|
||||||
|
|
||||||
|
FSM_second FSM_sec(
|
||||||
|
.rst(rst),
|
||||||
|
.clk(clk),
|
||||||
|
.sec_in(sec_in),
|
||||||
|
.sec_in_load(load_in),
|
||||||
|
.sec_out(sec_out));
|
||||||
|
|
||||||
|
FSM_minute FSM_min(
|
||||||
|
.rst(rst),
|
||||||
|
.clk(clk),
|
||||||
|
.min_in(min_in),
|
||||||
|
.min_in_load(load_in),
|
||||||
|
.sec_count(sec_out),
|
||||||
|
.min_out(min_out));
|
||||||
|
|
||||||
|
FSM_hour FSM_hr(
|
||||||
|
.rst(rst),
|
||||||
|
.clk(clk),
|
||||||
|
.hour_in(hour_in),
|
||||||
|
.hour_in_load(load_in),
|
||||||
|
.min_count(min_out),
|
||||||
|
.hour_out(hour_out),
|
||||||
|
.sec_count(sec_out));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
|
||||||
|
|
||||||
|
output zero_flag_out;
|
||||||
|
output reg [7:0]alu_out;
|
||||||
|
input [7:0]Reg_Y_in,Bus_1_in;
|
||||||
|
input [7:0]IR_code;
|
||||||
|
|
||||||
|
wire [3:0]opcode=IR_code[7:4];
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
case(opcode)
|
||||||
|
1: alu_out=Reg_Y_in+Bus_1_in;
|
||||||
|
2: alu_out=Bus_1_in+~(Reg_Y_in)+1;
|
||||||
|
3: alu_out=Reg_Y_in&(Bus_1_in);
|
||||||
|
4: alu_out=~(Bus_1_in);
|
||||||
|
default:alu_out=8'b0;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
assign zero_flag_out=~|alu_out;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,211 @@
|
||||||
|
module Controller(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,
|
||||||
|
Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,write,
|
||||||
|
zero,instruction,nclk,rst);
|
||||||
|
|
||||||
|
|
||||||
|
//狀態
|
||||||
|
parameter S_idle=0,S_fet1=1,S_fet2=2,S_dec=3,
|
||||||
|
S_ex1=4,S_rd1=5,S_rd2=6,S_wr1=7,S_wr2=8,
|
||||||
|
S_br1=9,S_br2=10,S_halt=11;
|
||||||
|
//指令
|
||||||
|
parameter NOP=0,ADD=1,SUB=2,AND=3,NOT=4,
|
||||||
|
RD=5,WR=6,BR=7,BRZ=8;
|
||||||
|
|
||||||
|
|
||||||
|
output reg L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,
|
||||||
|
L_IR,L_ADD_R,L_R_Y,L_R_Z,write;
|
||||||
|
output reg[2:0]Sel_Bus1;
|
||||||
|
output reg [1:0]Sel_Bus2;
|
||||||
|
|
||||||
|
input zero,nclk,rst;
|
||||||
|
input [7:0]instruction;
|
||||||
|
|
||||||
|
reg [15:0]Con_out;
|
||||||
|
reg [3:0]PS,NS;
|
||||||
|
reg err_flag;
|
||||||
|
|
||||||
|
wire [1:0]src=instruction[3:2];
|
||||||
|
wire [1:0]dest=instruction[1:0];
|
||||||
|
wire [3:0]opcode=instruction[7:4];
|
||||||
|
|
||||||
|
always@(posedge nclk)
|
||||||
|
begin
|
||||||
|
if(rst==1)PS<=0;
|
||||||
|
else PS<=NS;
|
||||||
|
end
|
||||||
|
|
||||||
|
always@(PS,opcode,src,dest,zero)
|
||||||
|
begin
|
||||||
|
L_R0=0;
|
||||||
|
L_R1=0;
|
||||||
|
L_R2=0;
|
||||||
|
L_R3=0;
|
||||||
|
L_PC=0;
|
||||||
|
Inc_PC=0;
|
||||||
|
Sel_Bus1=0;
|
||||||
|
L_IR=0;
|
||||||
|
L_ADD_R=0;
|
||||||
|
L_R_Y=0;
|
||||||
|
L_R_Z=0;
|
||||||
|
Sel_Bus2=0;
|
||||||
|
write=0;
|
||||||
|
err_flag=0;
|
||||||
|
case(PS)
|
||||||
|
S_idle: NS=S_fet1;
|
||||||
|
|
||||||
|
S_fet1: begin
|
||||||
|
NS=S_fet2;
|
||||||
|
Sel_Bus1=3'b100;//Sel_PC
|
||||||
|
Sel_Bus2=2'b01;//Sel_Bus1
|
||||||
|
L_ADD_R=1;
|
||||||
|
end
|
||||||
|
|
||||||
|
S_fet2: begin
|
||||||
|
NS=S_dec;
|
||||||
|
Sel_Bus2=2'b10;//Sel_Mem
|
||||||
|
L_IR=1;
|
||||||
|
Inc_PC=1;
|
||||||
|
end
|
||||||
|
|
||||||
|
S_dec: begin
|
||||||
|
case(opcode)
|
||||||
|
NOP:NS=S_fet1;
|
||||||
|
ADD,SUB,AND:begin
|
||||||
|
NS=S_ex1;
|
||||||
|
Sel_Bus2=2'b01;//Sel_Bus1
|
||||||
|
L_R_Y=1;
|
||||||
|
case(src)
|
||||||
|
0: Sel_Bus1=3'b000;//R0
|
||||||
|
1: Sel_Bus1=3'b001;//R1
|
||||||
|
2: Sel_Bus1=3'b010;//R2
|
||||||
|
3: Sel_Bus1=3'b011;//R3
|
||||||
|
default err_flag=1;
|
||||||
|
endcase
|
||||||
|
end//ADD,SUB,AND
|
||||||
|
|
||||||
|
NOT:begin
|
||||||
|
NS=S_fet1;
|
||||||
|
L_R_Z=1;
|
||||||
|
Sel_Bus2=2'b00;//Sel_ALU
|
||||||
|
case(src)
|
||||||
|
0: Sel_Bus1=3'b000;//R0
|
||||||
|
1: Sel_Bus1=3'b001;//R1
|
||||||
|
2: Sel_Bus1=3'b010;//R2
|
||||||
|
3: Sel_Bus1=3'b011;//R3
|
||||||
|
default err_flag=1;
|
||||||
|
endcase
|
||||||
|
case(dest)
|
||||||
|
0: L_R0=1;
|
||||||
|
1: L_R1=1;
|
||||||
|
2: L_R2=1;
|
||||||
|
3: L_R3=1;
|
||||||
|
default err_flag=1;
|
||||||
|
endcase
|
||||||
|
end//NOT
|
||||||
|
|
||||||
|
RD: begin
|
||||||
|
NS=S_rd1;
|
||||||
|
Sel_Bus1=3'b100;//Sel_PC
|
||||||
|
Sel_Bus2=3'b001;//Sel_Bus1
|
||||||
|
L_ADD_R=1;
|
||||||
|
end//RD
|
||||||
|
|
||||||
|
WR: begin
|
||||||
|
NS=S_wr1;
|
||||||
|
Sel_Bus1=3'b100;//Sel_PC
|
||||||
|
Sel_Bus2=3'b001;//Sel_Bus1
|
||||||
|
L_ADD_R=1;
|
||||||
|
end//WR
|
||||||
|
|
||||||
|
BR: begin
|
||||||
|
NS=S_br1;
|
||||||
|
Sel_Bus1=3'b100;//Sel_PC
|
||||||
|
Sel_Bus2=3'b001;//Sel_Bus1
|
||||||
|
L_ADD_R=1;
|
||||||
|
end//BR
|
||||||
|
|
||||||
|
BRZ:begin
|
||||||
|
if(zero==1)begin
|
||||||
|
NS=S_br1;
|
||||||
|
Sel_Bus1=3'b100;//Sel_PC
|
||||||
|
Sel_Bus2=3'b001;//Sel_Bus1
|
||||||
|
L_ADD_R=1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
NS=S_fet1;
|
||||||
|
Inc_PC=1;
|
||||||
|
end
|
||||||
|
end//BRZ
|
||||||
|
|
||||||
|
default NS=S_halt;
|
||||||
|
|
||||||
|
endcase//opcode
|
||||||
|
end
|
||||||
|
|
||||||
|
S_ex1: begin
|
||||||
|
NS=S_fet1;
|
||||||
|
L_R_Z=1;
|
||||||
|
Sel_Bus2=2'b00;//Sel_ALU
|
||||||
|
case(dest)
|
||||||
|
0: begin Sel_Bus1=3'b000;L_R0=1;end
|
||||||
|
1: begin Sel_Bus1=3'b001;L_R1=1;end
|
||||||
|
2: begin Sel_Bus1=3'b010;L_R2=1;end
|
||||||
|
3: begin Sel_Bus1=3'b011;L_R3=1;end
|
||||||
|
default err_flag=1;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
S_rd1: begin
|
||||||
|
NS=S_rd2;
|
||||||
|
Inc_PC=1;
|
||||||
|
Sel_Bus2=2'b10;//Sel_Mem
|
||||||
|
L_ADD_R=1;
|
||||||
|
end
|
||||||
|
|
||||||
|
S_wr1: begin
|
||||||
|
NS=S_wr2;
|
||||||
|
Inc_PC=1;
|
||||||
|
Sel_Bus2=2'b10;//Sel_Mem
|
||||||
|
L_ADD_R=1;
|
||||||
|
end
|
||||||
|
|
||||||
|
S_rd2: begin
|
||||||
|
NS=S_fet1;
|
||||||
|
Sel_Bus2=2'b10;//Sel_Mem
|
||||||
|
case(dest)
|
||||||
|
0: L_R0=1;
|
||||||
|
1: L_R1=1;
|
||||||
|
2: L_R2=1;
|
||||||
|
3: L_R3=1;
|
||||||
|
default err_flag=1;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
S_wr2: begin
|
||||||
|
NS=S_fet1;
|
||||||
|
write=1;
|
||||||
|
case(src)
|
||||||
|
0: Sel_Bus1=3'b000;//R0
|
||||||
|
1: Sel_Bus1=3'b001;//R1
|
||||||
|
2: Sel_Bus1=3'b010;//R2
|
||||||
|
3: Sel_Bus1=3'b011;//R3
|
||||||
|
default err_flag=1;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
S_br1: begin
|
||||||
|
NS=S_br2;
|
||||||
|
Sel_Bus2=2'b10;//Sel_Mem
|
||||||
|
L_ADD_R=1;
|
||||||
|
end
|
||||||
|
|
||||||
|
S_br2: begin
|
||||||
|
NS=S_fet1;
|
||||||
|
Sel_Bus2=2'b10;//Sel_Mem
|
||||||
|
L_PC=1;
|
||||||
|
end
|
||||||
|
S_halt: NS=S_halt;
|
||||||
|
default NS=S_idle;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,13 @@
|
||||||
|
module IR(IR_out,IR_in,load,clk,rst);
|
||||||
|
|
||||||
|
output reg [7:0]IR_out;
|
||||||
|
input [7:0]IR_in;
|
||||||
|
input load,clk,rst;
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst==1)IR_out<=8'b0;
|
||||||
|
else if(load==1)IR_out<=IR_in;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,61 @@
|
||||||
|
module Memory(Data_out,Address);
|
||||||
|
|
||||||
|
output [7:0]Data_out;
|
||||||
|
input [7:0]Address;
|
||||||
|
|
||||||
|
reg [7:0]mem[255:0];
|
||||||
|
assign Data_out=mem[Address];
|
||||||
|
|
||||||
|
always@(Address)
|
||||||
|
begin
|
||||||
|
case(Address)
|
||||||
|
//opcode_src_dest
|
||||||
|
//NOP
|
||||||
|
0: mem[Address]=8'b0000_00_00;
|
||||||
|
|
||||||
|
//rd 00 10 //Read MEM[130] to R2
|
||||||
|
1: mem[Address]=8'b0101_00_10; //Instruction
|
||||||
|
2: mem[Address]=130; //Address
|
||||||
|
|
||||||
|
//rd 00 11 //Read MEM[131] to R3
|
||||||
|
3: mem[Address]=8'b0101_00_11; //Instruction
|
||||||
|
4: mem[Address]=131; //Address
|
||||||
|
|
||||||
|
//rd 00 01 //Read MEM[128] to R1
|
||||||
|
5: mem[Address]=8'b0101_00_01; //Instruction
|
||||||
|
6: mem[Address]=128; //Address
|
||||||
|
|
||||||
|
//rd 00 00 //Read MEM[129] to R0
|
||||||
|
7: mem[Address]=8'b0101_00_00; //Instruction
|
||||||
|
8: mem[Address]=129; //Address
|
||||||
|
|
||||||
|
//Sub 00 01 //Sub R1-R0 to R1
|
||||||
|
9: mem[Address]=8'b0010_00_01; //Instruction
|
||||||
|
|
||||||
|
//BRZ 00 00
|
||||||
|
10: mem[Address]=8'b1000_00_00; //Instruction
|
||||||
|
11: mem[Address]=134; //Address
|
||||||
|
|
||||||
|
//Add 10 11 //Add R2+R3 to R3
|
||||||
|
12: mem[Address]=8'b00011011;
|
||||||
|
|
||||||
|
//BR
|
||||||
|
13: mem[Address]=8'b01110011; //Instruction
|
||||||
|
14: mem[Address]=140; //Address
|
||||||
|
|
||||||
|
128:mem[Address]=6;
|
||||||
|
129:mem[Address]=1;
|
||||||
|
130:mem[Address]=2;
|
||||||
|
131:mem[Address]=0;
|
||||||
|
134:mem[Address]=139; //Address
|
||||||
|
135:mem[Address]=0;
|
||||||
|
//HAL
|
||||||
|
139:mem[Address]=8'b1111_00_00; //Instruction
|
||||||
|
140:mem[Address]=9; //Address
|
||||||
|
default mem[Address]=8'bx;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
module Mux_31(Y,A0,A1,A2,sel);
|
||||||
|
|
||||||
|
output [7:0]Y;
|
||||||
|
input [7:0]A2,A1,A0;
|
||||||
|
input [1:0]sel;
|
||||||
|
|
||||||
|
reg [7:0]Y;
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
case(sel)
|
||||||
|
0: Y=A0;
|
||||||
|
1: Y=A1;
|
||||||
|
2: Y=A2;
|
||||||
|
default:Y=8'bz;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
@ -0,0 +1,22 @@
|
||||||
|
module Mux_51(Y,A0,A1,A2,A3,A4,sel);
|
||||||
|
|
||||||
|
output [7:0]Y;
|
||||||
|
input [7:0]A4,A3,A2,A1,A0;
|
||||||
|
input [2:0]sel;
|
||||||
|
|
||||||
|
reg [7:0]Y;
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
case(sel)
|
||||||
|
0: Y=A0;
|
||||||
|
1: Y=A1;
|
||||||
|
2: Y=A2;
|
||||||
|
3: Y=A3;
|
||||||
|
4: Y=A4;
|
||||||
|
default:Y=8'bx;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
@ -0,0 +1,17 @@
|
||||||
|
module PC(PC_out,PC_in,load,inc,clk,rst);
|
||||||
|
|
||||||
|
output [7:0]PC_out;
|
||||||
|
input [7:0]PC_in;
|
||||||
|
input load,inc,clk,rst;
|
||||||
|
|
||||||
|
reg [7:0]PC_out;
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst==1)PC_out<=8'b0;
|
||||||
|
else if(load==1)PC_out<=PC_in;
|
||||||
|
else if(inc==1)PC_out<=PC_out+8'b00000001;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);
|
||||||
|
|
||||||
|
output [7:0]bus_1_out;
|
||||||
|
input clk,rst;
|
||||||
|
output [7:0]Reg_R0_out;
|
||||||
|
output [7:0]Reg_R1_out;
|
||||||
|
output [7:0]Reg_R2_out;
|
||||||
|
output [7:0]Reg_R3_out;
|
||||||
|
|
||||||
|
wire [7:0]bus_1_out,MEMAddress;
|
||||||
|
wire clk,rst;
|
||||||
|
wire [7:0]MEMdataout;
|
||||||
|
wire [7:0]Reg_R0_out;
|
||||||
|
wire [7:0]Reg_R1_out;
|
||||||
|
wire [7:0]Reg_R2_out;
|
||||||
|
wire [7:0]Reg_R3_out;
|
||||||
|
|
||||||
|
|
||||||
|
RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);
|
||||||
|
|
||||||
|
Memory MEM(MEMdataout,MEMAddress);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,48 @@
|
||||||
|
module RISC_core_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);
|
||||||
|
|
||||||
|
output [7:0]bus_1_out,MEMAddress;
|
||||||
|
input clk,rst;
|
||||||
|
input [7:0]MEMdataout;
|
||||||
|
output [7:0]Reg_R0_out;
|
||||||
|
output [7:0]Reg_R1_out;
|
||||||
|
output [7:0]Reg_R2_out;
|
||||||
|
output [7:0]Reg_R3_out;
|
||||||
|
|
||||||
|
wire [7:0]BUS_2,BUS_1,MEMAddress;
|
||||||
|
wire [7:0]alu_out;
|
||||||
|
wire [7:0]MEMdataout;
|
||||||
|
wire [7:0]Reg_Y_out,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out;
|
||||||
|
wire [7:0]IR_out;
|
||||||
|
wire zero_flag_out;
|
||||||
|
wire [2:0]Sel_Bus1;
|
||||||
|
wire [1:0]Sel_Bus2;
|
||||||
|
wire L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,L_IR,L_ADD_R,L_R_Y,L_R_Z,MEMwrite,zero;
|
||||||
|
|
||||||
|
assign bus_1_out=BUS_1;
|
||||||
|
assign bus_2_out=BUS_2;
|
||||||
|
|
||||||
|
Controller CON(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,MEMwrite,zero,IR_out,clk,rst);
|
||||||
|
//module PC(PC_out,PC_in,load,inc,clk,rst);
|
||||||
|
PC Program_Counter(PC_out,BUS_2,L_PC,Inc_PC,clk,rst);
|
||||||
|
//module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
|
||||||
|
ALU Arithmetic_Logic_Unit(zero_flag_out,alu_out,Reg_Y_out,BUS_1,IR_out);
|
||||||
|
//module Memory(Data_out,Data_in,MEMAddress,clk,MEMwrite);
|
||||||
|
//Memory MEM(MEMdataout,BUS_1,MEMAddress,clk,MEMwrite);
|
||||||
|
//module Mux_31(Y,A0,A1,A2,sel);
|
||||||
|
Mux_31 Mux31(BUS_2,alu_out,BUS_1,MEMdataout,Sel_Bus2);
|
||||||
|
//module Reg_1bit(Q,D,load,clk,rst);
|
||||||
|
Reg_1bit Reg_Z(zero,zero_flag_out,L_R_Z,clk,rst);
|
||||||
|
//module Reg_8bit(Q,D,load,clk,rst);
|
||||||
|
Reg_8bit Reg_Y(Reg_Y_out,BUS_2,L_R_Y,clk,rst);
|
||||||
|
Reg_8bit Add_R(MEMAddress,BUS_2,L_ADD_R,clk,rst);
|
||||||
|
//R0~R3
|
||||||
|
Reg_8bit Reg_R0(Reg_R0_out,BUS_2,L_R0,clk,rst);
|
||||||
|
Reg_8bit Reg_R1(Reg_R1_out,BUS_2,L_R1,clk,rst);
|
||||||
|
Reg_8bit Reg_R2(Reg_R2_out,BUS_2,L_R2,clk,rst);
|
||||||
|
Reg_8bit Reg_R3(Reg_R3_out,BUS_2,L_R3,clk,rst);
|
||||||
|
//module Mux_51(Y,A0,A1,A2,A3,A4,sel);
|
||||||
|
Mux_51 Mux51(BUS_1,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out,Sel_Bus1);
|
||||||
|
//module IR(IR_out,IR_in,load,clk,rst);
|
||||||
|
IR Instruction_Register(IR_out,BUS_2,L_IR,clk,rst);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,53 @@
|
||||||
|
`timescale 1ns/1ns
|
||||||
|
|
||||||
|
module RISC_testbench;
|
||||||
|
|
||||||
|
wire [7:0]bus_1_out;
|
||||||
|
reg clk,rst;
|
||||||
|
wire [7:0]Reg_R0_out;
|
||||||
|
wire [7:0]Reg_R1_out;
|
||||||
|
wire [7:0]Reg_R2_out;
|
||||||
|
wire [7:0]Reg_R3_out;
|
||||||
|
|
||||||
|
/* wire [7:0]MEMAddress;
|
||||||
|
wire [7:0]MEMdataout;
|
||||||
|
wire MEMwrite; */
|
||||||
|
|
||||||
|
/* assign MEMAddress = top.MEMAddress;
|
||||||
|
assign MEMdataout = top.MEMdataout;
|
||||||
|
assign MEMwrite = top.MEMwrite; */
|
||||||
|
|
||||||
|
RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);
|
||||||
|
|
||||||
|
always#20 clk=~clk;
|
||||||
|
|
||||||
|
initial
|
||||||
|
begin
|
||||||
|
clk=0;rst=1;
|
||||||
|
#30 rst=0;
|
||||||
|
#6000 $stop;
|
||||||
|
end
|
||||||
|
|
||||||
|
/* //----------
|
||||||
|
|
||||||
|
integer fp;
|
||||||
|
initial
|
||||||
|
begin
|
||||||
|
fp = $fopen("RISC_xa.vec");
|
||||||
|
|
||||||
|
$fdisplay(fp, "radix 1 1 44 44 44 44 44 1 44 44");
|
||||||
|
$fdisplay(fp, "vname clk rst Reg_R0_out[[7:0]] Reg_R1_out[[7:0]] Reg_R2_out[[7:0]] Reg_R3_out[[7:0]] bus_1_out[[7:0]] MEMwrite MEMAddress MEMdataout");
|
||||||
|
$fdisplay(fp, " io i i oo oo oo oo oo o oo ii");
|
||||||
|
$fdisplay(fp, "slope 0.3");
|
||||||
|
$fdisplay(fp, " vih 3.3");
|
||||||
|
$fdisplay(fp, " vil 0");
|
||||||
|
$fdisplay(fp, "tunit ns");
|
||||||
|
end
|
||||||
|
always@(clk)
|
||||||
|
begin
|
||||||
|
$fdisplay(fp, "%t %b %b %h %h %h %h %h %b %h %h", $time, clk, rst, Reg_R0_out, Reg_R1_out, Reg_R2_out, Reg_R3_out, bus_1_out, MEMwrite, MEMAddress, MEMdataout);
|
||||||
|
end
|
||||||
|
|
||||||
|
//---------- */
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
module Reg_1bit(Q,D,load,clk,rst);
|
||||||
|
|
||||||
|
output Q;
|
||||||
|
input D;
|
||||||
|
input load,clk,rst;
|
||||||
|
|
||||||
|
reg Q;
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst==1)Q<=0;
|
||||||
|
else if(load==1)Q<=D;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
module Reg_8bit(Q,D,load,clk,rst);
|
||||||
|
|
||||||
|
output [7:0]Q;
|
||||||
|
input [7:0]D;
|
||||||
|
input load,clk,rst;
|
||||||
|
|
||||||
|
reg [7:0]Q;
|
||||||
|
|
||||||
|
always@(posedge clk)
|
||||||
|
begin
|
||||||
|
if(rst==1)Q<=8'b0;
|
||||||
|
else if(load==1)Q<=D;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
module ACC(
|
||||||
|
output [7:0] acc_out1,
|
||||||
|
output [7:0] acc_out2,
|
||||||
|
input [7:0] acc_in,
|
||||||
|
input la_,
|
||||||
|
input clk,
|
||||||
|
input clr_
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [7:0] q;
|
||||||
|
|
||||||
|
always @(posedge clk)
|
||||||
|
if (~clr_) q <= 8'b0;
|
||||||
|
else if(~la_) q <= acc_in;
|
||||||
|
|
||||||
|
assign acc_out1 = q;
|
||||||
|
assign acc_out2 = q;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,13 @@
|
||||||
|
module ADDSUB(
|
||||||
|
output [7:0] ADDSUB_out,
|
||||||
|
input [7:0] ADDSUB_in1,
|
||||||
|
input [7:0] ADDSUB_in2,
|
||||||
|
input su
|
||||||
|
);
|
||||||
|
|
||||||
|
wire [7:0] d;
|
||||||
|
|
||||||
|
assign d = su ? ADDSUB_in1 - ADDSUB_in2 : ADDSUB_in1 + ADDSUB_in2;
|
||||||
|
assign ADDSUB_out = d;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,13 @@
|
||||||
|
module BRegister(
|
||||||
|
output reg [7:0] BRegister_out,
|
||||||
|
input [7:0] BRegister_in,
|
||||||
|
input lb_,
|
||||||
|
input clk,
|
||||||
|
input clr_
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge clk)
|
||||||
|
if(~clr_) BRegister_out <= 8'b0;
|
||||||
|
else if(~lb_) BRegister_out <= BRegister_in;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,119 @@
|
||||||
|
module Controller(
|
||||||
|
output reg [11:0] control_signals,
|
||||||
|
input [3:0] opcode,
|
||||||
|
input clk,
|
||||||
|
input clr_
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [3:0] ps, ns;
|
||||||
|
|
||||||
|
always @(posedge clk)
|
||||||
|
begin
|
||||||
|
if(~clr_) ps <= 4'd0;
|
||||||
|
else ps <= ns;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(*)
|
||||||
|
begin
|
||||||
|
case(ps)
|
||||||
|
0:
|
||||||
|
begin
|
||||||
|
control_signals = 12'h3e3;
|
||||||
|
ns = 4'd1;
|
||||||
|
end
|
||||||
|
|
||||||
|
1: //T1
|
||||||
|
begin
|
||||||
|
control_signals = 12'h5e3;
|
||||||
|
ns = 4'd2;
|
||||||
|
end
|
||||||
|
|
||||||
|
2: //T2
|
||||||
|
begin
|
||||||
|
// control_signals = 12'hbe3;
|
||||||
|
control_signals = 12'h863;
|
||||||
|
ns = 4'd3;
|
||||||
|
end
|
||||||
|
|
||||||
|
3: //T3
|
||||||
|
begin
|
||||||
|
// control_signals = 12'h263;
|
||||||
|
control_signals = 12'h3e3;
|
||||||
|
if(opcode == 4'd0) //LDA
|
||||||
|
ns = 4'd4;
|
||||||
|
else if(opcode == 4'd1) //ADD
|
||||||
|
ns = 4'd6;
|
||||||
|
else if(opcode == 4'd2) //SUB
|
||||||
|
ns = 4'd9;
|
||||||
|
else if(opcode == 4'd14) //OUT
|
||||||
|
ns = 4'd12;
|
||||||
|
else if(opcode == 4'd15) //HLT
|
||||||
|
ns = 4'd13;
|
||||||
|
end
|
||||||
|
|
||||||
|
4: //LDA
|
||||||
|
begin
|
||||||
|
control_signals = 12'h1a3;
|
||||||
|
ns = 4'd5;
|
||||||
|
end
|
||||||
|
|
||||||
|
5: //LDA
|
||||||
|
begin
|
||||||
|
control_signals = 12'h2c3;
|
||||||
|
ns = 4'd1;
|
||||||
|
end
|
||||||
|
|
||||||
|
6: //ADD
|
||||||
|
begin
|
||||||
|
control_signals = 12'h1a3;
|
||||||
|
ns = 4'd7;
|
||||||
|
end
|
||||||
|
|
||||||
|
7: //ADD
|
||||||
|
begin
|
||||||
|
control_signals = 12'h2e1;
|
||||||
|
ns = 4'd8;
|
||||||
|
end
|
||||||
|
|
||||||
|
8: //ADD
|
||||||
|
begin
|
||||||
|
control_signals = 12'h3c7;
|
||||||
|
ns = 4'd1;
|
||||||
|
end
|
||||||
|
|
||||||
|
9: //SUB
|
||||||
|
begin
|
||||||
|
control_signals = 12'h1a3;
|
||||||
|
ns = 4'd10;
|
||||||
|
end
|
||||||
|
|
||||||
|
10: //SUB
|
||||||
|
begin
|
||||||
|
control_signals = 12'h2e1;
|
||||||
|
ns = 4'd11;
|
||||||
|
end
|
||||||
|
|
||||||
|
11: //SUB
|
||||||
|
begin
|
||||||
|
control_signals = 12'h3cf;
|
||||||
|
ns = 4'd1;
|
||||||
|
end
|
||||||
|
|
||||||
|
12: //OUT
|
||||||
|
begin
|
||||||
|
control_signals = 12'h3f2;
|
||||||
|
ns = 4'd1;
|
||||||
|
end
|
||||||
|
|
||||||
|
13: //HLT
|
||||||
|
ns = 4'd13;
|
||||||
|
|
||||||
|
default:
|
||||||
|
begin
|
||||||
|
ns = 4'd0;
|
||||||
|
control_signals = 12'h3e3;
|
||||||
|
end
|
||||||
|
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
module IR(
|
||||||
|
output [7:4] opcode,
|
||||||
|
output [3:0] oprand,
|
||||||
|
input wire [7:0] IR_in,
|
||||||
|
input li_,
|
||||||
|
input clk,
|
||||||
|
input clr_
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [7:0] q;
|
||||||
|
|
||||||
|
always @(posedge clk)
|
||||||
|
begin
|
||||||
|
if(~clr_) q <=8'b0;
|
||||||
|
else if(~li_) q <= IR_in;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign opcode = q[7:4];
|
||||||
|
assign oprand = q[3:0];
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,13 @@
|
||||||
|
module MAR(
|
||||||
|
output reg [3:0] mar_out,
|
||||||
|
input wire [3:0] mar_in,
|
||||||
|
input lm_,
|
||||||
|
input clk,
|
||||||
|
input clr_
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge clk)
|
||||||
|
if(~clr_) mar_out <= 4'b0;
|
||||||
|
else if(~lm_) mar_out <= mar_in;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,13 @@
|
||||||
|
module OutputRegister(
|
||||||
|
output reg [7:0] OutputRegister_out,
|
||||||
|
input [7:0] OutputRegister_in,
|
||||||
|
input lo_,
|
||||||
|
input clk,
|
||||||
|
input clr_
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge clk)
|
||||||
|
if(~clr_) OutputRegister_out <= 8'b0;
|
||||||
|
else if(~lo_) OutputRegister_out <= OutputRegister_in;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
module PC(
|
||||||
|
output reg [3:0] pc_out,
|
||||||
|
input cp,
|
||||||
|
input clk,
|
||||||
|
input clr_
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge clk)
|
||||||
|
begin
|
||||||
|
if(~clr_) pc_out <= 0;
|
||||||
|
else if (cp) pc_out <= pc_out + 1;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
module ROM(
|
||||||
|
output reg [7:0] rom_out,
|
||||||
|
input [3:0] rom_in
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(*)
|
||||||
|
begin
|
||||||
|
rom_out = 8'bx;
|
||||||
|
case(rom_in)
|
||||||
|
4'b0000: rom_out = 8'b0000_1001; //LDA
|
||||||
|
4'b0001: rom_out = 8'b0001_1010; //ADD
|
||||||
|
4'b0010: rom_out = 8'b0001_1011; //ADD
|
||||||
|
4'b0011: rom_out = 8'b0010_1100; //SUB
|
||||||
|
4'b0100: rom_out = 8'b1110_xxxx; //OUT
|
||||||
|
4'b0101: rom_out = 8'b1111_xxxx; //HLT
|
||||||
|
4'b0110: rom_out = 8'bxxxx_xxxx;
|
||||||
|
4'b0111: rom_out = 8'bxxxx_xxxx;
|
||||||
|
4'b1000: rom_out = 8'bxxxx_xxxx;
|
||||||
|
4'b1001: rom_out = 8'b0001_0000;
|
||||||
|
4'b1010: rom_out = 8'b0001_0100;
|
||||||
|
4'b1011: rom_out = 8'b0001_1000;
|
||||||
|
4'b1100: rom_out = 8'b0010_0000;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,100 @@
|
||||||
|
module SAPone(
|
||||||
|
output wire [7:0] SAP_out,
|
||||||
|
output wire [11:0] con,
|
||||||
|
output reg [7:0] bus,
|
||||||
|
input clk,
|
||||||
|
input clr_
|
||||||
|
);
|
||||||
|
|
||||||
|
wire cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_;
|
||||||
|
wire [7:0] acc_out2, BRegister_out, OutputRegister_out;
|
||||||
|
wire [3:0] IR_out, mar_out;
|
||||||
|
wire [4:0] bus_sel;
|
||||||
|
wire [3:0] pc_out, oprand;
|
||||||
|
wire [7:0] rom_out, acc_out1, ADDSUB_out;
|
||||||
|
|
||||||
|
assign {cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_} = con;
|
||||||
|
assign bus_sel = {ep, ce_, ei_, ea, eu};
|
||||||
|
|
||||||
|
always@(*)
|
||||||
|
begin
|
||||||
|
case(bus_sel)
|
||||||
|
5'b11100: bus[3:0] = pc_out;
|
||||||
|
5'b00100: bus[7:0] = rom_out;
|
||||||
|
5'b01000: bus[3:0] = oprand;
|
||||||
|
5'b01110: bus[7:0] = acc_out1;
|
||||||
|
5'b01101: bus[7:0] = ADDSUB_out;
|
||||||
|
default: bus[7:0] = 8'bx;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
PC pc1(
|
||||||
|
.pc_out(pc_out),
|
||||||
|
.cp(cp),
|
||||||
|
.clk(clk),
|
||||||
|
.clr_(clr_)
|
||||||
|
);
|
||||||
|
|
||||||
|
MAR mar1(
|
||||||
|
.mar_out(mar_out),
|
||||||
|
.mar_in(bus[3:0]),
|
||||||
|
.lm_(lm_),
|
||||||
|
.clk(clk),
|
||||||
|
.clr_(clr_)
|
||||||
|
);
|
||||||
|
|
||||||
|
ROM roml(
|
||||||
|
.rom_out(rom_out),
|
||||||
|
.rom_in(mar_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
IR ir1(
|
||||||
|
.opcode(IR_out),
|
||||||
|
.oprand(oprand),
|
||||||
|
.IR_in(bus[7:0]),
|
||||||
|
.li_(li_),
|
||||||
|
.clk(clk),
|
||||||
|
.clr_(clr_)
|
||||||
|
);
|
||||||
|
|
||||||
|
Controller cont1(
|
||||||
|
.control_signals(con),
|
||||||
|
.opcode(IR_out),
|
||||||
|
.clk(clk),
|
||||||
|
.clr_(clr_)
|
||||||
|
);
|
||||||
|
|
||||||
|
ACC acc1(
|
||||||
|
.acc_out1(acc_out1),
|
||||||
|
.acc_out2(acc_out2),
|
||||||
|
.acc_in(bus[7:0]),
|
||||||
|
.la_(la_),
|
||||||
|
.clk(clk),
|
||||||
|
.clr_(clr_)
|
||||||
|
);
|
||||||
|
|
||||||
|
ADDSUB addsub1(
|
||||||
|
.ADDSUB_out(ADDSUB_out),
|
||||||
|
.ADDSUB_in1(acc_out2),
|
||||||
|
.ADDSUB_in2(BRegister_out),
|
||||||
|
.su(su)
|
||||||
|
);
|
||||||
|
|
||||||
|
BRegister bregister1(
|
||||||
|
.BRegister_out(BRegister_out),
|
||||||
|
.BRegister_in(bus[7:0]),
|
||||||
|
.lb_(lb_),
|
||||||
|
.clk(clk),
|
||||||
|
.clr_(clr_)
|
||||||
|
);
|
||||||
|
|
||||||
|
OutputRegister outputregister1(
|
||||||
|
.OutputRegister_out(SAP_out),
|
||||||
|
.OutputRegister_in(bus[7:0]),
|
||||||
|
.lo_(lo_),
|
||||||
|
.clk(clk),
|
||||||
|
.clr_(clr_)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
module testSAPone;
|
||||||
|
|
||||||
|
wire [7:0] SAP_out;
|
||||||
|
wire [11:0] con;
|
||||||
|
wire [7:0] bus;
|
||||||
|
// wire clk_out, clr_out;
|
||||||
|
reg clk, clr_;
|
||||||
|
|
||||||
|
always #5 clk = ~clk;
|
||||||
|
|
||||||
|
SAPone sapone1(
|
||||||
|
.SAP_out(SAP_out),
|
||||||
|
.con(con),
|
||||||
|
.bus(bus),
|
||||||
|
// .clk_out(clk_out),
|
||||||
|
// .clr_out(clr_out),
|
||||||
|
.clk(clk),
|
||||||
|
.clr_(clr_)
|
||||||
|
);
|
||||||
|
|
||||||
|
// PC pc1(bus[3:0], clk, clr_, cp, ep);
|
||||||
|
// MAR mar1(mar, clk, lm_, bus[3:0]);
|
||||||
|
|
||||||
|
initial
|
||||||
|
begin
|
||||||
|
clk = 0; clr_ = 0;
|
||||||
|
#10 clr_ = 1;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#990 $stop;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
module counter(clk_counter, q_counter, rst_counter);
|
||||||
|
|
||||||
|
input clk_counter;
|
||||||
|
input rst_counter;
|
||||||
|
output [7:0] q_counter;
|
||||||
|
reg [7:0] q_counter;
|
||||||
|
|
||||||
|
always @ (posedge clk_counter)
|
||||||
|
begin
|
||||||
|
if(rst_counter)
|
||||||
|
q_counter <= 8'b00000000;
|
||||||
|
else
|
||||||
|
q_counter <= q_counter + 1;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -1,84 +0,0 @@
|
||||||
/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
|
|
||||||
|
|
||||||
module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] );
|
|
||||||
wire _00_;
|
|
||||||
wire _01_;
|
|
||||||
input clk_counter;
|
|
||||||
wire n22;
|
|
||||||
wire n26;
|
|
||||||
wire n30;
|
|
||||||
wire n34;
|
|
||||||
wire n38;
|
|
||||||
wire n42;
|
|
||||||
wire n46;
|
|
||||||
wire n50;
|
|
||||||
output \q_counter[0] ;
|
|
||||||
reg \q_counter[0] ;
|
|
||||||
output \q_counter[1] ;
|
|
||||||
reg \q_counter[1] ;
|
|
||||||
output \q_counter[2] ;
|
|
||||||
reg \q_counter[2] ;
|
|
||||||
output \q_counter[3] ;
|
|
||||||
reg \q_counter[3] ;
|
|
||||||
output \q_counter[4] ;
|
|
||||||
reg \q_counter[4] ;
|
|
||||||
output \q_counter[5] ;
|
|
||||||
reg \q_counter[5] ;
|
|
||||||
output \q_counter[6] ;
|
|
||||||
reg \q_counter[6] ;
|
|
||||||
output \q_counter[7] ;
|
|
||||||
reg \q_counter[7] ;
|
|
||||||
input rst_counter;
|
|
||||||
|
|
||||||
always @(posedge clk_counter)
|
|
||||||
begin
|
|
||||||
if(rst_counter) \q_counter[0] <= 1'b0;
|
|
||||||
else \q_counter[0] <= n22;
|
|
||||||
end
|
|
||||||
always @(posedge clk_counter)
|
|
||||||
begin
|
|
||||||
if(rst_counter) \q_counter[1] <= 1'b0;
|
|
||||||
else \q_counter[1] <= n26;
|
|
||||||
end
|
|
||||||
always @(posedge clk_counter)
|
|
||||||
begin
|
|
||||||
if(rst_counter) \q_counter[2] <= 1'b0;
|
|
||||||
else \q_counter[2] <= n30;
|
|
||||||
end
|
|
||||||
always @(posedge clk_counter)
|
|
||||||
begin
|
|
||||||
if(rst_counter) \q_counter[3] <= 1'b0;
|
|
||||||
else \q_counter[3] <= n34;
|
|
||||||
end
|
|
||||||
always @(posedge clk_counter)
|
|
||||||
begin
|
|
||||||
if(rst_counter) \q_counter[4] <= 1'b0;
|
|
||||||
else \q_counter[4] <= n38;
|
|
||||||
end
|
|
||||||
always @(posedge clk_counter)
|
|
||||||
begin
|
|
||||||
if(rst_counter) \q_counter[5] <= 1'b0;
|
|
||||||
else \q_counter[5] <= n42;
|
|
||||||
end
|
|
||||||
always @(posedge clk_counter)
|
|
||||||
begin
|
|
||||||
if(rst_counter) \q_counter[6] <= 1'b0;
|
|
||||||
else \q_counter[6] <= n46;
|
|
||||||
end
|
|
||||||
always @(posedge clk_counter)
|
|
||||||
begin
|
|
||||||
if(rst_counter) \q_counter[7] <= 1'b0;
|
|
||||||
else \q_counter[7] <= n50;
|
|
||||||
end
|
|
||||||
|
|
||||||
assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter };
|
|
||||||
assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1] };
|
|
||||||
assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] };
|
|
||||||
assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] };
|
|
||||||
assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter };
|
|
||||||
assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] };
|
|
||||||
assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter };
|
|
||||||
assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] };
|
|
||||||
assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6] };
|
|
||||||
assign n22 = 4'h1 >> { \q_counter[0] , rst_counter };
|
|
||||||
endmodule
|
|
||||||
|
|
@ -1,69 +0,0 @@
|
||||||
# Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 7.0.0 -fPIC -Os)
|
|
||||||
|
|
||||||
.model counter
|
|
||||||
.inputs clk_counter rst_counter
|
|
||||||
.outputs q_counter[0] q_counter[1] q_counter[2] q_counter[3] q_counter[4] q_counter[5] q_counter[6] q_counter[7]
|
|
||||||
.names $false
|
|
||||||
.names $true
|
|
||||||
1
|
|
||||||
.names $undef
|
|
||||||
.names q_counter[7] rst_counter q_counter[6] $abc$3686$new_n20_ $0\q_counter[7][0:0]
|
|
||||||
0011 1
|
|
||||||
1000 1
|
|
||||||
1001 1
|
|
||||||
1010 1
|
|
||||||
.names q_counter[4] q_counter[5] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n20_
|
|
||||||
111111 1
|
|
||||||
.names q_counter[6] $abc$3686$new_n20_ rst_counter $0\q_counter[6][0:0]
|
|
||||||
010 1
|
|
||||||
100 1
|
|
||||||
.names q_counter[5] $abc$3686$new_n23_ rst_counter $0\q_counter[5][0:0]
|
|
||||||
010 1
|
|
||||||
100 1
|
|
||||||
.names q_counter[4] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n23_
|
|
||||||
11111 1
|
|
||||||
.names q_counter[2] rst_counter q_counter[1] q_counter[0] $0\q_counter[2][0:0]
|
|
||||||
0011 1
|
|
||||||
1000 1
|
|
||||||
1001 1
|
|
||||||
1010 1
|
|
||||||
.names q_counter[4] rst_counter q_counter[3] q_counter[2] q_counter[1] q_counter[0] $0\q_counter[4][0:0]
|
|
||||||
001111 1
|
|
||||||
100000 1
|
|
||||||
100001 1
|
|
||||||
100010 1
|
|
||||||
100011 1
|
|
||||||
100100 1
|
|
||||||
100101 1
|
|
||||||
100110 1
|
|
||||||
100111 1
|
|
||||||
101000 1
|
|
||||||
101001 1
|
|
||||||
101010 1
|
|
||||||
101011 1
|
|
||||||
101100 1
|
|
||||||
101101 1
|
|
||||||
101110 1
|
|
||||||
.names q_counter[3] rst_counter q_counter[2] q_counter[1] q_counter[0] $0\q_counter[3][0:0]
|
|
||||||
00111 1
|
|
||||||
10000 1
|
|
||||||
10001 1
|
|
||||||
10010 1
|
|
||||||
10011 1
|
|
||||||
10100 1
|
|
||||||
10101 1
|
|
||||||
10110 1
|
|
||||||
.names q_counter[1] q_counter[0] rst_counter $0\q_counter[1][0:0]
|
|
||||||
010 1
|
|
||||||
100 1
|
|
||||||
.names q_counter[0] rst_counter $0\q_counter[0][0:0]
|
|
||||||
00 1
|
|
||||||
.latch $0\q_counter[7][0:0] q_counter[7] re clk_counter 2
|
|
||||||
.latch $0\q_counter[6][0:0] q_counter[6] re clk_counter 2
|
|
||||||
.latch $0\q_counter[5][0:0] q_counter[5] re clk_counter 2
|
|
||||||
.latch $0\q_counter[4][0:0] q_counter[4] re clk_counter 2
|
|
||||||
.latch $0\q_counter[3][0:0] q_counter[3] re clk_counter 2
|
|
||||||
.latch $0\q_counter[2][0:0] q_counter[2] re clk_counter 2
|
|
||||||
.latch $0\q_counter[1][0:0] q_counter[1] re clk_counter 2
|
|
||||||
.latch $0\q_counter[0][0:0] q_counter[0] re clk_counter 2
|
|
||||||
.end
|
|
||||||
|
|
@ -1,20 +0,0 @@
|
||||||
clk_counter 0.500000 2.000000
|
|
||||||
rst_counter 0.492200 0.201800
|
|
||||||
q_counter[0] 0.281800 0.563400
|
|
||||||
q_counter[1] 0.248200 0.273600
|
|
||||||
q_counter[2] 0.183200 0.125600
|
|
||||||
q_counter[3] 0.097400 0.044800
|
|
||||||
q_counter[4] 0.022600 0.007200
|
|
||||||
q_counter[5] 0.002200 0.000800
|
|
||||||
q_counter[6] 0.000000 0.000000
|
|
||||||
q_counter[7] 0.000000 0.000000
|
|
||||||
$0\q_counter[7][0:0] 0 0
|
|
||||||
$0\q_counter[6][0:0] 0 0
|
|
||||||
$0\q_counter[5][0:0] 0 0
|
|
||||||
$0\q_counter[4][0:0] 0 0
|
|
||||||
$0\q_counter[3][0:0] 0 0
|
|
||||||
$0\q_counter[2][0:0] 0 0
|
|
||||||
$0\q_counter[1][0:0] 0 0
|
|
||||||
$0\q_counter[0][0:0] 0 0
|
|
||||||
$abc$3686$new_n23_ 0 0
|
|
||||||
$abc$3686$new_n20_ 0 0
|
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
module counter_tb;
|
||||||
|
|
||||||
|
reg clk_counter, rst_counter;
|
||||||
|
wire [7:0] q_counter;
|
||||||
|
|
||||||
|
counter_original C_1(
|
||||||
|
clk_counter,
|
||||||
|
q_counter,
|
||||||
|
rst_counter);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
#0 rst_counter = 1'b1; clk_counter = 1'b0;
|
||||||
|
#100 rst_counter = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
always begin
|
||||||
|
#10 clk_counter = ~clk_counter;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
#5000 $stop;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -242,7 +242,7 @@
|
||||||
<!-- physical pb_type binding in complex block CLB -->
|
<!-- physical pb_type binding in complex block CLB -->
|
||||||
<!-- physical mode will be the default mode if not specified -->
|
<!-- physical mode will be the default mode if not specified -->
|
||||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||||
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
|
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
|
||||||
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
|
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
|
||||||
<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
|
<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
|
||||||
<!-- Binding operating pb_type to physical pb_type -->
|
<!-- Binding operating pb_type to physical pb_type -->
|
||||||
|
|
@ -277,7 +277,7 @@
|
||||||
<pb_type name="clb_spypad.fle" physical_mode_name="physical"/>
|
<pb_type name="clb_spypad.fle" physical_mode_name="physical"/>
|
||||||
|
|
||||||
<!-- Binding regular FLEs -->
|
<!-- Binding regular FLEs -->
|
||||||
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
|
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
|
||||||
<pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
|
<pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
|
||||||
<pb_type name="clb_spypad.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
|
<pb_type name="clb_spypad.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
|
||||||
<!-- Binding operating pb_type to physical pb_type -->
|
<!-- Binding operating pb_type to physical pb_type -->
|
||||||
|
|
@ -310,7 +310,7 @@
|
||||||
<!-- physical mode will be the default mode if not specified -->
|
<!-- physical mode will be the default mode if not specified -->
|
||||||
<pb_type name="clb_spypad.fle_spypad" physical_mode_name="physical"/>
|
<pb_type name="clb_spypad.fle_spypad" physical_mode_name="physical"/>
|
||||||
|
|
||||||
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="11"/>
|
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="00"/>
|
||||||
<pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
|
<pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
|
||||||
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
|
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
|
||||||
<!-- Binding operating pb_type to physical pb_type -->
|
<!-- Binding operating pb_type to physical pb_type -->
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,231 @@
|
||||||
|
<!-- Architecture annotation for OpenFPGA framework
|
||||||
|
This annotation supports the k6_N8_40nm.xml
|
||||||
|
- General purpose logic block
|
||||||
|
- K = 6, N = 8, I = 32
|
||||||
|
- Single mode
|
||||||
|
- Routing architecture
|
||||||
|
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||||
|
-->
|
||||||
|
<openfpga_architecture>
|
||||||
|
<technology_library>
|
||||||
|
<device_library>
|
||||||
|
<device_model name="logic" type="transistor">
|
||||||
|
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="0.9" pn_ratio="2"/>
|
||||||
|
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
<device_model name="io" type="transistor">
|
||||||
|
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="2.5" pn_ratio="3"/>
|
||||||
|
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
</device_library>
|
||||||
|
<variation_library>
|
||||||
|
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
</variation_library>
|
||||||
|
</technology_library>
|
||||||
|
<circuit_library>
|
||||||
|
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="OR"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="a" size="1"/>
|
||||||
|
<port type="input" prefix="b" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||||
|
10e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||||
|
10e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="input" prefix="sel" size="1"/>
|
||||||
|
<port type="input" prefix="selb" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||||
|
10e-12 5e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||||
|
10e-12 5e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||||
|
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" fracturable_lut="true"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||||
|
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
|
||||||
|
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
||||||
|
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
|
||||||
|
<port type="sram" prefix="sram" size="64"/>
|
||||||
|
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="output" prefix="Qb" size="1"/>
|
||||||
|
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
|
||||||
|
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
|
<port type="input" prefix="outpad" size="1"/>
|
||||||
|
<port type="output" prefix="inpad" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
</circuit_library>
|
||||||
|
<configuration_protocol>
|
||||||
|
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
|
||||||
|
</configuration_protocol>
|
||||||
|
<connection_block>
|
||||||
|
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||||
|
</connection_block>
|
||||||
|
<switch_block>
|
||||||
|
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||||
|
</switch_block>
|
||||||
|
<routing_segment>
|
||||||
|
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||||
|
</routing_segment>
|
||||||
|
<pb_type_annotations>
|
||||||
|
<!-- physical pb_type binding in complex block IO -->
|
||||||
|
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||||
|
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
|
||||||
|
<!-- physical pb_type binding in complex block CLB -->
|
||||||
|
<!-- physical mode will be the default mode if not specified -->
|
||||||
|
<pb_type name="clb">
|
||||||
|
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||||
|
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
|
||||||
|
<!-- Binding operating pb_type to physical pb_type -->
|
||||||
|
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||||
|
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:4]"/>
|
||||||
|
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||||
|
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
|
||||||
|
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:5]"/>
|
||||||
|
<port name="out" physical_mode_port="lut6_out"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
</pb_type_annotations>
|
||||||
|
</openfpga_architecture>
|
||||||
|
|
@ -0,0 +1,231 @@
|
||||||
|
<!-- Architecture annotation for OpenFPGA framework
|
||||||
|
This annotation supports the k6_N10_40nm.xml
|
||||||
|
- General purpose logic block
|
||||||
|
- K = 6, N = 8, I = 40
|
||||||
|
- Single mode
|
||||||
|
- Routing architecture
|
||||||
|
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||||
|
-->
|
||||||
|
<openfpga_architecture>
|
||||||
|
<technology_library>
|
||||||
|
<device_library>
|
||||||
|
<device_model name="logic" type="transistor">
|
||||||
|
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="0.9" pn_ratio="2"/>
|
||||||
|
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
<device_model name="io" type="transistor">
|
||||||
|
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="2.5" pn_ratio="3"/>
|
||||||
|
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
</device_library>
|
||||||
|
<variation_library>
|
||||||
|
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
</variation_library>
|
||||||
|
</technology_library>
|
||||||
|
<circuit_library>
|
||||||
|
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="OR"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="a" size="1"/>
|
||||||
|
<port type="input" prefix="b" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||||
|
10e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||||
|
10e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="input" prefix="sel" size="1"/>
|
||||||
|
<port type="input" prefix="selb" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||||
|
10e-12 5e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||||
|
10e-12 5e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true" local_encoder="true">
|
||||||
|
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||||
|
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" fracturable_lut="true"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||||
|
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
|
||||||
|
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
||||||
|
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
|
||||||
|
<port type="sram" prefix="sram" size="64"/>
|
||||||
|
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="output" prefix="Qb" size="1"/>
|
||||||
|
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
|
||||||
|
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
|
<port type="input" prefix="outpad" size="1"/>
|
||||||
|
<port type="output" prefix="inpad" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
</circuit_library>
|
||||||
|
<configuration_protocol>
|
||||||
|
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
|
||||||
|
</configuration_protocol>
|
||||||
|
<connection_block>
|
||||||
|
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||||
|
</connection_block>
|
||||||
|
<switch_block>
|
||||||
|
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||||
|
</switch_block>
|
||||||
|
<routing_segment>
|
||||||
|
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||||
|
</routing_segment>
|
||||||
|
<pb_type_annotations>
|
||||||
|
<!-- physical pb_type binding in complex block IO -->
|
||||||
|
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||||
|
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
|
||||||
|
<!-- physical pb_type binding in complex block CLB -->
|
||||||
|
<!-- physical mode will be the default mode if not specified -->
|
||||||
|
<pb_type name="clb">
|
||||||
|
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||||
|
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
|
||||||
|
<!-- Binding operating pb_type to physical pb_type -->
|
||||||
|
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||||
|
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:4]"/>
|
||||||
|
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||||
|
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
|
||||||
|
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:5]"/>
|
||||||
|
<port name="out" physical_mode_port="lut6_out"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
</pb_type_annotations>
|
||||||
|
</openfpga_architecture>
|
||||||
|
|
@ -0,0 +1,223 @@
|
||||||
|
<!-- Architecture annotation for OpenFPGA framework
|
||||||
|
This annotation supports the k6_N10_40nm.xml
|
||||||
|
- General purpose logic block
|
||||||
|
- K = 6, N = 8, I = 40
|
||||||
|
- Single mode
|
||||||
|
- Routing architecture
|
||||||
|
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||||
|
-->
|
||||||
|
<openfpga_architecture>
|
||||||
|
<technology_library>
|
||||||
|
<device_library>
|
||||||
|
<device_model name="logic" type="transistor">
|
||||||
|
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="0.9" pn_ratio="2"/>
|
||||||
|
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
<device_model name="io" type="transistor">
|
||||||
|
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="2.5" pn_ratio="3"/>
|
||||||
|
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
</device_library>
|
||||||
|
<variation_library>
|
||||||
|
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
</variation_library>
|
||||||
|
</technology_library>
|
||||||
|
<circuit_library>
|
||||||
|
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="OR"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="a" size="1"/>
|
||||||
|
<port type="input" prefix="b" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||||
|
10e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||||
|
10e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<!-- Define a circuit model for the standard cell MUX2
|
||||||
|
OpenFPGA requires the following truth table for the MUX2
|
||||||
|
When the select signal sel is enabled, the first input, i.e., in0
|
||||||
|
will be propagated to the output, i.e., out
|
||||||
|
If your standard cell provider does not offer the exact truth table,
|
||||||
|
you can simply swap the inputs as shown in the example below
|
||||||
|
-->
|
||||||
|
<circuit_model type="gate" name="MUX2" prefix="MUX2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mux2.v">
|
||||||
|
<design_technology type="cmos" topology="MUX2"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in0" lib_name="B" size="1"/>
|
||||||
|
<port type="input" prefix="in1" lib_name="A" size="1"/>
|
||||||
|
<port type="input" prefix="sel" lib_name="S0" size="1"/>
|
||||||
|
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||||
|
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||||
|
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" fracturable_lut="true"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||||
|
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
|
||||||
|
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||||
|
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
|
||||||
|
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
||||||
|
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
|
||||||
|
<port type="sram" prefix="sram" size="64"/>
|
||||||
|
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="output" prefix="Qb" size="1"/>
|
||||||
|
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
|
||||||
|
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
|
<port type="input" prefix="outpad" size="1"/>
|
||||||
|
<port type="output" prefix="inpad" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
</circuit_library>
|
||||||
|
<configuration_protocol>
|
||||||
|
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
|
||||||
|
</configuration_protocol>
|
||||||
|
<connection_block>
|
||||||
|
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
|
||||||
|
</connection_block>
|
||||||
|
<switch_block>
|
||||||
|
<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
|
||||||
|
</switch_block>
|
||||||
|
<routing_segment>
|
||||||
|
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||||
|
</routing_segment>
|
||||||
|
<pb_type_annotations>
|
||||||
|
<!-- physical pb_type binding in complex block IO -->
|
||||||
|
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||||
|
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
|
||||||
|
<!-- physical pb_type binding in complex block CLB -->
|
||||||
|
<!-- physical mode will be the default mode if not specified -->
|
||||||
|
<pb_type name="clb">
|
||||||
|
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||||
|
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
|
||||||
|
<!-- Binding operating pb_type to physical pb_type -->
|
||||||
|
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||||
|
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:4]"/>
|
||||||
|
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||||
|
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
|
||||||
|
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:5]"/>
|
||||||
|
<port name="out" physical_mode_port="lut6_out"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
</pb_type_annotations>
|
||||||
|
</openfpga_architecture>
|
||||||
|
|
@ -0,0 +1,222 @@
|
||||||
|
<!-- Architecture annotation for OpenFPGA framework
|
||||||
|
This annotation supports the k6_N10_40nm.xml
|
||||||
|
- General purpose logic block
|
||||||
|
- K = 6, N = 8, I = 40
|
||||||
|
- Single mode
|
||||||
|
- Routing architecture
|
||||||
|
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||||
|
-->
|
||||||
|
<openfpga_architecture>
|
||||||
|
<technology_library>
|
||||||
|
<device_library>
|
||||||
|
<device_model name="logic" type="transistor">
|
||||||
|
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="0.9" pn_ratio="2"/>
|
||||||
|
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
<device_model name="io" type="transistor">
|
||||||
|
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="2.5" pn_ratio="3"/>
|
||||||
|
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
</device_library>
|
||||||
|
<variation_library>
|
||||||
|
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
</variation_library>
|
||||||
|
</technology_library>
|
||||||
|
<circuit_library>
|
||||||
|
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="OR"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="a" size="1"/>
|
||||||
|
<port type="input" prefix="b" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||||
|
10e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||||
|
10e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="pass_gate" name="MUX2" prefix="MUX2" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="input" prefix="sel" size="1"/>
|
||||||
|
<port type="input" prefix="selb" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||||
|
10e-12 5e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||||
|
10e-12 5e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||||
|
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||||
|
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" fracturable_lut="true"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||||
|
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
|
||||||
|
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||||
|
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
|
||||||
|
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
||||||
|
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
|
||||||
|
<port type="sram" prefix="sram" size="64"/>
|
||||||
|
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="output" prefix="Qb" size="1"/>
|
||||||
|
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
|
||||||
|
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||||
|
<port type="input" prefix="outpad" size="1"/>
|
||||||
|
<port type="output" prefix="inpad" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
</circuit_library>
|
||||||
|
<configuration_protocol>
|
||||||
|
<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
|
||||||
|
</configuration_protocol>
|
||||||
|
<connection_block>
|
||||||
|
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
|
||||||
|
</connection_block>
|
||||||
|
<switch_block>
|
||||||
|
<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
|
||||||
|
</switch_block>
|
||||||
|
<routing_segment>
|
||||||
|
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||||
|
</routing_segment>
|
||||||
|
<pb_type_annotations>
|
||||||
|
<!-- physical pb_type binding in complex block IO -->
|
||||||
|
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||||
|
<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
|
||||||
|
<!-- physical pb_type binding in complex block CLB -->
|
||||||
|
<!-- physical mode will be the default mode if not specified -->
|
||||||
|
<pb_type name="clb">
|
||||||
|
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||||
|
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
|
||||||
|
<!-- Binding operating pb_type to physical pb_type -->
|
||||||
|
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||||
|
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:4]"/>
|
||||||
|
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||||
|
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
|
||||||
|
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:5]"/>
|
||||||
|
<port name="out" physical_mode_port="lut6_out"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
</pb_type_annotations>
|
||||||
|
</openfpga_architecture>
|
||||||
|
|
@ -419,6 +419,17 @@ def prepare_run_directory(run_dir):
|
||||||
with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile:
|
with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile:
|
||||||
archfile.write(tmpl.substitute(script_env_vars["PATH"]))
|
archfile.write(tmpl.substitute(script_env_vars["PATH"]))
|
||||||
|
|
||||||
|
# Sanitize provided openshell template, if provided
|
||||||
|
if (args.openfpga_shell_template):
|
||||||
|
if not os.path.isfile(args.openfpga_shell_template or ""):
|
||||||
|
logger.error("Openfpga shell file - %s" %
|
||||||
|
args.openfpga_shell_template)
|
||||||
|
clean_up_and_exit("Provided openfpga_shell_template" +
|
||||||
|
f" {args.openfpga_shell_template} file not found")
|
||||||
|
else:
|
||||||
|
shutil.copy(args.openfpga_shell_template,
|
||||||
|
args.top_module+"_template.openfpga")
|
||||||
|
|
||||||
# Create benchmark dir in run_dir and copy flattern architecture file
|
# Create benchmark dir in run_dir and copy flattern architecture file
|
||||||
os.mkdir("benchmark")
|
os.mkdir("benchmark")
|
||||||
try:
|
try:
|
||||||
|
|
@ -600,17 +611,6 @@ def collect_files_for_vpr():
|
||||||
clean_up_and_exit("Provided base_verilog file not found")
|
clean_up_and_exit("Provided base_verilog file not found")
|
||||||
shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
|
shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
|
||||||
|
|
||||||
# Sanitize provided openshell template, if provided
|
|
||||||
if (args.openfpga_shell_template):
|
|
||||||
if not os.path.isfile(args.openfpga_shell_template or ""):
|
|
||||||
logger.error("Openfpga shell file - %s" %
|
|
||||||
args.openfpga_shell_template)
|
|
||||||
clean_up_and_exit("Provided openfpga_shell_template" +
|
|
||||||
f" {args.openfpga_shell_template} file not found")
|
|
||||||
else:
|
|
||||||
shutil.copy(args.openfpga_shell_template,
|
|
||||||
args.top_module+"_template.openfpga")
|
|
||||||
|
|
||||||
|
|
||||||
def run_vpr():
|
def run_vpr():
|
||||||
ExecTime["VPRStart"] = time.time()
|
ExecTime["VPRStart"] = time.time()
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,14 +23,11 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
end_flow_with_test=
|
end_flow_with_test=
|
||||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,14 +23,11 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
end_flow_with_test=
|
end_flow_with_test=
|
||||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,14 +23,11 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
end_flow_with_test=
|
end_flow_with_test=
|
||||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,14 +23,11 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
end_flow_with_test=
|
end_flow_with_test=
|
||||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,14 +23,11 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
end_flow_with_test=
|
end_flow_with_test=
|
||||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,14 +23,11 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
end_flow_with_test=
|
end_flow_with_test=
|
||||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,14 +23,11 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
end_flow_with_test=
|
end_flow_with_test=
|
||||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,11 +23,9 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,12 +23,10 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = counter
|
bench0_top = counter
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
|
|
||||||
|
|
@ -15,12 +15,12 @@ spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=vpr_blif
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
||||||
[ARCHITECTURES]
|
[ARCHITECTURES]
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
#
|
#
|
||||||
|
|
|
||||||
|
|
@ -15,12 +15,12 @@ spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=vpr_blif
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
||||||
[ARCHITECTURES]
|
[ARCHITECTURES]
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
||||||
|
|
|
||||||
|
|
@ -15,12 +15,12 @@ spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=vpr_blif
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
||||||
[ARCHITECTURES]
|
[ARCHITECTURES]
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
||||||
|
|
|
||||||
|
|
@ -15,12 +15,12 @@ spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=vpr_blif
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
||||||
[ARCHITECTURES]
|
[ARCHITECTURES]
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,12 +23,10 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,12 +23,10 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,12 +23,10 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
verilog_output=true
|
verilog_output=true
|
||||||
timeout_each_job = 20*60
|
timeout_each_job = 20*60
|
||||||
fpga_flow=vpr_blif
|
fpga_flow=yosys_vpr
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
external_fabric_key_file=
|
external_fabric_key_file=
|
||||||
|
|
@ -23,12 +23,10 @@ external_fabric_key_file=
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
|
||||||
[SYNTHESIS_PARAM]
|
[SYNTHESIS_PARAM]
|
||||||
bench0_top = and2
|
bench0_top = and2
|
||||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
|
||||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
|
||||||
bench0_chan_width = 300
|
bench0_chan_width = 300
|
||||||
|
|
||||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
|
|
||||||
|
|
@ -8,7 +8,7 @@
|
||||||
|
|
||||||
[GENERAL]
|
[GENERAL]
|
||||||
run_engine=openfpga_shell
|
run_engine=openfpga_shell
|
||||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
|
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
|
||||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||||
power_analysis = true
|
power_analysis = true
|
||||||
spice_output=false
|
spice_output=false
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,441 @@
|
||||||
|
<!--
|
||||||
|
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
|
||||||
|
|
||||||
|
- 40 nm technology
|
||||||
|
- General purpose logic block:
|
||||||
|
K = 6, N = 8, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared)
|
||||||
|
with optionally registered outputs
|
||||||
|
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
|
||||||
|
|
||||||
|
Details on Modelling:
|
||||||
|
|
||||||
|
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
|
||||||
|
|
||||||
|
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
|
||||||
|
-->
|
||||||
|
<architecture>
|
||||||
|
<!--
|
||||||
|
ODIN II specific config begins
|
||||||
|
Describes the types of user-specified netlist blocks (in blif, this corresponds to
|
||||||
|
".model [type_of_block]") that this architecture supports.
|
||||||
|
|
||||||
|
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
|
||||||
|
already special structures in blif (.names, .input, .output, and .latch)
|
||||||
|
that describe them.
|
||||||
|
-->
|
||||||
|
<models>
|
||||||
|
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||||
|
<model name="io">
|
||||||
|
<input_ports>
|
||||||
|
<port name="outpad"/>
|
||||||
|
</input_ports>
|
||||||
|
<output_ports>
|
||||||
|
<port name="inpad"/>
|
||||||
|
</output_ports>
|
||||||
|
</model>
|
||||||
|
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||||
|
<model name="frac_lut6">
|
||||||
|
<input_ports>
|
||||||
|
<port name="in"/>
|
||||||
|
</input_ports>
|
||||||
|
<output_ports>
|
||||||
|
<port name="lut5_out"/>
|
||||||
|
<port name="lut6_out"/>
|
||||||
|
</output_ports>
|
||||||
|
</model>
|
||||||
|
</models>
|
||||||
|
<tiles>
|
||||||
|
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||||
|
If you need to register the I/O, define clocks in the circuit models
|
||||||
|
These clocks can be handled in back-end
|
||||||
|
-->
|
||||||
|
<tile name="io" capacity="8" area="0">
|
||||||
|
<equivalent_sites>
|
||||||
|
<site pb_type="io"/>
|
||||||
|
</equivalent_sites>
|
||||||
|
<input name="outpad" num_pins="1"/>
|
||||||
|
<output name="inpad" num_pins="1"/>
|
||||||
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||||
|
<pinlocations pattern="custom">
|
||||||
|
<loc side="left">io.outpad io.inpad</loc>
|
||||||
|
<loc side="top">io.outpad io.inpad</loc>
|
||||||
|
<loc side="right">io.outpad io.inpad</loc>
|
||||||
|
<loc side="bottom">io.outpad io.inpad</loc>
|
||||||
|
</pinlocations>
|
||||||
|
</tile>
|
||||||
|
<tile name="clb" area="53894">
|
||||||
|
<equivalent_sites>
|
||||||
|
<site pb_type="clb"/>
|
||||||
|
</equivalent_sites>
|
||||||
|
<input name="I" num_pins="32" equivalent="full"/>
|
||||||
|
<output name="O" num_pins="16" equivalent="none"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||||
|
<pinlocations pattern="spread"/>
|
||||||
|
</tile>
|
||||||
|
</tiles>
|
||||||
|
<!-- ODIN II specific config ends -->
|
||||||
|
<!-- Physical descriptions begin -->
|
||||||
|
<layout tileable="true">
|
||||||
|
<!--auto_layout aspect_ratio="1.0"-->
|
||||||
|
<fixed_layout name="2x2" width="4" height="4">
|
||||||
|
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||||
|
<perimeter type="io" priority="100"/>
|
||||||
|
<corners type="EMPTY" priority="101"/>
|
||||||
|
<!--Fill with 'clb'-->
|
||||||
|
<fill type="clb" priority="10"/>
|
||||||
|
</fixed_layout>
|
||||||
|
<!-- /auto_layout -->
|
||||||
|
</layout>
|
||||||
|
<device>
|
||||||
|
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||||
|
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
||||||
|
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
||||||
|
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
||||||
|
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
||||||
|
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
||||||
|
lined up with Stratix IV.
|
||||||
|
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
||||||
|
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
||||||
|
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
||||||
|
by 2.5x when looking up in Jeff's tables.
|
||||||
|
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
||||||
|
proposed FPGA, and which is also 40 nm
|
||||||
|
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
||||||
|
4x minimum drive strength buffer. -->
|
||||||
|
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||||
|
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||||
|
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||||
|
-->
|
||||||
|
<area grid_logic_tile_area="0"/>
|
||||||
|
<chan_width_distr>
|
||||||
|
<x distr="uniform" peak="1.000000"/>
|
||||||
|
<y distr="uniform" peak="1.000000"/>
|
||||||
|
</chan_width_distr>
|
||||||
|
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
|
||||||
|
<connection_block input_switch_name="ipin_cblock"/>
|
||||||
|
</device>
|
||||||
|
<switchlist>
|
||||||
|
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
||||||
|
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
||||||
|
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
||||||
|
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
||||||
|
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
|
||||||
|
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
|
||||||
|
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
|
||||||
|
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
|
||||||
|
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
|
||||||
|
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
|
||||||
|
2.5x when looking up in Jeff's tables.
|
||||||
|
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
||||||
|
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
||||||
|
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||||
|
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
|
||||||
|
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||||
|
</switchlist>
|
||||||
|
<segmentlist>
|
||||||
|
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
||||||
|
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
||||||
|
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
||||||
|
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
|
||||||
|
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||||
|
<mux name="0"/>
|
||||||
|
<sb type="pattern">1 1 1 1 1</sb>
|
||||||
|
<cb type="pattern">1 1 1 1</cb>
|
||||||
|
</segment>
|
||||||
|
</segmentlist>
|
||||||
|
<complexblocklist>
|
||||||
|
<!-- Define I/O pads begin -->
|
||||||
|
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
||||||
|
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
||||||
|
<pb_type name="io">
|
||||||
|
<input name="outpad" num_pins="1"/>
|
||||||
|
<output name="inpad" num_pins="1"/>
|
||||||
|
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||||
|
If you need to register the I/O, define clocks in the circuit models
|
||||||
|
These clocks can be handled in back-end
|
||||||
|
-->
|
||||||
|
<!-- A mode denotes the physical implementation of an I/O
|
||||||
|
This mode will be not packable but is mainly used for fabric verilog generation
|
||||||
|
-->
|
||||||
|
<mode name="physical" disabled_in_pack="true">
|
||||||
|
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||||
|
<input name="outpad" num_pins="1"/>
|
||||||
|
<output name="inpad" num_pins="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
||||||
|
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||||
|
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||||
|
</direct>
|
||||||
|
</interconnect>
|
||||||
|
</mode>
|
||||||
|
|
||||||
|
<!-- IOs can operate as either inputs or outputs.
|
||||||
|
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
||||||
|
the delays to and from registers in the I/O (and generally I/Os are registered
|
||||||
|
today and that is when you timing analyze them.
|
||||||
|
-->
|
||||||
|
<mode name="inpad">
|
||||||
|
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||||
|
<output name="inpad" num_pins="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||||
|
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||||
|
</direct>
|
||||||
|
</interconnect>
|
||||||
|
</mode>
|
||||||
|
<mode name="outpad">
|
||||||
|
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||||
|
<input name="outpad" num_pins="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||||
|
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||||
|
</direct>
|
||||||
|
</interconnect>
|
||||||
|
</mode>
|
||||||
|
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||||
|
<!-- IOs go on the periphery of the FPGA, for consistency,
|
||||||
|
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
||||||
|
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
||||||
|
-->
|
||||||
|
<!-- Place I/Os on the sides of the FPGA -->
|
||||||
|
<power method="ignore"/>
|
||||||
|
</pb_type>
|
||||||
|
<!-- Define I/O pads ends -->
|
||||||
|
<!-- Define general purpose logic block (CLB) begin -->
|
||||||
|
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
|
||||||
|
area is 60 L^2 yields a tile area of 84375 MWTAs.
|
||||||
|
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
|
||||||
|
This means that only 37% of our area is in the general routing, and 63% is inside the logic
|
||||||
|
block. Note that the crossbar / local interconnect is considered part of the logic block
|
||||||
|
area in this analysis. That is a lower proportion of of routing area than most academics
|
||||||
|
assume, but note that the total routing area really includes the crossbar, which would push
|
||||||
|
routing area up significantly, we estimate into the ~70% range.
|
||||||
|
-->
|
||||||
|
<pb_type name="clb">
|
||||||
|
<input name="I" num_pins="32" equivalent="full"/>
|
||||||
|
<output name="O" num_pins="16" equivalent="none"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<!-- Describe fracturable logic element.
|
||||||
|
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||||||
|
The outputs of the fracturable logic element can be optionally registered
|
||||||
|
-->
|
||||||
|
<pb_type name="fle" num_pb="8">
|
||||||
|
<input name="in" num_pins="6"/>
|
||||||
|
<output name="out" num_pins="2"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<!-- Physical mode definition begin (physical implementation of the fle) -->
|
||||||
|
<mode name="physical" disabled_in_pack="true">
|
||||||
|
<pb_type name="fabric" num_pb="1">
|
||||||
|
<input name="in" num_pins="6"/>
|
||||||
|
<output name="out" num_pins="2"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<pb_type name="frac_logic" num_pb="1">
|
||||||
|
<input name="in" num_pins="6"/>
|
||||||
|
<output name="out" num_pins="2"/>
|
||||||
|
<!-- Define LUT -->
|
||||||
|
<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
|
||||||
|
<input name="in" num_pins="6"/>
|
||||||
|
<output name="lut5_out" num_pins="2"/>
|
||||||
|
<output name="lut6_out" num_pins="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
|
||||||
|
<direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
|
||||||
|
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
|
||||||
|
<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
|
||||||
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<!-- Define flip-flop -->
|
||||||
|
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
|
||||||
|
<input name="D" num_pins="1" port_class="D"/>
|
||||||
|
<output name="Q" num_pins="1" port_class="Q"/>
|
||||||
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||||
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
|
||||||
|
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
|
||||||
|
<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
|
||||||
|
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
|
||||||
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||||
|
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
|
||||||
|
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
|
||||||
|
</mux>
|
||||||
|
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||||
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||||
|
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
|
||||||
|
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
|
||||||
|
</mux>
|
||||||
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="fle.in" output="fabric.in"/>
|
||||||
|
<direct name="direct2" input="fabric.out" output="fle.out"/>
|
||||||
|
<direct name="direct3" input="fle.clk" output="fabric.clk"/>
|
||||||
|
</interconnect>
|
||||||
|
</mode>
|
||||||
|
<!-- Physical mode definition end (physical implementation of the fle) -->
|
||||||
|
<!-- Dual 5-LUT mode definition begin -->
|
||||||
|
<mode name="n2_lut5">
|
||||||
|
<pb_type name="lut5inter" num_pb="1">
|
||||||
|
<input name="in" num_pins="5"/>
|
||||||
|
<output name="out" num_pins="2"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<pb_type name="ble5" num_pb="2">
|
||||||
|
<input name="in" num_pins="5"/>
|
||||||
|
<output name="out" num_pins="1"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<!-- Define the LUT -->
|
||||||
|
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
||||||
|
<input name="in" num_pins="5" port_class="lut_in"/>
|
||||||
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||||
|
<!-- LUT timing using delay matrix -->
|
||||||
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||||
|
we instead take the average of these numbers to get more stable results
|
||||||
|
82e-12
|
||||||
|
173e-12
|
||||||
|
261e-12
|
||||||
|
263e-12
|
||||||
|
398e-12
|
||||||
|
-->
|
||||||
|
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||||||
|
235e-12
|
||||||
|
235e-12
|
||||||
|
235e-12
|
||||||
|
235e-12
|
||||||
|
235e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</pb_type>
|
||||||
|
<!-- Define the flip-flop -->
|
||||||
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||||
|
<input name="D" num_pins="1" port_class="D"/>
|
||||||
|
<output name="Q" num_pins="1" port_class="Q"/>
|
||||||
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||||
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
|
||||||
|
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
|
||||||
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||||
|
<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
|
||||||
|
<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
|
||||||
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||||
|
<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
|
||||||
|
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
|
||||||
|
</mux>
|
||||||
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
|
||||||
|
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
|
||||||
|
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
|
||||||
|
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
|
||||||
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
|
||||||
|
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
|
||||||
|
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
|
||||||
|
</interconnect>
|
||||||
|
</mode>
|
||||||
|
<!-- Dual 5-LUT mode definition end -->
|
||||||
|
<!-- 6-LUT mode definition begin -->
|
||||||
|
<mode name="n1_lut6">
|
||||||
|
<!-- Define 6-LUT mode -->
|
||||||
|
<pb_type name="ble6" num_pb="1">
|
||||||
|
<input name="in" num_pins="6"/>
|
||||||
|
<output name="out" num_pins="1"/>
|
||||||
|
<clock name="clk" num_pins="1"/>
|
||||||
|
<!-- Define LUT -->
|
||||||
|
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
|
||||||
|
<input name="in" num_pins="6" port_class="lut_in"/>
|
||||||
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||||
|
<!-- LUT timing using delay matrix -->
|
||||||
|
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||||
|
we instead take the average of these numbers to get more stable results
|
||||||
|
82e-12
|
||||||
|
173e-12
|
||||||
|
261e-12
|
||||||
|
263e-12
|
||||||
|
398e-12
|
||||||
|
397e-12
|
||||||
|
-->
|
||||||
|
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
261e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</pb_type>
|
||||||
|
<!-- Define flip-flop -->
|
||||||
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||||
|
<input name="D" num_pins="1" port_class="D"/>
|
||||||
|
<output name="Q" num_pins="1" port_class="Q"/>
|
||||||
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||||
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||||
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||||
|
<direct name="direct2" input="lut6.out" output="ff.D">
|
||||||
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||||
|
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||||||
|
</direct>
|
||||||
|
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||||
|
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||||
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||||
|
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
|
||||||
|
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
|
||||||
|
</mux>
|
||||||
|
</interconnect>
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<direct name="direct1" input="fle.in" output="ble6.in"/>
|
||||||
|
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||||||
|
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||||
|
</interconnect>
|
||||||
|
</mode>
|
||||||
|
<!-- 6-LUT mode definition end -->
|
||||||
|
</pb_type>
|
||||||
|
<interconnect>
|
||||||
|
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
||||||
|
The delays below come from Stratix IV. the delay through a connection block
|
||||||
|
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||||||
|
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||||||
|
delay within the crossbar is 95 ps.
|
||||||
|
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
|
||||||
|
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||||
|
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||||
|
to get the part that should be marked on the crossbar. -->
|
||||||
|
<complete name="crossbar" input="clb.I fle[7:0].out" output="fle[7:0].in">
|
||||||
|
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[7:0].in"/>
|
||||||
|
<delay_constant max="75e-12" in_port="fle[7:0].out" out_port="fle[7:0].in"/>
|
||||||
|
</complete>
|
||||||
|
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
|
||||||
|
</complete>
|
||||||
|
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||||
|
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||||
|
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||||
|
naive specification).
|
||||||
|
-->
|
||||||
|
<direct name="clbouts1" input="fle[7:0].out[0:0]" output="clb.O[7:0]"/>
|
||||||
|
<direct name="clbouts2" input="fle[7:0].out[1:1]" output="clb.O[15:8]"/>
|
||||||
|
</interconnect>
|
||||||
|
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||||
|
<!-- Place this general purpose logic block in any unspecified column -->
|
||||||
|
</pb_type>
|
||||||
|
<!-- Define general purpose logic block (CLB) ends -->
|
||||||
|
</complexblocklist>
|
||||||
|
</architecture>
|
||||||
Loading…
Reference in New Issue