From c26c268dcdc08a3bf0ce0166e25efa19f9f99bd6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 15 Jul 2020 13:55:32 -0600 Subject: [PATCH 01/14] update documentation on fast configuration support for configuration chain --- .../openfpga_shell/openfpga_commands/fpga_verilog_commands.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index de4aecad8..c2044cf57 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -31,7 +31,7 @@ write_verilog_testbench - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches - - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to memory bank and frame-based configuration protocols. When enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. + - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA From eb070694b5d55ada546a13e1ee80967696b29b93 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 15 Jul 2020 17:52:41 -0600 Subject: [PATCH 02/14] fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 9 +++++---- ..._register_scan_chain_depop50_spypad_40nm_openfpga.xml | 6 +++--- openfpga_flow/tasks/spypad/config/task.conf | 2 +- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 0f5640618..27f714957 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1154,17 +1154,18 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, /* Attention: when the fast configuration is enabled, we will start from the first bit '1' * This requires a reset signal (as we forced in the first clock cycle) */ - bool first_bit_one = false; + bool start_config = false; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { - first_bit_one = true; + if ( (false == start_config) + && (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { + start_config = true; } /* In fast configuration mode, we do not output anything * until we have to (the first bit '1' detected) */ if ( (true == fast_configuration) - && (false == first_bit_one)) { + && (false == start_config)) { continue; } diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 0fa650846..7f31c435f 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -242,7 +242,7 @@ - + @@ -277,7 +277,7 @@ - + @@ -310,7 +310,7 @@ - + diff --git a/openfpga_flow/tasks/spypad/config/task.conf b/openfpga_flow/tasks/spypad/config/task.conf index 51197d1f7..13233e400 100644 --- a/openfpga_flow/tasks/spypad/config/task.conf +++ b/openfpga_flow/tasks/spypad/config/task.conf @@ -8,7 +8,7 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false From b5fd6aa8598a4082eae8107737997736098c8602 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 17 Jul 2020 13:01:08 -0600 Subject: [PATCH 03/14] add inverter subckt writer to FPGA-SPICE --- openfpga/src/base/openfpga_spice.cpp | 2 +- openfpga/src/fpga_spice/spice_api.cpp | 5 +- openfpga/src/fpga_spice/spice_api.h | 4 +- .../src/fpga_spice/spice_essential_gates.cpp | 164 +++++++++++++++++- .../src/fpga_spice/spice_essential_gates.h | 10 ++ openfpga/src/fpga_spice/spice_submodule.cpp | 12 +- openfpga/src/fpga_spice/spice_submodule.h | 6 +- 7 files changed, 193 insertions(+), 10 deletions(-) diff --git a/openfpga/src/base/openfpga_spice.cpp b/openfpga/src/base/openfpga_spice.cpp index 2b99d33e8..4ef4058ee 100644 --- a/openfpga/src/base/openfpga_spice.cpp +++ b/openfpga/src/base/openfpga_spice.cpp @@ -39,7 +39,7 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx, int status = CMD_EXEC_SUCCESS; status = fpga_fabric_spice(openfpga_ctx.module_graph(), openfpga_ctx.mutable_spice_netlists(), - openfpga_ctx.arch().tech_lib, + openfpga_ctx.arch(), options); return status; diff --git a/openfpga/src/fpga_spice/spice_api.cpp b/openfpga/src/fpga_spice/spice_api.cpp index ab65794ac..658d43851 100644 --- a/openfpga/src/fpga_spice/spice_api.cpp +++ b/openfpga/src/fpga_spice/spice_api.cpp @@ -39,7 +39,7 @@ namespace openfpga { ********************************************************************/ int fpga_fabric_spice(const ModuleManager& module_manager, NetlistManager& netlist_manager, - const TechnologyLibrary& tech_lib, + const Arch& openfpga_arch, const FabricSpiceOption& options) { vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n"); @@ -71,7 +71,8 @@ int fpga_fabric_spice(const ModuleManager& module_manager, int status = CMD_EXEC_SUCCESS; status = print_spice_submodule(netlist_manager, - tech_lib, + module_manager, + openfpga_arch, submodule_dir_path); if (CMD_EXEC_SUCCESS != status) { diff --git a/openfpga/src/fpga_spice/spice_api.h b/openfpga/src/fpga_spice/spice_api.h index a214ac652..cf1ce5a0a 100644 --- a/openfpga/src/fpga_spice/spice_api.h +++ b/openfpga/src/fpga_spice/spice_api.h @@ -9,7 +9,7 @@ #include #include "netlist_manager.h" #include "module_manager.h" -#include "technology_library.h" +#include "openfpga_arch.h" #include "fabric_spice_options.h" /******************************************************************** @@ -21,7 +21,7 @@ namespace openfpga { int fpga_fabric_spice(const ModuleManager& module_manager, NetlistManager& netlist_manager, - const TechnologyLibrary& tech_lib, + const Arch& openfpga_arch, const FabricSpiceOption& options); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp index b21b98b59..e6230b531 100644 --- a/openfpga/src/fpga_spice/spice_essential_gates.cpp +++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp @@ -18,6 +18,7 @@ #include "openfpga_digest.h" #include "spice_constants.h" +#include "spice_writer_utils.h" #include "spice_essential_gates.h" /* begin namespace openfpga */ @@ -82,7 +83,7 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager, check_file_stream(spice_fname.c_str(), fp); /* Create file */ - VTR_LOG("Generating SPICE netlist '%s' for transistor wrappers...", + VTR_LOG("Generating SPICE netlist '%s' for essential gates...", spice_fname.c_str()); /* Iterate over the transistor models */ @@ -110,4 +111,165 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager, return CMD_EXEC_SUCCESS; } +/************************************************ + * Generate the SPICE subckt for an inverter + * Schematic + * LVDD + * | + * - + * +-o|| + * | - + * | | + * in-->+ +--> OUT + * | | + * | - + * +--|| + * - + * | + * LGND + * + ***********************************************/ +static +int print_spice_inverter_subckt(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const TechnologyLibrary& tech_lib, + const TechnologyModelId& tech_model) { + if (false == valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + /* Print the inverter subckt definition */ + print_spice_subckt_definition(fp, module_manager, module_id); + + /* Find the input and output ports: + * we do NOT support global ports here, + * it should be handled in another type of inverter subckt (power-gated) + */ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true); + + /* Make sure: + * There is only 1 input port and 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* TODO: may consider use size/bin to compact layout etc. */ + for (size_t i = 0; i < circuit_lib.buffer_size(circuit_model); ++i) { + /* Write transistor pairs using the technology model */ + fp << "Xpmos_" << i << " "; + fp << circuit_lib.port_prefix(output_ports[0]) << " "; + fp << circuit_lib.port_prefix(input_ports[0]) << " "; + fp << "LVDD "; + fp << "LVDD "; + fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; + + fp << "Xnmos_" << i << " "; + fp << circuit_lib.port_prefix(output_ports[0]) << " "; + fp << circuit_lib.port_prefix(input_ports[0]) << " "; + fp << "LGND "; + fp << "LGND "; + fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; + } + + print_spice_subckt_end(fp, module_manager.module_name(module_id)); + + return CMD_EXEC_SUCCESS; +} + +/************************************************ + * Generate the SPICE netlist for essential gates: + * - inverters and their templates + * - buffers and their templates + * - pass-transistor or transmission gates + * - logic gates + ***********************************************/ +int print_spice_essential_gates(NetlistManager& netlist_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const TechnologyLibrary& tech_lib, + const std::map& circuit_tech_binding, + const std::string& submodule_dir) { + std::string spice_fname = submodule_dir + std::string(ESSENTIALS_SPICE_FILE_NAME); + + std::fstream fp; + + /* Create the file stream */ + fp.open(spice_fname, std::fstream::out | std::fstream::trunc); + /* Check if the file stream if valid or not */ + check_file_stream(spice_fname.c_str(), fp); + + /* Create file */ + VTR_LOG("Generating SPICE netlist '%s' for transistor wrappers...", + spice_fname.c_str()); + + int status = CMD_EXEC_SUCCESS; + + /* Iterate over the circuit models */ + for (const CircuitModelId& circuit_model : circuit_lib.models()) { + /* Bypass models require extern netlists */ + if (true == circuit_lib.model_circuit_netlist(circuit_model).empty()) { + continue; + } + + /* Spot module id */ + const ModuleId& module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); + + TechnologyModelId tech_model; + /* Focus on inverter/buffer/pass-gate/logic gates only */ + if ( (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) + || (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) + || (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model))) { + auto result = circuit_tech_binding.find(circuit_model); + if (result == circuit_tech_binding.end()) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Unable to find technology binding for circuit model '%s'!\n", + circuit_lib.model_name(circuit_model).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + /* Valid technology binding. Assign techology model */ + tech_model = result->second; + /* Ensure we have a valid technology model */ + VTR_ASSERT(true == tech_lib.valid_model_id(tech_model)); + VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == tech_lib.model_type(tech_model)); + } + + /* Now branch on netlist writing */ + if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { + if (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) { + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); + status = print_spice_inverter_subckt(fp, + module_manager, module_id, + circuit_lib, circuit_model, + tech_lib, tech_model); + } else { + VTR_ASSERT(CIRCUIT_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model)); + } + + if (CMD_EXEC_FATAL_ERROR == status) { + break; + } + + /* Finish, go to the next */ + continue; + } + } + + /* Close file handler*/ + fp.close(); + + /* Add fname to the netlist name list */ + NetlistId nlist_id = netlist_manager.add_netlist(spice_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); + + VTR_LOG("Done\n"); + + return status; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_spice/spice_essential_gates.h b/openfpga/src/fpga_spice/spice_essential_gates.h index 055a8a55f..de9ab3cdb 100644 --- a/openfpga/src/fpga_spice/spice_essential_gates.h +++ b/openfpga/src/fpga_spice/spice_essential_gates.h @@ -5,7 +5,10 @@ * Include header files that are required by function declaration *******************************************************************/ #include +#include #include "netlist_manager.h" +#include "module_manager.h" +#include "circuit_library.h" #include "technology_library.h" /******************************************************************** @@ -19,6 +22,13 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager, const TechnologyLibrary& tech_lib, const std::string& submodule_dir); +int print_spice_essential_gates(NetlistManager& netlist_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const TechnologyLibrary& tech_lib, + const std::map& circuit_tech_binding, + const std::string& submodule_dir); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/fpga_spice/spice_submodule.cpp b/openfpga/src/fpga_spice/spice_submodule.cpp index e99a0feda..4de678af5 100644 --- a/openfpga/src/fpga_spice/spice_submodule.cpp +++ b/openfpga/src/fpga_spice/spice_submodule.cpp @@ -28,15 +28,23 @@ namespace openfpga { * 6. TODO: Configuration memory blocks ********************************************************************/ int print_spice_submodule(NetlistManager& netlist_manager, - const TechnologyLibrary& tech_lib, + const ModuleManager& module_manager, + const Arch& openfpga_arch, const std::string& submodule_dir) { int status = CMD_EXEC_SUCCESS; status = print_spice_transistor_wrapper(netlist_manager, - tech_lib, + openfpga_arch.tech_lib, submodule_dir); + status = print_spice_essential_gates(netlist_manager, + module_manager, + openfpga_arch.circuit_lib, + openfpga_arch.tech_lib, + openfpga_arch.circuit_tech_binding, + submodule_dir); + return status; } diff --git a/openfpga/src/fpga_spice/spice_submodule.h b/openfpga/src/fpga_spice/spice_submodule.h index bea004b6d..27a49de87 100644 --- a/openfpga/src/fpga_spice/spice_submodule.h +++ b/openfpga/src/fpga_spice/spice_submodule.h @@ -5,7 +5,8 @@ * Include header files that are required by function declaration *******************************************************************/ #include "netlist_manager.h" -#include "technology_library.h" +#include "module_manager.h" +#include "openfpga_arch.h" /******************************************************************** * Function declaration @@ -15,7 +16,8 @@ namespace openfpga { int print_spice_submodule(NetlistManager& netlist_manager, - const TechnologyLibrary& tech_lib, + const ModuleManager& module_manager, + const Arch& openfpga_arch, const std::string& submodule_dir); } /* end namespace openfpga */ From 3b6cd885f3f4c372a5b92e12a85faa12d17298f4 Mon Sep 17 00:00:00 2001 From: ganeshgore Date: Wed, 22 Jul 2020 11:57:04 -0600 Subject: [PATCH 04/14] BugFix: Fixed yosys_vpr with openFPGA_Shell --- openfpga_flow/scripts/run_fpga_flow.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 9975a506d..9ab384cc4 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -419,6 +419,17 @@ def prepare_run_directory(run_dir): with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile: archfile.write(tmpl.substitute(script_env_vars["PATH"])) + # Sanitize provided openshell template, if provided + if (args.openfpga_shell_template): + if not os.path.isfile(args.openfpga_shell_template or ""): + logger.error("Openfpga shell file - %s" % + args.openfpga_shell_template) + clean_up_and_exit("Provided openfpga_shell_template" + + f" {args.openfpga_shell_template} file not found") + else: + shutil.copy(args.openfpga_shell_template, + args.top_module+"_template.openfpga") + # Create benchmark dir in run_dir and copy flattern architecture file os.mkdir("benchmark") try: @@ -600,17 +611,6 @@ def collect_files_for_vpr(): clean_up_and_exit("Provided base_verilog file not found") shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v") - # Sanitize provided openshell template, if provided - if (args.openfpga_shell_template): - if not os.path.isfile(args.openfpga_shell_template or ""): - logger.error("Openfpga shell file - %s" % - args.openfpga_shell_template) - clean_up_and_exit("Provided openfpga_shell_template" + - f" {args.openfpga_shell_template} file not found") - else: - shutil.copy(args.openfpga_shell_template, - args.top_module+"_template.openfpga") - def run_vpr(): ExecTime["VPRStart"] = time.time() From d8804f4ec12dc5b0de1d2beef55c34697da490a0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 12:21:59 -0600 Subject: [PATCH 05/14] deploy yosys_vpr flow to basic regression tests --- .../full_testbench/configuration_chain/config/task.conf | 6 +++--- .../full_testbench/configuration_frame/config/task.conf | 6 +++--- .../fast_configuration_chain/config/task.conf | 6 +++--- .../fast_configuration_frame/config/task.conf | 6 +++--- .../tasks/full_testbench/fast_memory_bank/config/task.conf | 6 +++--- .../tasks/full_testbench/flatten_memory/config/task.conf | 6 +++--- .../tasks/full_testbench/memory_bank/config/task.conf | 6 +++--- 7 files changed, 21 insertions(+), 21 deletions(-) diff --git a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf index 9b21a6a26..945d99b1b 100644 --- a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf index dab7a9e3c..8188a3d5d 100644 --- a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf index 8fabc7635..5785df9ed 100644 --- a/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf index 5ef4a8a2a..afde541fa 100644 --- a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf index feb5f4372..65e7a3808 100644 --- a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf index 45946b434..69c7afd5d 100644 --- a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf index 94957ac84..0c74ddfd4 100644 --- a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From b96cdbf857ceaf5d25e998e06696968f2735b751 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 12:23:39 -0600 Subject: [PATCH 06/14] adapt preconfig test cases to use yosys_vpr flow --- .../configuration_chain/config/task.conf | 6 +++--- .../configuration_frame/config/task.conf | 6 +++--- .../preconfig_testbench/flatten_memory/config/task.conf | 6 +++--- .../tasks/preconfig_testbench/memory_bank/config/task.conf | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf index 53354162b..7f113ce06 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf index dca01bcfd..a527516e5 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf index a413be671..1b1b3108e 100644 --- a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf index bb9f7c11f..1d8ef602e 100644 --- a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 1d36de817fb68e2fcfd75e1cb9b987f207310e26 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 12:24:34 -0600 Subject: [PATCH 07/14] adapt generate bitstream testcase to use yosys vpr flow --- openfpga_flow/tasks/generate_bitstream/config/task.conf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/generate_bitstream/config/task.conf b/openfpga_flow/tasks/generate_bitstream/config/task.conf index e684dd543..c65544acc 100644 --- a/openfpga_flow/tasks/generate_bitstream/config/task.conf +++ b/openfpga_flow/tasks/generate_bitstream/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,7 +27,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 7d39e136a4327cc3b925e4d5c253983b0828bde8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 12:33:52 -0600 Subject: [PATCH 08/14] enrich micro benchmarks --- .../micro_benchmark/FSM_three_code/FSM_hour.v | 81 +++++++ .../FSM_three_code/FSM_minute.v | 80 +++++++ .../FSM_three_code/FSM_second.v | 70 ++++++ .../FSM_three_code/FSM_three_tb.v | 34 +++ .../micro_benchmark/FSM_three_code/FSM_top.v | 37 +++ .../micro_benchmark/RISC_posedge_clk/ALU.v | 27 +++ .../RISC_posedge_clk/Controller.v | 211 ++++++++++++++++++ .../micro_benchmark/RISC_posedge_clk/IR.v | 13 ++ .../micro_benchmark/RISC_posedge_clk/Memory.v | 61 +++++ .../micro_benchmark/RISC_posedge_clk/Mux_31.v | 20 ++ .../micro_benchmark/RISC_posedge_clk/Mux_51.v | 22 ++ .../micro_benchmark/RISC_posedge_clk/PC.v | 17 ++ .../RISC_posedge_clk/RISC_core_mem_top.v | 23 ++ .../RISC_posedge_clk/RISC_core_top.v | 48 ++++ .../RISC_posedge_clk/RISC_testbench.v | 53 +++++ .../RISC_posedge_clk/Reg_1bit.v | 16 ++ .../RISC_posedge_clk/Reg_8bit.v | 16 ++ .../benchmarks/micro_benchmark/SAPone/ACC.v | 19 ++ .../micro_benchmark/SAPone/ADDSUB.v | 13 ++ .../micro_benchmark/SAPone/BRegister.v | 13 ++ .../micro_benchmark/SAPone/Controller.v | 119 ++++++++++ .../benchmarks/micro_benchmark/SAPone/IR.v | 21 ++ .../benchmarks/micro_benchmark/SAPone/MAR.v | 13 ++ .../micro_benchmark/SAPone/OutputRegister.v | 13 ++ .../benchmarks/micro_benchmark/SAPone/PC.v | 15 ++ .../benchmarks/micro_benchmark/SAPone/ROM.v | 26 +++ .../micro_benchmark/SAPone/SAPone.v | 100 +++++++++ .../micro_benchmark/SAPone/testSAPone.v | 34 +++ .../micro_benchmark/counter/counter.v | 16 ++ .../counter/counter_output_verilog.v | 84 ------- .../counter/counter_post_yosys.blif | 69 ------ .../counter/counter_pre_vpr.act | 20 -- .../micro_benchmark/counter/counter_tb.v | 24 ++ 33 files changed, 1255 insertions(+), 173 deletions(-) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter/counter.v delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v new file mode 100644 index 000000000..f976a60d6 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v @@ -0,0 +1,81 @@ +module FSM_hour( + input wire rst, + input wire clk, + input wire [5:0] hour_in, + input wire hour_in_load, + input wire [5:0] min_count, + input wire [5:0] sec_count, + output reg [5:0] hour_out); + + reg [2:0] ps, ns; + wire [5:0] hour_data_add; + reg [5:0] hour_data; + reg [5:0] hour_ps, hour_ns; + reg [1:0] hour_sel; + wire hour_count; + + always@(posedge clk) + begin + if(rst) ps <= 3'd0; + else ps <= ns; + end + + always@(posedge clk) + begin + if(rst) hour_ps <= 6'd0; + else hour_ps <= hour_ns; + end + + always@(*) + begin + hour_sel = 2'd0; + case(ps) + 3'd0: begin + ns = 3'd1; + end + 3'd1: begin + if(hour_in_load) begin + hour_sel = 2'd1; + hour_out = hour_data; + ns = 3'd2; + hour_ns = hour_data; + end + else ns = 3'd1; + end + 3'd2: begin + if(hour_count == 1'd1) begin + if(hour_data == 6'd59) begin + hour_out = hour_data; + ns = 3'd2; + hour_ns = 6'd0; + end + else begin + hour_out = hour_data; + ns = 3'd2; + hour_ns = hour_data_add; + end + end + else begin + hour_out = hour_data; + hour_ns = hour_data; + ns = 3'd2; + end + end + default: begin + ns = 3'd0; + end + endcase + end + + assign hour_data_add = hour_data + 1; + assign hour_count = ((sec_count == 6'd59)&&(min_count == 6'd59)) ? 1'd1 : 1'd0; + + always@(*) + begin + case(hour_sel) + 2'd0: hour_data = hour_ps; + 2'd1: hour_data = hour_in; + endcase + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v new file mode 100644 index 000000000..0f67682ad --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v @@ -0,0 +1,80 @@ +module FSM_minute( + input wire rst, + input wire clk, + input wire [5:0] min_in, + input wire min_in_load, + input wire [5:0] sec_count, + output reg [5:0] min_out); + + reg [2:0] ps, ns; + wire [5:0] min_data_add; + reg [5:0] min_data; + reg [5:0] min_ps, min_ns; + reg [1:0] min_sel; + wire min_count; + + always@(posedge clk) + begin + if(rst) ps <= 3'd0; + else ps <= ns; + end + + always@(posedge clk) + begin + if(rst) min_ps <= 6'd0; + else min_ps <= min_ns; + end + + always@(*) + begin + min_sel = 2'd0; + case(ps) + 3'd0: begin + ns = 3'd1; + end + 3'd1: begin + if(min_in_load) begin + min_sel = 2'd1; + min_out = min_data; + ns = 3'd2; + min_ns = min_data; + end + else ns = 3'd1; + end + 3'd2: begin + if(min_count == 1'd1) begin + if(min_data == 6'd59) begin + min_out = min_data; + ns = 3'd2; + min_ns = 6'd0; + end + else begin + min_out = min_data; + ns = 3'd2; + min_ns = min_data_add; + end + end + else begin + min_out = min_data; + min_ns = min_data; + ns = 3'd2; + end + end + default: begin + ns = 3'd0; + end + endcase + end + + assign min_data_add = min_data + 1; + assign min_count = (sec_count == 6'd59) ? 1'd1 : 1'd0; + + always@(*) + begin + case(min_sel) + 2'd0: min_data = min_ps; + 2'd1: min_data = min_in; + endcase + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v new file mode 100644 index 000000000..5837d47e6 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v @@ -0,0 +1,70 @@ +module FSM_second( + input wire rst, + input wire clk, + input wire [5:0] sec_in, + input wire sec_in_load, + output reg [5:0] sec_out); + + reg [2:0] ps, ns; + wire [5:0] sec_data_add; + reg [5:0] sec_data; + reg [5:0] sec_ps, sec_ns; + reg [1:0] sec_sel; + + always@(posedge clk) + begin + if(rst) ps <= 3'd0; + else ps <= ns; + end + + always@(posedge clk) + begin + if(rst) sec_ps <= 6'd0; + else sec_ps <= sec_ns; + end + + always@(*) + begin + sec_sel = 2'd0; + case(ps) + 3'd0: begin + ns = 3'd1; + end + 3'd1: begin + if(sec_in_load) begin + sec_sel = 2'd1; + sec_out = sec_data; + ns = 3'd2; + sec_ns = sec_data_add; + end + else ns = 3'd1; + end + 3'd2: begin + if(sec_data == 6'd59) begin + sec_out = sec_data; + ns = 3'd2; + sec_ns = 6'd0; + end + else begin + sec_out = sec_data; + ns = 3'd2; + sec_ns = sec_data_add; + end + end + default: begin + ns = 3'd0; + end + endcase + end + + assign sec_data_add = sec_data + 1; + + always@(*) + begin + case(sec_sel) + 2'd0: sec_data = sec_ps; + 2'd1: sec_data = sec_in; + endcase + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v new file mode 100644 index 000000000..f8e4f498d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v @@ -0,0 +1,34 @@ +module FSM_three_tb; + + reg rst; + reg clk; + reg [5:0] sec_in, min_in, hour_in; + reg load_in; + wire [5:0] sec_out, min_out, hour_out; + + FSM_top FSM_1( + .rst(rst), + .clk(clk), + .sec_in(sec_in), + .load_in(load_in), + .sec_out(sec_out), + .min_in(min_in), + .min_out(min_out), + .hour_in(hour_in), + .hour_out(hour_out)); + + initial begin + #0 rst = 1'd1; clk = 1'd0; load_in = 1'd1; sec_in = 6'd33; min_in = 6'd14; hour_in = 6'd5; + #100 rst = 1'd0; + #50 load_in = 1'd0; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #100000 $stop; + end + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v new file mode 100644 index 000000000..2587af165 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v @@ -0,0 +1,37 @@ +module FSM_top( + input wire rst, + input wire clk, + input wire load_in, + input wire [5:0] sec_in, + input wire [5:0] min_in, + input wire [5:0] hour_in, + output wire [5:0] sec_out, + output wire [5:0] min_out, + output wire [5:0] hour_out + ); + + FSM_second FSM_sec( + .rst(rst), + .clk(clk), + .sec_in(sec_in), + .sec_in_load(load_in), + .sec_out(sec_out)); + + FSM_minute FSM_min( + .rst(rst), + .clk(clk), + .min_in(min_in), + .min_in_load(load_in), + .sec_count(sec_out), + .min_out(min_out)); + + FSM_hour FSM_hr( + .rst(rst), + .clk(clk), + .hour_in(hour_in), + .hour_in_load(load_in), + .min_count(min_out), + .hour_out(hour_out), + .sec_count(sec_out)); + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v new file mode 100644 index 000000000..798446a64 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v @@ -0,0 +1,27 @@ +module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code); + +output zero_flag_out; +output reg [7:0]alu_out; +input [7:0]Reg_Y_in,Bus_1_in; +input [7:0]IR_code; + +wire [3:0]opcode=IR_code[7:4]; + + + +always@(*) + begin + case(opcode) + 1: alu_out=Reg_Y_in+Bus_1_in; + 2: alu_out=Bus_1_in+~(Reg_Y_in)+1; + 3: alu_out=Reg_Y_in&(Bus_1_in); + 4: alu_out=~(Bus_1_in); + default:alu_out=8'b0; + endcase + end + +assign zero_flag_out=~|alu_out; + +endmodule + + \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v new file mode 100644 index 000000000..eae6c7ceb --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v @@ -0,0 +1,211 @@ +module Controller(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC, +Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,write, +zero,instruction,nclk,rst); + + +//็‹€ๆ…‹ +parameter S_idle=0,S_fet1=1,S_fet2=2,S_dec=3, + S_ex1=4,S_rd1=5,S_rd2=6,S_wr1=7,S_wr2=8, + S_br1=9,S_br2=10,S_halt=11; +//ๆŒ‡ไปค +parameter NOP=0,ADD=1,SUB=2,AND=3,NOT=4, + RD=5,WR=6,BR=7,BRZ=8; + + +output reg L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC, + L_IR,L_ADD_R,L_R_Y,L_R_Z,write; +output reg[2:0]Sel_Bus1; +output reg [1:0]Sel_Bus2; + +input zero,nclk,rst; +input [7:0]instruction; + +reg [15:0]Con_out; +reg [3:0]PS,NS; +reg err_flag; + +wire [1:0]src=instruction[3:2]; +wire [1:0]dest=instruction[1:0]; +wire [3:0]opcode=instruction[7:4]; + +always@(posedge nclk) + begin + if(rst==1)PS<=0; + else PS<=NS; + end + +always@(PS,opcode,src,dest,zero) + begin + L_R0=0; + L_R1=0; + L_R2=0; + L_R3=0; + L_PC=0; + Inc_PC=0; + Sel_Bus1=0; + L_IR=0; + L_ADD_R=0; + L_R_Y=0; + L_R_Z=0; + Sel_Bus2=0; + write=0; + err_flag=0; + case(PS) + S_idle: NS=S_fet1; + + S_fet1: begin + NS=S_fet2; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=2'b01;//Sel_Bus1 + L_ADD_R=1; + end + + S_fet2: begin + NS=S_dec; + Sel_Bus2=2'b10;//Sel_Mem + L_IR=1; + Inc_PC=1; + end + + S_dec: begin + case(opcode) + NOP:NS=S_fet1; + ADD,SUB,AND:begin + NS=S_ex1; + Sel_Bus2=2'b01;//Sel_Bus1 + L_R_Y=1; + case(src) + 0: Sel_Bus1=3'b000;//R0 + 1: Sel_Bus1=3'b001;//R1 + 2: Sel_Bus1=3'b010;//R2 + 3: Sel_Bus1=3'b011;//R3 + default err_flag=1; + endcase + end//ADD,SUB,AND + + NOT:begin + NS=S_fet1; + L_R_Z=1; + Sel_Bus2=2'b00;//Sel_ALU + case(src) + 0: Sel_Bus1=3'b000;//R0 + 1: Sel_Bus1=3'b001;//R1 + 2: Sel_Bus1=3'b010;//R2 + 3: Sel_Bus1=3'b011;//R3 + default err_flag=1; + endcase + case(dest) + 0: L_R0=1; + 1: L_R1=1; + 2: L_R2=1; + 3: L_R3=1; + default err_flag=1; + endcase + end//NOT + + RD: begin + NS=S_rd1; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=3'b001;//Sel_Bus1 + L_ADD_R=1; + end//RD + + WR: begin + NS=S_wr1; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=3'b001;//Sel_Bus1 + L_ADD_R=1; + end//WR + + BR: begin + NS=S_br1; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=3'b001;//Sel_Bus1 + L_ADD_R=1; + end//BR + + BRZ:begin + if(zero==1)begin + NS=S_br1; + Sel_Bus1=3'b100;//Sel_PC + Sel_Bus2=3'b001;//Sel_Bus1 + L_ADD_R=1; + end + else begin + NS=S_fet1; + Inc_PC=1; + end + end//BRZ + + default NS=S_halt; + + endcase//opcode + end + + S_ex1: begin + NS=S_fet1; + L_R_Z=1; + Sel_Bus2=2'b00;//Sel_ALU + case(dest) + 0: begin Sel_Bus1=3'b000;L_R0=1;end + 1: begin Sel_Bus1=3'b001;L_R1=1;end + 2: begin Sel_Bus1=3'b010;L_R2=1;end + 3: begin Sel_Bus1=3'b011;L_R3=1;end + default err_flag=1; + endcase + end + + S_rd1: begin + NS=S_rd2; + Inc_PC=1; + Sel_Bus2=2'b10;//Sel_Mem + L_ADD_R=1; + end + + S_wr1: begin + NS=S_wr2; + Inc_PC=1; + Sel_Bus2=2'b10;//Sel_Mem + L_ADD_R=1; + end + + S_rd2: begin + NS=S_fet1; + Sel_Bus2=2'b10;//Sel_Mem + case(dest) + 0: L_R0=1; + 1: L_R1=1; + 2: L_R2=1; + 3: L_R3=1; + default err_flag=1; + endcase + end + + S_wr2: begin + NS=S_fet1; + write=1; + case(src) + 0: Sel_Bus1=3'b000;//R0 + 1: Sel_Bus1=3'b001;//R1 + 2: Sel_Bus1=3'b010;//R2 + 3: Sel_Bus1=3'b011;//R3 + default err_flag=1; + endcase + end + + S_br1: begin + NS=S_br2; + Sel_Bus2=2'b10;//Sel_Mem + L_ADD_R=1; + end + + S_br2: begin + NS=S_fet1; + Sel_Bus2=2'b10;//Sel_Mem + L_PC=1; + end + S_halt: NS=S_halt; + default NS=S_idle; + endcase + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v new file mode 100644 index 000000000..cdf41abfc --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v @@ -0,0 +1,13 @@ +module IR(IR_out,IR_in,load,clk,rst); + +output reg [7:0]IR_out; +input [7:0]IR_in; +input load,clk,rst; + +always@(posedge clk) + begin + if(rst==1)IR_out<=8'b0; + else if(load==1)IR_out<=IR_in; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v new file mode 100644 index 000000000..3f25916e2 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v @@ -0,0 +1,61 @@ +module Memory(Data_out,Address); + + output [7:0]Data_out; + input [7:0]Address; + + reg [7:0]mem[255:0]; + assign Data_out=mem[Address]; + + always@(Address) + begin + case(Address) + //opcode_src_dest + //NOP + 0: mem[Address]=8'b0000_00_00; + + //rd 00 10 //Read MEM[130] to R2 + 1: mem[Address]=8'b0101_00_10; //Instruction + 2: mem[Address]=130; //Address + + //rd 00 11 //Read MEM[131] to R3 + 3: mem[Address]=8'b0101_00_11; //Instruction + 4: mem[Address]=131; //Address + + //rd 00 01 //Read MEM[128] to R1 + 5: mem[Address]=8'b0101_00_01; //Instruction + 6: mem[Address]=128; //Address + + //rd 00 00 //Read MEM[129] to R0 + 7: mem[Address]=8'b0101_00_00; //Instruction + 8: mem[Address]=129; //Address + + //Sub 00 01 //Sub R1-R0 to R1 + 9: mem[Address]=8'b0010_00_01; //Instruction + + //BRZ 00 00 + 10: mem[Address]=8'b1000_00_00; //Instruction + 11: mem[Address]=134; //Address + + //Add 10 11 //Add R2+R3 to R3 + 12: mem[Address]=8'b00011011; + + //BR + 13: mem[Address]=8'b01110011; //Instruction + 14: mem[Address]=140; //Address + + 128:mem[Address]=6; + 129:mem[Address]=1; + 130:mem[Address]=2; + 131:mem[Address]=0; + 134:mem[Address]=139; //Address + 135:mem[Address]=0; + //HAL + 139:mem[Address]=8'b1111_00_00; //Instruction + 140:mem[Address]=9; //Address + default mem[Address]=8'bx; + endcase + end + +endmodule + + \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v new file mode 100644 index 000000000..1f678f02b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v @@ -0,0 +1,20 @@ +module Mux_31(Y,A0,A1,A2,sel); + +output [7:0]Y; +input [7:0]A2,A1,A0; +input [1:0]sel; + +reg [7:0]Y; + +always@(*) + begin + case(sel) + 0: Y=A0; + 1: Y=A1; + 2: Y=A2; + default:Y=8'bz; + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v new file mode 100644 index 000000000..213069454 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v @@ -0,0 +1,22 @@ +module Mux_51(Y,A0,A1,A2,A3,A4,sel); + +output [7:0]Y; +input [7:0]A4,A3,A2,A1,A0; +input [2:0]sel; + +reg [7:0]Y; + +always@(*) + begin + case(sel) + 0: Y=A0; + 1: Y=A1; + 2: Y=A2; + 3: Y=A3; + 4: Y=A4; + default:Y=8'bx; + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v new file mode 100644 index 000000000..f82c44e92 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v @@ -0,0 +1,17 @@ +module PC(PC_out,PC_in,load,inc,clk,rst); + +output [7:0]PC_out; +input [7:0]PC_in; +input load,inc,clk,rst; + +reg [7:0]PC_out; + +always@(posedge clk) + begin + if(rst==1)PC_out<=8'b0; + else if(load==1)PC_out<=PC_in; + else if(inc==1)PC_out<=PC_out+8'b00000001; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v new file mode 100644 index 000000000..910b52408 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v @@ -0,0 +1,23 @@ +module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst); + +output [7:0]bus_1_out; +input clk,rst; +output [7:0]Reg_R0_out; +output [7:0]Reg_R1_out; +output [7:0]Reg_R2_out; +output [7:0]Reg_R3_out; + +wire [7:0]bus_1_out,MEMAddress; +wire clk,rst; +wire [7:0]MEMdataout; +wire [7:0]Reg_R0_out; +wire [7:0]Reg_R1_out; +wire [7:0]Reg_R2_out; +wire [7:0]Reg_R3_out; + + +RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress); + +Memory MEM(MEMdataout,MEMAddress); + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v new file mode 100644 index 000000000..a12b867b1 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v @@ -0,0 +1,48 @@ +module RISC_core_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress); + +output [7:0]bus_1_out,MEMAddress; +input clk,rst; +input [7:0]MEMdataout; +output [7:0]Reg_R0_out; +output [7:0]Reg_R1_out; +output [7:0]Reg_R2_out; +output [7:0]Reg_R3_out; + +wire [7:0]BUS_2,BUS_1,MEMAddress; +wire [7:0]alu_out; +wire [7:0]MEMdataout; +wire [7:0]Reg_Y_out,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out; +wire [7:0]IR_out; +wire zero_flag_out; +wire [2:0]Sel_Bus1; +wire [1:0]Sel_Bus2; +wire L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,L_IR,L_ADD_R,L_R_Y,L_R_Z,MEMwrite,zero; + +assign bus_1_out=BUS_1; +assign bus_2_out=BUS_2; + +Controller CON(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,MEMwrite,zero,IR_out,clk,rst); +//module PC(PC_out,PC_in,load,inc,clk,rst); +PC Program_Counter(PC_out,BUS_2,L_PC,Inc_PC,clk,rst); +//module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code); +ALU Arithmetic_Logic_Unit(zero_flag_out,alu_out,Reg_Y_out,BUS_1,IR_out); +//module Memory(Data_out,Data_in,MEMAddress,clk,MEMwrite); +//Memory MEM(MEMdataout,BUS_1,MEMAddress,clk,MEMwrite); +//module Mux_31(Y,A0,A1,A2,sel); +Mux_31 Mux31(BUS_2,alu_out,BUS_1,MEMdataout,Sel_Bus2); +//module Reg_1bit(Q,D,load,clk,rst); +Reg_1bit Reg_Z(zero,zero_flag_out,L_R_Z,clk,rst); +//module Reg_8bit(Q,D,load,clk,rst); +Reg_8bit Reg_Y(Reg_Y_out,BUS_2,L_R_Y,clk,rst); +Reg_8bit Add_R(MEMAddress,BUS_2,L_ADD_R,clk,rst); +//R0~R3 +Reg_8bit Reg_R0(Reg_R0_out,BUS_2,L_R0,clk,rst); +Reg_8bit Reg_R1(Reg_R1_out,BUS_2,L_R1,clk,rst); +Reg_8bit Reg_R2(Reg_R2_out,BUS_2,L_R2,clk,rst); +Reg_8bit Reg_R3(Reg_R3_out,BUS_2,L_R3,clk,rst); +//module Mux_51(Y,A0,A1,A2,A3,A4,sel); +Mux_51 Mux51(BUS_1,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out,Sel_Bus1); +//module IR(IR_out,IR_in,load,clk,rst); +IR Instruction_Register(IR_out,BUS_2,L_IR,clk,rst); + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v new file mode 100644 index 000000000..371c84da3 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v @@ -0,0 +1,53 @@ +`timescale 1ns/1ns + +module RISC_testbench; + +wire [7:0]bus_1_out; +reg clk,rst; +wire [7:0]Reg_R0_out; +wire [7:0]Reg_R1_out; +wire [7:0]Reg_R2_out; +wire [7:0]Reg_R3_out; + +/* wire [7:0]MEMAddress; +wire [7:0]MEMdataout; +wire MEMwrite; */ + +/* assign MEMAddress = top.MEMAddress; +assign MEMdataout = top.MEMdataout; +assign MEMwrite = top.MEMwrite; */ + +RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst); + + always#20 clk=~clk; + + initial + begin + clk=0;rst=1; + #30 rst=0; + #6000 $stop; + end + +/* //---------- + + integer fp; + initial + begin + fp = $fopen("RISC_xa.vec"); + + $fdisplay(fp, "radix 1 1 44 44 44 44 44 1 44 44"); + $fdisplay(fp, "vname clk rst Reg_R0_out[[7:0]] Reg_R1_out[[7:0]] Reg_R2_out[[7:0]] Reg_R3_out[[7:0]] bus_1_out[[7:0]] MEMwrite MEMAddress MEMdataout"); + $fdisplay(fp, " io i i oo oo oo oo oo o oo ii"); + $fdisplay(fp, "slope 0.3"); + $fdisplay(fp, " vih 3.3"); + $fdisplay(fp, " vil 0"); + $fdisplay(fp, "tunit ns"); + end + always@(clk) + begin + $fdisplay(fp, "%t %b %b %h %h %h %h %h %b %h %h", $time, clk, rst, Reg_R0_out, Reg_R1_out, Reg_R2_out, Reg_R3_out, bus_1_out, MEMwrite, MEMAddress, MEMdataout); + end + +//---------- */ + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v new file mode 100644 index 000000000..67bc59367 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v @@ -0,0 +1,16 @@ +module Reg_1bit(Q,D,load,clk,rst); + +output Q; +input D; +input load,clk,rst; + +reg Q; + +always@(posedge clk) + begin + if(rst==1)Q<=0; + else if(load==1)Q<=D; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v new file mode 100644 index 000000000..2b9bd810e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v @@ -0,0 +1,16 @@ +module Reg_8bit(Q,D,load,clk,rst); + +output [7:0]Q; +input [7:0]D; +input load,clk,rst; + +reg [7:0]Q; + +always@(posedge clk) + begin + if(rst==1)Q<=8'b0; + else if(load==1)Q<=D; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v new file mode 100644 index 000000000..acd178ea4 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v @@ -0,0 +1,19 @@ +module ACC( + output [7:0] acc_out1, + output [7:0] acc_out2, + input [7:0] acc_in, + input la_, + input clk, + input clr_ + ); + + reg [7:0] q; + + always @(posedge clk) + if (~clr_) q <= 8'b0; + else if(~la_) q <= acc_in; + + assign acc_out1 = q; + assign acc_out2 = q; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v new file mode 100644 index 000000000..79719f59e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v @@ -0,0 +1,13 @@ +module ADDSUB( + output [7:0] ADDSUB_out, + input [7:0] ADDSUB_in1, + input [7:0] ADDSUB_in2, + input su + ); + + wire [7:0] d; + + assign d = su ? ADDSUB_in1 - ADDSUB_in2 : ADDSUB_in1 + ADDSUB_in2; + assign ADDSUB_out = d; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v new file mode 100644 index 000000000..e8ea08b2d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v @@ -0,0 +1,13 @@ +module BRegister( + output reg [7:0] BRegister_out, + input [7:0] BRegister_in, + input lb_, + input clk, + input clr_ + ); + + always @(posedge clk) + if(~clr_) BRegister_out <= 8'b0; + else if(~lb_) BRegister_out <= BRegister_in; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v new file mode 100644 index 000000000..5a14a8f4d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v @@ -0,0 +1,119 @@ +module Controller( + output reg [11:0] control_signals, + input [3:0] opcode, + input clk, + input clr_ + ); + + reg [3:0] ps, ns; + + always @(posedge clk) + begin + if(~clr_) ps <= 4'd0; + else ps <= ns; + end + + always @(*) + begin + case(ps) + 0: + begin + control_signals = 12'h3e3; + ns = 4'd1; + end + + 1: //T1 + begin + control_signals = 12'h5e3; + ns = 4'd2; + end + + 2: //T2 + begin +// control_signals = 12'hbe3; + control_signals = 12'h863; + ns = 4'd3; + end + + 3: //T3 + begin +// control_signals = 12'h263; + control_signals = 12'h3e3; + if(opcode == 4'd0) //LDA + ns = 4'd4; + else if(opcode == 4'd1) //ADD + ns = 4'd6; + else if(opcode == 4'd2) //SUB + ns = 4'd9; + else if(opcode == 4'd14) //OUT + ns = 4'd12; + else if(opcode == 4'd15) //HLT + ns = 4'd13; + end + + 4: //LDA + begin + control_signals = 12'h1a3; + ns = 4'd5; + end + + 5: //LDA + begin + control_signals = 12'h2c3; + ns = 4'd1; + end + + 6: //ADD + begin + control_signals = 12'h1a3; + ns = 4'd7; + end + + 7: //ADD + begin + control_signals = 12'h2e1; + ns = 4'd8; + end + + 8: //ADD + begin + control_signals = 12'h3c7; + ns = 4'd1; + end + + 9: //SUB + begin + control_signals = 12'h1a3; + ns = 4'd10; + end + + 10: //SUB + begin + control_signals = 12'h2e1; + ns = 4'd11; + end + + 11: //SUB + begin + control_signals = 12'h3cf; + ns = 4'd1; + end + + 12: //OUT + begin + control_signals = 12'h3f2; + ns = 4'd1; + end + + 13: //HLT + ns = 4'd13; + + default: + begin + ns = 4'd0; + control_signals = 12'h3e3; + end + + endcase + end +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v new file mode 100644 index 000000000..f95a31453 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v @@ -0,0 +1,21 @@ +module IR( + output [7:4] opcode, + output [3:0] oprand, + input wire [7:0] IR_in, + input li_, + input clk, + input clr_ + ); + + reg [7:0] q; + + always @(posedge clk) + begin + if(~clr_) q <=8'b0; + else if(~li_) q <= IR_in; + end + + assign opcode = q[7:4]; + assign oprand = q[3:0]; + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v new file mode 100644 index 000000000..0408bf01b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v @@ -0,0 +1,13 @@ +module MAR( + output reg [3:0] mar_out, + input wire [3:0] mar_in, + input lm_, + input clk, + input clr_ + ); + + always @(posedge clk) + if(~clr_) mar_out <= 4'b0; + else if(~lm_) mar_out <= mar_in; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v new file mode 100644 index 000000000..6bc7aac2a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v @@ -0,0 +1,13 @@ +module OutputRegister( + output reg [7:0] OutputRegister_out, + input [7:0] OutputRegister_in, + input lo_, + input clk, + input clr_ + ); + + always @(posedge clk) + if(~clr_) OutputRegister_out <= 8'b0; + else if(~lo_) OutputRegister_out <= OutputRegister_in; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v new file mode 100644 index 000000000..c987145e9 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v @@ -0,0 +1,15 @@ + module PC( + output reg [3:0] pc_out, + input cp, + input clk, + input clr_ + ); + + always @(posedge clk) + begin + if(~clr_) pc_out <= 0; + else if (cp) pc_out <= pc_out + 1; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v new file mode 100644 index 000000000..5fab7744b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v @@ -0,0 +1,26 @@ +module ROM( + output reg [7:0] rom_out, + input [3:0] rom_in + ); + + always @(*) + begin + rom_out = 8'bx; + case(rom_in) + 4'b0000: rom_out = 8'b0000_1001; //LDA + 4'b0001: rom_out = 8'b0001_1010; //ADD + 4'b0010: rom_out = 8'b0001_1011; //ADD + 4'b0011: rom_out = 8'b0010_1100; //SUB + 4'b0100: rom_out = 8'b1110_xxxx; //OUT + 4'b0101: rom_out = 8'b1111_xxxx; //HLT + 4'b0110: rom_out = 8'bxxxx_xxxx; + 4'b0111: rom_out = 8'bxxxx_xxxx; + 4'b1000: rom_out = 8'bxxxx_xxxx; + 4'b1001: rom_out = 8'b0001_0000; + 4'b1010: rom_out = 8'b0001_0100; + 4'b1011: rom_out = 8'b0001_1000; + 4'b1100: rom_out = 8'b0010_0000; + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v new file mode 100644 index 000000000..63d2513b7 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v @@ -0,0 +1,100 @@ +module SAPone( + output wire [7:0] SAP_out, + output wire [11:0] con, + output reg [7:0] bus, + input clk, + input clr_ + ); + + wire cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_; + wire [7:0] acc_out2, BRegister_out, OutputRegister_out; + wire [3:0] IR_out, mar_out; + wire [4:0] bus_sel; + wire [3:0] pc_out, oprand; + wire [7:0] rom_out, acc_out1, ADDSUB_out; + + assign {cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_} = con; + assign bus_sel = {ep, ce_, ei_, ea, eu}; + + always@(*) + begin + case(bus_sel) + 5'b11100: bus[3:0] = pc_out; + 5'b00100: bus[7:0] = rom_out; + 5'b01000: bus[3:0] = oprand; + 5'b01110: bus[7:0] = acc_out1; + 5'b01101: bus[7:0] = ADDSUB_out; + default: bus[7:0] = 8'bx; + endcase + end + + PC pc1( + .pc_out(pc_out), + .cp(cp), + .clk(clk), + .clr_(clr_) + ); + + MAR mar1( + .mar_out(mar_out), + .mar_in(bus[3:0]), + .lm_(lm_), + .clk(clk), + .clr_(clr_) + ); + + ROM roml( + .rom_out(rom_out), + .rom_in(mar_out) + ); + + IR ir1( + .opcode(IR_out), + .oprand(oprand), + .IR_in(bus[7:0]), + .li_(li_), + .clk(clk), + .clr_(clr_) + ); + + Controller cont1( + .control_signals(con), + .opcode(IR_out), + .clk(clk), + .clr_(clr_) + ); + + ACC acc1( + .acc_out1(acc_out1), + .acc_out2(acc_out2), + .acc_in(bus[7:0]), + .la_(la_), + .clk(clk), + .clr_(clr_) + ); + + ADDSUB addsub1( + .ADDSUB_out(ADDSUB_out), + .ADDSUB_in1(acc_out2), + .ADDSUB_in2(BRegister_out), + .su(su) + ); + + BRegister bregister1( + .BRegister_out(BRegister_out), + .BRegister_in(bus[7:0]), + .lb_(lb_), + .clk(clk), + .clr_(clr_) + ); + + OutputRegister outputregister1( + .OutputRegister_out(SAP_out), + .OutputRegister_in(bus[7:0]), + .lo_(lo_), + .clk(clk), + .clr_(clr_) + ); + + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v new file mode 100644 index 000000000..3f0b4e4dd --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v @@ -0,0 +1,34 @@ +module testSAPone; + + wire [7:0] SAP_out; + wire [11:0] con; + wire [7:0] bus; +// wire clk_out, clr_out; + reg clk, clr_; + + always #5 clk = ~clk; + + SAPone sapone1( + .SAP_out(SAP_out), + .con(con), + .bus(bus), +// .clk_out(clk_out), +// .clr_out(clr_out), + .clk(clk), + .clr_(clr_) + ); + +// PC pc1(bus[3:0], clk, clr_, cp, ep); +// MAR mar1(mar, clk, lm_, bus[3:0]); + + initial + begin + clk = 0; clr_ = 0; + #10 clr_ = 1; + + + + #990 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v new file mode 100644 index 000000000..98a4ff291 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v @@ -0,0 +1,16 @@ +module counter_original(clk_counter, q_counter, rst_counter); + + input clk_counter; + input rst_counter; + output [7:0] q_counter; + reg [7:0] q_counter; + + always @ (posedge clk_counter) + begin + if(rst_counter) + q_counter <= 8'b00000000; + else + q_counter <= q_counter + 1; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v deleted file mode 100644 index 17896cc04..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v +++ /dev/null @@ -1,84 +0,0 @@ -/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */ - -module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] ); - wire _00_; - wire _01_; - input clk_counter; - wire n22; - wire n26; - wire n30; - wire n34; - wire n38; - wire n42; - wire n46; - wire n50; - output \q_counter[0] ; - reg \q_counter[0] ; - output \q_counter[1] ; - reg \q_counter[1] ; - output \q_counter[2] ; - reg \q_counter[2] ; - output \q_counter[3] ; - reg \q_counter[3] ; - output \q_counter[4] ; - reg \q_counter[4] ; - output \q_counter[5] ; - reg \q_counter[5] ; - output \q_counter[6] ; - reg \q_counter[6] ; - output \q_counter[7] ; - reg \q_counter[7] ; - input rst_counter; - - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[0] <= 1'b0; - else \q_counter[0] <= n22; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[1] <= 1'b0; - else \q_counter[1] <= n26; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[2] <= 1'b0; - else \q_counter[2] <= n30; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[3] <= 1'b0; - else \q_counter[3] <= n34; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[4] <= 1'b0; - else \q_counter[4] <= n38; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[5] <= 1'b0; - else \q_counter[5] <= n42; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[6] <= 1'b0; - else \q_counter[6] <= n46; - end - always @(posedge clk_counter) - begin - if(rst_counter) \q_counter[7] <= 1'b0; - else \q_counter[7] <= n50; - end - - assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter }; - assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1] }; - assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] }; - assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] }; - assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter }; - assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] }; - assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter }; - assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] }; - assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6] }; - assign n22 = 4'h1 >> { \q_counter[0] , rst_counter }; -endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif deleted file mode 100644 index ebf780381..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif +++ /dev/null @@ -1,69 +0,0 @@ -# Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 7.0.0 -fPIC -Os) - -.model counter -.inputs clk_counter rst_counter -.outputs q_counter[0] q_counter[1] q_counter[2] q_counter[3] q_counter[4] q_counter[5] q_counter[6] q_counter[7] -.names $false -.names $true -1 -.names $undef -.names q_counter[7] rst_counter q_counter[6] $abc$3686$new_n20_ $0\q_counter[7][0:0] -0011 1 -1000 1 -1001 1 -1010 1 -.names q_counter[4] q_counter[5] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n20_ -111111 1 -.names q_counter[6] $abc$3686$new_n20_ rst_counter $0\q_counter[6][0:0] -010 1 -100 1 -.names q_counter[5] $abc$3686$new_n23_ rst_counter $0\q_counter[5][0:0] -010 1 -100 1 -.names q_counter[4] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n23_ -11111 1 -.names q_counter[2] rst_counter q_counter[1] q_counter[0] $0\q_counter[2][0:0] -0011 1 -1000 1 -1001 1 -1010 1 -.names q_counter[4] rst_counter q_counter[3] q_counter[2] q_counter[1] q_counter[0] $0\q_counter[4][0:0] -001111 1 -100000 1 -100001 1 -100010 1 -100011 1 -100100 1 -100101 1 -100110 1 -100111 1 -101000 1 -101001 1 -101010 1 -101011 1 -101100 1 -101101 1 -101110 1 -.names q_counter[3] rst_counter q_counter[2] q_counter[1] q_counter[0] $0\q_counter[3][0:0] -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -.names q_counter[1] q_counter[0] rst_counter $0\q_counter[1][0:0] -010 1 -100 1 -.names q_counter[0] rst_counter $0\q_counter[0][0:0] -00 1 -.latch $0\q_counter[7][0:0] q_counter[7] re clk_counter 2 -.latch $0\q_counter[6][0:0] q_counter[6] re clk_counter 2 -.latch $0\q_counter[5][0:0] q_counter[5] re clk_counter 2 -.latch $0\q_counter[4][0:0] q_counter[4] re clk_counter 2 -.latch $0\q_counter[3][0:0] q_counter[3] re clk_counter 2 -.latch $0\q_counter[2][0:0] q_counter[2] re clk_counter 2 -.latch $0\q_counter[1][0:0] q_counter[1] re clk_counter 2 -.latch $0\q_counter[0][0:0] q_counter[0] re clk_counter 2 -.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act deleted file mode 100644 index 800b2a89e..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act +++ /dev/null @@ -1,20 +0,0 @@ -clk_counter 0.500000 2.000000 -rst_counter 0.492200 0.201800 -q_counter[0] 0.281800 0.563400 -q_counter[1] 0.248200 0.273600 -q_counter[2] 0.183200 0.125600 -q_counter[3] 0.097400 0.044800 -q_counter[4] 0.022600 0.007200 -q_counter[5] 0.002200 0.000800 -q_counter[6] 0.000000 0.000000 -q_counter[7] 0.000000 0.000000 -$0\q_counter[7][0:0] 0 0 -$0\q_counter[6][0:0] 0 0 -$0\q_counter[5][0:0] 0 0 -$0\q_counter[4][0:0] 0 0 -$0\q_counter[3][0:0] 0 0 -$0\q_counter[2][0:0] 0 0 -$0\q_counter[1][0:0] 0 0 -$0\q_counter[0][0:0] 0 0 -$abc$3686$new_n23_ 0 0 -$abc$3686$new_n20_ 0 0 diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v new file mode 100644 index 000000000..accfd8267 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v @@ -0,0 +1,24 @@ +module counter_tb; + + reg clk_counter, rst_counter; + wire [7:0] q_counter; + + counter_original C_1( + clk_counter, + q_counter, + rst_counter); + + initial begin + #0 rst_counter = 1'b1; clk_counter = 1'b0; + #100 rst_counter = 1'b0; + end + + always begin + #10 clk_counter = ~clk_counter; + end + + initial begin + #5000 $stop; + end + +endmodule \ No newline at end of file From 05dccadf21d0e3e4e777181359476315eb94294c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 12:44:19 -0600 Subject: [PATCH 09/14] bug fix in the testcases using yosys_vpr flow --- .../full_testbench/configuration_chain/config/task.conf | 5 +---- .../full_testbench/configuration_frame/config/task.conf | 5 +---- .../full_testbench/fast_configuration_chain/config/task.conf | 5 +---- .../full_testbench/fast_configuration_frame/config/task.conf | 5 +---- .../tasks/full_testbench/fast_memory_bank/config/task.conf | 5 +---- .../tasks/full_testbench/flatten_memory/config/task.conf | 5 +---- .../tasks/full_testbench/memory_bank/config/task.conf | 5 +---- openfpga_flow/tasks/generate_bitstream/config/task.conf | 4 +--- .../preconfig_testbench/configuration_chain/config/task.conf | 4 +--- .../preconfig_testbench/configuration_frame/config/task.conf | 4 +--- .../preconfig_testbench/flatten_memory/config/task.conf | 4 +--- .../tasks/preconfig_testbench/memory_bank/config/task.conf | 4 +--- 12 files changed, 12 insertions(+), 43 deletions(-) diff --git a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf index 945d99b1b..604e78631 100644 --- a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf @@ -23,14 +23,11 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf index 8188a3d5d..0edbee487 100644 --- a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf @@ -23,14 +23,11 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf index 5785df9ed..a5ce479e8 100644 --- a/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf @@ -23,14 +23,11 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf index afde541fa..68dcc1778 100644 --- a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf @@ -23,14 +23,11 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf index 65e7a3808..6d4fa16ba 100644 --- a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf @@ -23,14 +23,11 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf index 69c7afd5d..9376005d0 100644 --- a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf @@ -23,14 +23,11 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf index 0c74ddfd4..c1ed83684 100644 --- a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf @@ -23,14 +23,11 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/generate_bitstream/config/task.conf b/openfpga_flow/tasks/generate_bitstream/config/task.conf index c65544acc..4d63d929e 100644 --- a/openfpga_flow/tasks/generate_bitstream/config/task.conf +++ b/openfpga_flow/tasks/generate_bitstream/config/task.conf @@ -23,11 +23,9 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf index 7f113ce06..ac70a4fbf 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf @@ -23,12 +23,10 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf index a527516e5..57805a4ac 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf @@ -23,12 +23,10 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf index 1b1b3108e..52028e028 100644 --- a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf @@ -23,12 +23,10 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf index 1d8ef602e..c2b6bf442 100644 --- a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf @@ -23,12 +23,10 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 92c34499999029e6f15209f7170a47b4df11c760 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 13:17:05 -0600 Subject: [PATCH 10/14] bug fix in the regression test due to benchmark changes --- openfpga_flow/benchmarks/micro_benchmark/counter/counter.v | 2 +- openfpga_flow/tasks/implicit_verilog/config/task.conf | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v index 98a4ff291..216053285 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v @@ -1,4 +1,4 @@ -module counter_original(clk_counter, q_counter, rst_counter); +module counter(clk_counter, q_counter, rst_counter); input clk_counter; input rst_counter; diff --git a/openfpga_flow/tasks/implicit_verilog/config/task.conf b/openfpga_flow/tasks/implicit_verilog/config/task.conf index 5ebdd49a7..6c94a415a 100644 --- a/openfpga_flow/tasks/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/implicit_verilog/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -23,12 +23,10 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v [SYNTHESIS_PARAM] bench0_top = counter -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From f754c8af061d79f34b5d4cbb9e7b68256eae4678 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 13:45:55 -0600 Subject: [PATCH 11/14] use k6_n10 architecture to reduce CI runtime --- .../k6_frac_N8_40nm_openfpga.xml | 231 +++++++++ .../lut_design/frac_lut/config/task.conf | 4 +- .../vpr_arch/k6_frac_N8_tileable_40nm.xml | 441 ++++++++++++++++++ 3 files changed, 674 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml create mode 100644 openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml new file mode 100644 index 000000000..74d1d9933 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -0,0 +1,231 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf index 08a28be87..7eb80e932 100644 --- a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf @@ -15,12 +15,12 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] # diff --git a/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml new file mode 100644 index 000000000..a31984e8b --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 95c1fe61e1ae6ba53e46ad807fd19cd91f2f4543 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 13:49:03 -0600 Subject: [PATCH 12/14] use k6 n8 in mux design to speed up CI --- openfpga_flow/tasks/mux_design/local_encoder/config/task.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf index a9ddefc19..f34e31c44 100644 --- a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf +++ b/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf @@ -15,12 +15,12 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif From 1a1c3885e73bce43b2c0df7e928ca62c4ef6f009 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 13:54:09 -0600 Subject: [PATCH 13/14] use k6 n10 in mux designs to speed up CI --- openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf | 4 ++-- .../tasks/mux_design/tree_structure/config/task.conf | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf index 426bb8884..bd770ab87 100644 --- a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf +++ b/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf @@ -15,12 +15,12 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf index 9c63bfdbd..ccc293b69 100644 --- a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf +++ b/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf @@ -15,12 +15,12 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif From 8ade40713aeedeb3a414b848b55f4bd9c2b20e82 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 14:07:39 -0600 Subject: [PATCH 14/14] add missing architecture for CI --- ...k6_frac_N8_local_encoder_40nm_openfpga.xml | 231 ++++++++++++++++++ .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 223 +++++++++++++++++ .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 222 +++++++++++++++++ 3 files changed, 676 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml new file mode 100644 index 000000000..721fb6663 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -0,0 +1,231 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml new file mode 100644 index 000000000..da7c4b76b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -0,0 +1,223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml new file mode 100644 index 000000000..b39c7a999 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -0,0 +1,222 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +