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[core] fixed a bug in fabric bitgen due to tile modules

This commit is contained in:
tangxifan 2023-07-25 14:49:12 -07:00
parent 95a32628ab
commit 6ecbbb3a94
2 changed files with 27 additions and 7 deletions
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15
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -1314,6 +1314,11 @@ static int build_tile_module(
}
size_t pb_instance = module_manager.num_instance(tile_module, pb_module);
module_manager.add_child_module(tile_module, pb_module);
std::string pb_instance_name = generate_grid_block_instance_name(
std::string(GRID_MODULE_NAME_PREFIX), std::string(phy_tile->name),
is_io_type(phy_tile), grid_side, grid_coord);
module_manager.set_child_instance_name(tile_module, pb_module,
pb_instance, pb_instance_name);
if (0 < find_module_num_config_bits(module_manager, pb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
@ -1353,6 +1358,11 @@ static int build_tile_module(
}
size_t cb_instance = module_manager.num_instance(tile_module, cb_module);
module_manager.add_child_module(tile_module, cb_module, false);
const RRGSB& inst_rr_gsb = device_rr_gsb.get_gsb(cb_coord);
std::string cb_instance_name = generate_connection_block_module_name(
cb_type, inst_rr_gsb.get_cb_coordinate(cb_type));
module_manager.set_child_instance_name(tile_module, cb_module,
cb_instance, cb_instance_name);
if (0 < find_module_num_config_bits(module_manager, cb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
@ -1386,6 +1396,11 @@ static int build_tile_module(
}
size_t sb_instance = module_manager.num_instance(tile_module, sb_module);
module_manager.add_child_module(tile_module, sb_module, false);
const RRGSB& inst_rr_gsb = device_rr_gsb.get_gsb(sb_coord);
std::string sb_instance_name =
generate_switch_block_module_name(inst_rr_gsb.get_sb_coordinate());
module_manager.set_child_instance_name(tile_module, sb_module, sb_instance,
sb_instance_name);
if (0 < find_module_num_config_bits(module_manager, sb_module, circuit_lib,
sram_model, sram_orgz_type)) {
module_manager.add_configurable_child(tile_module, sb_module,

19
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
View File

@ -39,7 +39,7 @@ static void rec_build_module_fabric_dependent_chain_bitstream(
const ModuleManager& module_manager, const ModuleId& top_module,
const ModuleId& parent_module, const ConfigRegionId& config_region,
FabricBitstream& fabric_bitstream,
const FabricBitRegionId& fabric_bitstream_region) {
const FabricBitRegionId& fabric_bitstream_region, const bool& verbose) {
/* Depth-first search: if we have any children in the parent_block,
* we dive to the next level first!
*/
@ -69,7 +69,7 @@ static void rec_build_module_fabric_dependent_chain_bitstream(
rec_build_module_fabric_dependent_chain_bitstream(
bitstream_manager, child_block, module_manager, top_module,
child_module, config_region, fabric_bitstream,
fabric_bitstream_region);
fabric_bitstream_region, verbose);
}
} else {
for (size_t child_id = 0;
@ -87,6 +87,11 @@ static void rec_build_module_fabric_dependent_chain_bitstream(
/* Find the child block that matches the instance name! */
ConfigBlockId child_block =
bitstream_manager.find_child_block(parent_block, instance_name);
VTR_LOGV(verbose,
"Try to find a configurable block corresponding to module "
"'%s' in FPGA fabric under its parent block '%s'\n",
instance_name.c_str(),
bitstream_manager.block_name(parent_block).c_str());
/* We must have one valid block id! */
VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
@ -94,7 +99,7 @@ static void rec_build_module_fabric_dependent_chain_bitstream(
rec_build_module_fabric_dependent_chain_bitstream(
bitstream_manager, child_block, module_manager, top_module,
child_module, config_region, fabric_bitstream,
fabric_bitstream_region);
fabric_bitstream_region, verbose);
}
}
/* Ensure that there should be no configuration bits in the parent block */
@ -534,7 +539,7 @@ static void build_module_fabric_dependent_bitstream(
const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib,
const BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
const ModuleManager& module_manager, const ModuleId& top_module,
FabricBitstream& fabric_bitstream) {
FabricBitstream& fabric_bitstream, const bool& verbose) {
switch (config_protocol.type()) {
case CONFIG_MEM_STANDALONE: {
/* Reserve bits before build-up */
@ -546,7 +551,7 @@ static void build_module_fabric_dependent_bitstream(
fabric_bitstream.add_region();
rec_build_module_fabric_dependent_chain_bitstream(
bitstream_manager, top_block, module_manager, top_module, top_module,
config_region, fabric_bitstream, fabric_bitstream_region);
config_region, fabric_bitstream, fabric_bitstream_region, verbose);
}
break;
@ -561,7 +566,7 @@ static void build_module_fabric_dependent_bitstream(
fabric_bitstream.add_region();
rec_build_module_fabric_dependent_chain_bitstream(
bitstream_manager, top_block, module_manager, top_module, top_module,
config_region, fabric_bitstream, fabric_bitstream_region);
config_region, fabric_bitstream, fabric_bitstream_region, verbose);
fabric_bitstream.reverse_region_bits(fabric_bitstream_region);
}
break;
@ -791,7 +796,7 @@ FabricBitstream build_fabric_dependent_bitstream(
/* Start build-up formally */
build_module_fabric_dependent_bitstream(
config_protocol, circuit_lib, bitstream_manager, top_block, module_manager,
top_module, fabric_bitstream);
top_module, fabric_bitstream, verbose);
VTR_LOGV(verbose, "Built %lu configuration bits for fabric\n",
fabric_bitstream.num_bits());