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[lib] update vtr

This commit is contained in:
tangxifan 2024-07-04 14:46:57 -07:00
parent f560fb8381
commit 6d798897fd
2 changed files with 2 additions and 1 deletions
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1
openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
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@ -261,6 +261,7 @@ static vtr::Matrix<size_t> add_top_module_connection_block_instances(
* We will skip those modules * We will skip those modules
*/ */
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", cb_type == CHANX ? "X-" : "Y-", ix, iy);
vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type), vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type),
rr_gsb.get_cb_y(cb_type)); rr_gsb.get_cb_y(cb_type));
if (false == rr_gsb.is_cb_exist(cb_type)) { if (false == rr_gsb.is_cb_exist(cb_type)) {

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit fbbf53d8207d55df8c6c62e1a0505f94ccba612a Subproject commit 19fa43cc62bf7a38e4151c1c3867a760ba683719