diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
index 3978339a2..2e7a33182 100644
--- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
+++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
@@ -261,6 +261,7 @@ static vtr::Matrix<size_t> add_top_module_connection_block_instances(
        * We will skip those modules
        */
       const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", cb_type == CHANX ? "X-" : "Y-", ix, iy); 
       vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type),
                                        rr_gsb.get_cb_y(cb_type));
       if (false == rr_gsb.is_cb_exist(cb_type)) {
diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing
index fbbf53d82..19fa43cc6 160000
--- a/vtr-verilog-to-routing
+++ b/vtr-verilog-to-routing
@@ -1 +1 @@
-Subproject commit fbbf53d8207d55df8c6c62e1a0505f94ccba612a
+Subproject commit 19fa43cc62bf7a38e4151c1c3867a760ba683719