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[Test] Deploy verilog default net wire type test case to CI

This commit is contained in:
tangxifan 2021-02-28 12:33:48 -07:00
parent 18a7041424
commit 6d419fed41
1 changed files with 3 additions and 0 deletions
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openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -101,6 +101,9 @@ run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --sh
echo -e "Testing implicit Verilog generation"; echo -e "Testing implicit Verilog generation";
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs
echo -e "Testing implicit Verilog generation";
run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire --debug --show_thread_logs
echo -e "Testing Verilog generation with flatten routing modules"; echo -e "Testing Verilog generation with flatten routing modules";
run-task fpga_verilog/flatten_routing --debug --show_thread_logs run-task fpga_verilog/flatten_routing --debug --show_thread_logs