diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
index acdf9a446..16226c299 100755
--- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
@@ -101,6 +101,9 @@ run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --sh
 echo -e "Testing implicit Verilog generation";
 run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs
 
+echo -e "Testing implicit Verilog generation";
+run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire --debug --show_thread_logs
+
 echo -e "Testing Verilog generation with flatten routing modules";
 run-task fpga_verilog/flatten_routing --debug --show_thread_logs