keep debugging the rr_graph generator. Definitely should rework the RREdge creation functions
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@ -370,21 +370,24 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ
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/* Check if x, y, type and ptc, side is valid */
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if ((x < 0) /* See if x is smaller than the index of first element */
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|| (size_t(x) > node_lookup_.dim_size(0) - 1)) { /* See if x is large than the index of last element */
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|| (size_t(x) > node_lookup_.dim_size(0) - 1) /* See if x is large than the index of last element */
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|| (0 == node_lookup_.dim_size(0))) { /* See if x is large than the index of last element */
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/* Return a zero range! */
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return RRNodeId::INVALID();
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}
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/* Check if x, y, type and ptc, side is valid */
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if ((y < 0) /* See if y is smaller than the index of first element */
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|| (size_t(y) > node_lookup_.dim_size(1) - 1)) { /* See if y is large than the index of last element */
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|| (size_t(y) > node_lookup_.dim_size(1) - 1) /* See if y is large than the index of last element */
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|| (0 == node_lookup_.dim_size(1))) { /* See if y is large than the index of last element */
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/* Return a zero range! */
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return RRNodeId::INVALID();
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}
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/* Check if x, y, type and ptc, side is valid */
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/* itype is always larger than -1, we can skip checking */
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if (itype > node_lookup_.dim_size(2) - 1) { /* See if type is large than the index of last element */
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if ( (itype > node_lookup_.dim_size(2) - 1) /* See if type is large than the index of last element */
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|| (0 == node_lookup_.dim_size(2))) { /* See if type is large than the index of last element */
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/* Return a zero range! */
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return RRNodeId::INVALID();
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}
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@ -399,7 +402,8 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ
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/* Check if x, y, type and ptc, side is valid */
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/* iside is always larger than -1, we can skip checking */
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if (iside > node_lookup_[x][y][type][ptc].size() - 1) { /* See if side is large than the index of last element */
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if ((iside > node_lookup_[x][y][type][ptc].size() - 1) /* See if side is large than the index of last element */
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|| (0 == node_lookup_[x][y][type][ptc].size()) ) { /* See if side is large than the index of last element */
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/* Return a zero range! */
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return RRNodeId::INVALID();
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}
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@ -857,7 +861,7 @@ RRNodeId RRGraph::create_node(const t_rr_type& type) {
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RREdgeId RRGraph::create_edge(const RRNodeId& source, const RRNodeId& sink, const RRSwitchId& switch_id) {
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VTR_ASSERT(valid_node_id(source));
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VTR_ASSERT(valid_node_id(sink));
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//VTR_ASSERT(valid_switch_id(switch_id));
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VTR_ASSERT(valid_switch_id(switch_id));
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/* Allocate an ID */
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RREdgeId edge_id = RREdgeId(num_edges_);
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@ -726,6 +726,9 @@ class RRGraph {
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/* top-level function to free, should be called when to delete a RRGraph */
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void clear();
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/* Due to the rr_graph builder, we have to make this method public!!!! */
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void clear_switches();
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public: /* Type implementations */
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/*
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* This class (forward delcared above) is a template used to represent a lazily calculated
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@ -776,7 +779,6 @@ class RRGraph {
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private: /* Internal free functions */
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void clear_nodes();
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void clear_edges();
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void clear_switches();
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void clear_segments();
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private: /* Graph Compression related */
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@ -15,7 +15,7 @@ class RouterDelayProfiler {
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const RouterLookahead* router_lookahead_;
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};
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vtr::vector<RRNodeId, float> calculate_all_path_delays_from_rr_node(int src_rr_node, const t_router_opts& router_opts);
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vtr::vector<RRNodeId, float> calculate_all_path_delays_from_rr_node(const RRNodeId& src_rr_node, const t_router_opts& router_opts);
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void alloc_routing_structs(t_chan_width chan_width,
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const t_router_opts& router_opts,
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@ -251,6 +251,11 @@ static void alloc_and_load_rr_switch_inf(const int num_arch_switches,
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const int wire_to_arch_ipin_switch,
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int* wire_to_rr_ipin_switch);
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static
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t_rr_switch_inf create_rr_switch_from_arch_switch(int arch_switch_idx,
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const float R_minW_nmos,
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const float R_minW_pmos);
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static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin);
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static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const t_arch_switch_fanin& switch_fanin);
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@ -704,6 +709,20 @@ static void build_rr_graph(const t_graph_type graph_type,
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/* END OPIN MAP */
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bool Fc_clipped = false;
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/* Draft the switches as internal data of RRGraph object
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* These are temporary switches copied from arch switches
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* We use them to build the edges
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* We will reset all the switches in the function
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* alloc_and_load_rr_switch_inf()
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*/
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device_ctx.rr_graph.reserve_switches(device_ctx.num_arch_switches);
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// Create the switches
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for (size_t iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) {
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const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(iswitch, R_minW_nmos, R_minW_pmos);
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device_ctx.rr_graph.create_switch(temp_rr_switch);
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}
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alloc_and_load_rr_graph(device_ctx.rr_graph.nodes().size(), device_ctx.rr_graph, segment_inf.size(),
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chan_details_x, chan_details_y,
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track_to_pin_lookup, opin_to_track_map,
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@ -732,13 +751,34 @@ static void build_rr_graph(const t_graph_type graph_type,
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}
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}
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/* First time to build edges so that we can remap the architecture switch to rr_switch
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* This is a must-do before function alloc_and_load_rr_switch_inf()
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*/
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device_ctx.rr_graph.rebuild_node_edges();
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/* Allocate and load routing resource switches, which are derived from the switches from the architecture file,
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* based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */
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alloc_and_load_rr_switch_inf(num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch);
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//Partition the rr graph edges for efficient access to configurable/non-configurable
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//edge subsets. Must be done after RR switches have been allocated
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device_ctx.rr_graph.rebuild_node_edges();
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//Save the channel widths for the newly constructed graph
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device_ctx.chan_width = nodes_per_chan;
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rr_graph_externals(segment_inf, max_chan_width,
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*wire_to_rr_ipin_switch, base_cost_type);
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/* Rebuild the link between RRGraph node and segments
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* Should be called only AFTER the function
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* rr_graph_externals()
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*/
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for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
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if ( (CHANX != device_ctx.rr_graph.node_type(inode))
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&& (CHANY != device_ctx.rr_graph.node_type(inode)) ) {
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continue;
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}
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short irc_data = device_ctx.rr_graph.node_cost_index(inode);
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short iseg = device_ctx.rr_indexed_data[irc_data].seg_index;
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device_ctx.rr_graph.set_node_segment(inode, RRSegmentId(iseg));
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}
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/* Essential check for rr_graph, build look-up and */
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if (false == device_ctx.rr_graph.validate()) {
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@ -749,12 +789,6 @@ static void build_rr_graph(const t_graph_type graph_type,
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"Fundamental errors occurred when validating rr_graph object!\n");
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}
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//Save the channel widths for the newly constructed graph
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device_ctx.chan_width = nodes_per_chan;
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rr_graph_externals(segment_inf, max_chan_width,
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*wire_to_rr_ipin_switch, base_cost_type);
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check_rr_graph(graph_type, grid, types);
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/* Error out if advanced checker of rr_graph fails */
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if (false == check_rr_graph(device_ctx.rr_graph)) {
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@ -922,6 +956,7 @@ static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_n
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}
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/* Create switches as internal data of RRGraph object */
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device_ctx.rr_graph.clear_switches();
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device_ctx.rr_graph.reserve_switches(device_ctx.rr_switch_inf.size());
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// Create the switches
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for (size_t iswitch = 0; iswitch < device_ctx.rr_switch_inf.size(); ++iswitch) {
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@ -930,6 +965,41 @@ static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_n
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}
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static
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t_rr_switch_inf create_rr_switch_from_arch_switch(int arch_switch_idx,
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const float R_minW_nmos,
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const float R_minW_pmos) {
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auto& device_ctx = g_vpr_ctx.mutable_device();
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t_rr_switch_inf rr_switch_inf;
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/* figure out, by looking at the arch switch's Tdel map, what the delay of the new
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* rr switch should be */
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double rr_switch_Tdel = device_ctx.arch_switch_inf[arch_switch_idx].Tdel(0);
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/* copy over the arch switch to rr_switch_inf[rr_switch_idx], but with the changed Tdel value */
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rr_switch_inf.set_type(device_ctx.arch_switch_inf[arch_switch_idx].type());
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rr_switch_inf.R = device_ctx.arch_switch_inf[arch_switch_idx].R;
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rr_switch_inf.Cin = device_ctx.arch_switch_inf[arch_switch_idx].Cin;
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rr_switch_inf.Cinternal = device_ctx.arch_switch_inf[arch_switch_idx].Cinternal;
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rr_switch_inf.Cout = device_ctx.arch_switch_inf[arch_switch_idx].Cout;
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rr_switch_inf.Tdel = rr_switch_Tdel;
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rr_switch_inf.mux_trans_size = device_ctx.arch_switch_inf[arch_switch_idx].mux_trans_size;
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if (device_ctx.arch_switch_inf[arch_switch_idx].buf_size_type == BufferSize::AUTO) {
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//Size based on resistance
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rr_switch_inf.buf_size = trans_per_buf(device_ctx.arch_switch_inf[arch_switch_idx].R, R_minW_nmos, R_minW_pmos);
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} else {
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VTR_ASSERT(device_ctx.arch_switch_inf[arch_switch_idx].buf_size_type == BufferSize::ABSOLUTE);
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//Use the specified size
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rr_switch_inf.buf_size = device_ctx.arch_switch_inf[arch_switch_idx].buf_size;
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}
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rr_switch_inf.name = device_ctx.arch_switch_inf[arch_switch_idx].name;
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rr_switch_inf.power_buffer_type = device_ctx.arch_switch_inf[arch_switch_idx].power_buffer_type;
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rr_switch_inf.power_buffer_size = device_ctx.arch_switch_inf[arch_switch_idx].power_buffer_size;
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return rr_switch_inf;
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}
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void load_rr_switch_from_arch_switch(int arch_switch_idx,
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int rr_switch_idx,
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int fanin,
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