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[FPGA-Verilog] Bug fix

This commit is contained in:
tangxifan 2021-10-09 21:34:07 -07:00
parent 7810f376c8
commit 6aa4991314
1 changed files with 3 additions and 1 deletions
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4
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
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@ -349,7 +349,9 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(s
BasicPort start_wl_sr_port(TOP_TB_START_WL_SHIFT_REGISTER_PORT_NAME, 1); BasicPort start_wl_sr_port(TOP_TB_START_WL_SHIFT_REGISTER_PORT_NAME, 1);
/* Reorganize the fabric bitstream by the same address across regions */ /* Reorganize the fabric bitstream by the same address across regions */
if (CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) { if ( (CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type())
&& (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type())
&& (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type()) ) {
MemoryBankShiftRegisterFabricBitstream fabric_bits_by_addr = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream, MemoryBankShiftRegisterFabricBitstream fabric_bits_by_addr = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream,
blwl_sr_banks, blwl_sr_banks,
fast_configuration, fast_configuration,