From 6aa4991314fd2c107969d4867ef21b1c41a99c2d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 9 Oct 2021 21:34:07 -0700 Subject: [PATCH] [FPGA-Verilog] Bug fix --- .../src/fpga_verilog/verilog_top_testbench_memory_bank.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp index b9eb69d96..581149d1b 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp @@ -349,7 +349,9 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(s BasicPort start_wl_sr_port(TOP_TB_START_WL_SHIFT_REGISTER_PORT_NAME, 1); /* Reorganize the fabric bitstream by the same address across regions */ - if (CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) { + if ( (CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) + && (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()) + && (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type()) ) { MemoryBankShiftRegisterFabricBitstream fabric_bits_by_addr = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream, blwl_sr_banks, fast_configuration,